[24mvd0019@mentorserver Exercise1]$ .

/run_scan_fix
/home/MGC/2021/tessent_2020/bin/tessent -shell -dofile solutions/insert_scan_fix.do
-log logs/insert_log_scan_fix.log -replace
// Tessent Shell 2020.4 Tue Dec 08 00:41:38 GMT 2020
// Copyright 2011-2020 Mentor Graphics Corporation
//
// All Rights Reserved.
//
// THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH
// IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS
// SUBJECT TO LICENSE TERMS.
//
// Mentor Graphics software executing under x86-64 Linux on Mon Feb 17 19:04:19
IST 2025.
// 64 bit version
// Host: mentorserver.vit.ac.in (128939 MB RAM, 8191 MB Swap)
//
Checkout succeeded: mtnslogicbist_c/3F1AD03FB75949766738
License file: [email protected]
License Server: [email protected]
// command: set_drc_handling s1 warn
// command: set_context dft -scan
// command: read_verilog design/gate_noscan.v
// command: read_cell_library libs/adk.atpg
// Reading DFT Library file libs/adk.atpg
// Finished reading file libs/adk.atpg
// command: set_current_design
// Note: Top design is 'I8051_ALL'.
// Warning: 1 case: Undriven net in netlist module
// Note: Issue set_current_design with the -show_elaboration_warnings option to
see more details about previous warnings
// command: add_clocks 0 clk
// command: add_clocks 0 rst
// command: set_test_logic -reset on
// command: check_design_rules
// Warning: Rule FN1 violation occurs 22 times
// Warning: Rule FN4 violation occurs 1341 times
// Flattening process completed, cell instances=14392, gates=19424, PIs=34,
POs=32, CPU time=0.07 sec.
// ---------------------------------------------------------------------------
// Begin circuit learning analyses.
// --------------------------------
// Learning completed, CPU time=0.09 sec.
// ---------------------------------------------------------------------------
// Begin scan chain identification process, memory elements = 1341,
// sequential library cells = 1341.
// ---------------------------------------------------------------------------
// ---------------------------------------------------------------------------
// Begin scannability rules checking for 1341 sequential library cells.
// ---------------------------------------------------------------------------
// 1317 sequential library cells identified as scannable.
// ---------------------------------------------------------------------------
// Begin scan clock rules checking.
// ---------------------------------------------------------------------------
// 2 scan clock/set/reset lines have been identified.
// All scan clocks successfully passed off-state check.
// 1317 sequential cells passed clock stability checking.
// Warning: There were 1 clock rule C6 fails (clock may capture data affected by
itself).
// ---------------------------------------------------------------------------
// 24 non-scan memory elements are identified.
// ---------------------------------------------------------------------------
// 24 non-scan memory elements are identified as INIT-X. (D5)
// ---------------------------------------------------------------------------
// ---------------------------------------------------------------------------
// Begin gating checking
// ---------------------------------------------------------------------------
// ---------------------------------------------------------------------------
// Checking reset for 24 non-scannable sequential instances
// ---------------------------------------------------------------------------
// 24 sequential instances can be gated to be scannable
// 0 sequential instances remain non-scannable
// Note: There were 24 S1 violations that will be fixed by adding test logic.
// ---------------------------------------------------------------------------
// Begin shift register identification for 1341 sequential library cells.
// ---------------------------------------------------------------------------
// No shift registers identified.
// Number of targeted sequential library cells = 1341
// command: report_drc_rules
C6: #fails=1 handling=warning (clock may capture data affected by itself)
D5: #fails=24 handling=warning (non-scan memory element)
S1: #fails=24 handling=warning (unstable nonscan cells when clocks off)
// command: set_scan_insertion_options -si_timing any_edge -so_timing any_edge -
single_clock_edge_chains off -single_clock_domain_chains off
// command: set_insertion_options -module_uniquification_suffix _scan#
// command: add_scan_mode unwrapped -chain_count 2 -port_index_start_value 1 -
port_scalar_index_modifier 1
// command: analyze_scan_chains
// Chain allocation of 'unwrapped' mode completed:
Distribution - populating 'unwrapped' chains: 100.0% completed (estimated time
remaining 0 secs)// 2 distributed chains of sizes ranging from 670 to 671
// command: insert_test_logic
=============================
Test Logic Insertion Summary:
=============================

Structural Data:
----------------
Added top-level port count: 4
Added instance count: 5

Logical Data:
-------------
Added clock control logic count: 1
Added scan chain count (unwrapped): 2

// Warning: Flattened model deleted.

// command: report_scan_chains

===============================
Scan Chains Created by the Tool
===============================

Scan mode 'unwrapped' scan chains:

----------------------------------
chain = chain1 group = dummy input = /ts_si[1] output = /ts_so[1] length
= 671
chain = chain2 group = dummy input = /ts_si[2] output = /ts_so[2] length
= 670

// command: write_design -output_file design/gate_scan.v -replace

// command: write_atpg_setup results/atpg -replace
INSERTION>
(gedit:32772): Gtk-WARNING **: Attempting to store changes into
`/home/userdata/24mvd0019/.local/share/recently-used.xbel', but failed: Failed to
create file '/home/userdata/24mvd0019/.local/share/recently-used.xbel.19E212': No
such file or directory

(gedit:32772): Gtk-WARNING **: Attempting to set the permissions of

`/home/userdata/24mvd0019/.local/share/recently-used.xbel', but failed: No such
file or directory