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Department of Electronics and Communication Engineering

Internal Test – II ANSWER KEY

Date 16.10.2023 Department ECE
Semester VII Class/section IV ECE
Duration 2:00 Hours Maximum marks 50
Course Code & Title: 20EC2E29 - TESTING OF VLSI CIRCUITS
Course Outcome Addressed
CO3 : Apply the techniques for designing VLSI circuits with testability.
CO4 : Apply the different techniques for self-test and fault diagnosis.

Q.No Questions
PART- A Answer all Questions (10x1 = 10 Marks)
1. The addition of ______ improves the observability.
a) adders b) multiplexers c) multipliers d) demultiplexers
2. In test mode, storage elements are connected as
a) parallel shift b) serial shift c) combiners d) buffers
registers registers
3. Signature analysis performs
a) multiplication b) addition c) polynomial d) subtraction
division
4. Fault diagnosis based on fault dictionaries can be characterized as
a) cause-effect b) effect-cause c) model-based d) random approach
analysis analysis reasoning
5. Self-checking technique consists of
a) supplying b) receiving c) supplying all d) all of the mentioned
coded input coded output possible input
data data sequence
6. Which is not the function of LSSD method?
a) eliminates b) eliminates races c) simplifies fault d) stores the data
hazards generation
7. The defect present in the following MOSFET is:

a) Logical stuck b) Logical stuck c) Physical d) Electrical Transistor stuck

at 1 at 0 defect open
8. In scan/set method Separate Register is used to implement a scan path.
9. ATPG stands for Automatic Test Pattern Generation
10. The parity check detection in self checking circuit is done using X-OR Gate
 PART – B (Short Answer Questions)
(Answer All Questions) ( 5 x2 = 10 Marks)
11. Outline the Design for Testability.
Design for testing or design for testability (DFT) consists of IC design techniques that add testability
features to a hardware product design. The added features make it easier to develop and apply
manufacturing tests to the designed hardware.

12. Summarize the important factors of Testability.

1. Controllability: Measure the ease of controlling a line ie., it can be set to any value.
2. Observability: Measure the ease of observing a line at a PO (primary output).

13. Compare the online and offline BIST.

Online BIST - testing occurs during normal functional operating conditions ie., the CUT is not
placed into a test mode where normal functions are locked.
Online BIST Techniques: Concurrent Online BIST and Nonconcurrent Online BIST
Offline BIST - testing a system when it is not carrying out its normal functions.
Two types: Functional offline BIST and Structural offline BIST.

14. Illustrate the principle of Ones count compression technique with an example.
In Ones count compression technique, the number of 1s in the raw output test response is counted and
obtained as signature output instead of the actual raw test response. This is illustrated with an
example as shown.

• C: single-output combinational circuit

• R: output response R = r1r2...rm
• Signature output = 1C(R) = No. of ones in R

15. List the advantages and disadvantages of Circular BIST.

Advantages of Circular BIST
• provides high fault coverage
• Low hardware overhead
Disadvantages
• Test patterns generated depend on the function of the circuit under test. Hence, if
certain patterns are not generated, then fault coverage may be less than that of a
conventional pseudorandom testing. However, it is possible to improve the fault
coverage by configuring the CFFs in a
partial scan path and applying deterministic test patterns via this path.
 • Another problem is the selection of FFs to be used as CFFs. Fewer the CFFs, lower
the overhead will be. But, smaller no. of CFFs may not allow generation of enough
random patterns to satisfy the fault coverage requirement.

PART – C (3x10 = 30 Marks)

16. Compulsory question:
Examine the clocking schemes for Partial Scan circuits and deduce the best method
which reduces multiple clock trees and extra clock signal routing efforts. (10)
Explanation for Scheme1 with diagram (2 marks)

Explanation for Sceme 2: (2 marks)

Advantages and Disadvantages of the above two schemes (1 Mark)

Explanation for Best method for redducing clocking efforts – (2+3 Marks)
 Answer any Two Questions
17. (i) With suitable diagram, explain how Adhoc designs are used to improve the testability of
digital circuits. (5)

Concept- 1 mark
● Adhoc testing refers to collections of ideas that are aimed at reducing the
combinational explosion of testing.
● Insert test points to increase controllability and observability.
▪ CP: Control Points – Primary inputs used to enhance controllability;
▪ OP: Observation Points – Primary outputs used to enhance
observability.
● To increase the testability, it is necessary to make nodes more accessible at some cost
by physically inserting more access circuits to the original design.
The different designs are as follows:
1) Insert Test points to improve controllability and Observability
2) Partition and Multiplexer techniques
3) Disable Internal Oscillators and Clocks
4) Avoid Asynchronous Logic and Redundant Logic
5) Avoid delay dependent logic
6) Avoid clock gating
7) Initialize sequential logic

Explanation of any 4 techniques ----- each 1 mark

1) Insert Test points to improve controllability and Observability
When a node has difficult access from primary inputs or outputs (pads of the circuit),
a very efficient method is to add internal pads.

2. Partition and Multiplexer techniques

With this design technique, the number of accessible nodes can be increased and
the number of test patterns can be reduced.
 3. Disable Internal Oscillators and Clocks
• To avoid synchronization problems during testing, internal oscillators and
clocks should be disabled.
• Disable =1

4. Avoid Asynchronous Logic and Redundant Logic

• Design and test of an asynchronous logic circuit are more difficult than for a
synchronous logic circuit. Its state transition times are difficult to predict.
• The operation of an asynchronous logic circuit is sensitive to input test
patterns, often causing race problems and hazards of having momentary signal values
opposite to the expected values.

(ii) Examine the boundary scan technique that is used to resolve the problem of
controlling and observing the input and output pins of chips employed in
assembling a system. (5)

Explanation with diagram (2+3 Marks)

18 (i) Describe the BEST BIST architecture with a neat block diagram. (5)
Explanation: 5 points 5 marks
• BEST is an application of Centralized and Separate BIST level design (CSBL) to
chips. In general, the logic being tested is a sequential circuit. The inputs to the CUT
are driven by a PRPG and the outputs are compressed using a MISR.
• Either a MUX can be used or the primary inputs may first be loaded into a PRPG and
then applied to the CUT. The same concepts apply to the outputs.

BEST BIST Architecture

• Both an embedded and a separate version of this architecture exist.

• For eg., if the primary inputs to the CUT go directly to registers and the primary
outputs are driven by registers, then an embedded BIST can be designed. ie,., these
IO registers may be modified for use as PRPG and MISR.
• Otherwise, the PRPG and MISR are to be added to the CUT which results in a
separate architecture. Here, PRPG and MISR can be made part of the boundary scan
registers.
Advantages:
• Hardware overhead is low.
Limitations:
• Extensive fault simulation is required to determine an acceptable balance between
fault coverage and test length.
• For some circuits, this technique can be ineffective in achieving the acceptable level
of fault coverage.
 (ii) Apply a totally self-checking k/2k checker circuit to realize a general k/n checker
with a neat circuit diagram. (5)

• Self-checking systems simplify fault diagnosis or detection. (1 mark)

• In self-checking systems, faults can be automatically detected by a subcircuit called a
checker. Such circuits imply the use of coded inputs.
• In some cases it may be possible to determine from the outputs of a circuit C
whether a certain fault f exists within the circuit without knowing the value of the
expected response. This type of testing, which can be performed "on-line" is based
on checking some invariant properties of the response. In this case, it is unnecessary
to test explicitly for f, and the circuit is said to be self-checking for f. Another
circuit, called a checker, can be designed to generate an error signal whenever the
outputs of C indicate the presence of a fault within C. It is desirable to design
circuits, including checkers, to be self-checking to as great an extent as possible
(i.e., for as many faults as possible).

Figure a: Totally self-checking k/2k checker (2 marks)

• For an arbitrary combinational circuit with p inputs and q outputs, all 2 input
combinations can occur, as can all 2° possible output combinations. If all possible
output combinations can occur, it is impossible to determine whether a fault is
present by just observing the outputs of the circuit, assuming no knowledge of the
corresponding inputs. However, if only k < 2° output configurations can occur
during normal operation, the occurrence of any of the 2° — k other configurations
indicates a malfunction (regardless of the corresponding input). Thus, faults that
result in such an "illegal" output can be detected by a hardware checker.

Figure b : A k/n checker design (2 marks)

19. (i) Describe the principle of circular BIST technique with a neat architecture. (5)
Circular BIST is a special form of BIST technique based on pseudorandom testing.
A simple configuration is as shown in Figure.
 Fig a. Circular BIST Architecture (1 mark)

Fig b. Circular Flipflop (1 mark)

Logical Module (LM) is the circuit under test without certain selected memory elements.
These memory elements are replaced by special flipflop cells called circular flipflops
(CFFs) .
A circular FF uses a 2:1 mux and an XOR gate. It can operate in 2 different modes: Functional
mode &
BIST mode.
Two special additional control lines can be incorporated into a CFF to provide four modes of
operation. Tables 1 & 2 reveals these modes.

Table 1: CFF Function table (1 mark)

 Modified CFF Circuit (1 mark)

Table 2: Modified CFF Function table (1 mark)

ii) An UUT is observed to have opens and defective components. Apply the principle of basic guided
probe testing technique to the UUT for faults diagnosis. (5)
Guided-probe testing extends an edge-pin testing process by monitoring internal signals in the
UUT via a probe which is moved (usually by an operator) following the guidance provided by the ATE.
The principle of guided-probe testing is to backtrace an error from the primary output where it has been
observed during edge-pin testing to its source (physical fault) in the UUT ( Fig.a). (1 mark)
Typical faults located by guided-probe testing are opens and defective components. An open
between two points A and B is identified by a mismatch between the error observed at B and the correct
value measured at the signal source A (fig b). (1 mark)
A faulty device is identified by detecting an error at one of its outputs, while only expected
values are observed at its inputs. (Fig c) ( 1 mark)
Unlike the fault-dictionary method, guided-probe testing is not limited to the SSF model. The
concept of "defective component" covers any type of internal device fault detected by the applied test;
this generality makes guided-probe testing independent of a particular fault model.
In addition to the applied stimuli and the expected response needed for edge-pin testing, ATE
supporting guided-probe testing also needs the expected values of all the internal lines accessible for
probing and the structural model of the UUT. Because the backtrace is guided by the structural model,
faults that create additional connections are inherently difficult to locate. For example, the faulty-device
diagnosis illustrated in Figure c would be incorrect had the error on the device output been caused by a
short. ( 1 mark)

( 1 mark)
Figure a) Backtracing errors b) identifying an open c) identifying faulty device

Course Instructor Programme Assessment Committee HoD

Dr.M.Jagadeeswari, Dr.H.Mangalam Dr.M.Jagadeeswari,
Prof. & Head Prof./ECE Prof & Head