The 8085 Microprocessor

Architecture

By
Prof. Priti Jain,
Mechatronics Dept, PIT.
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 The ALU
• In addition to the arithmetic & logic circuits, the ALU
includes the accumulator, which is part of every
arithmetic & logic operation.

• Also, the ALU includes a temporary register used for

holding data temporarily during the execution of the
operation. This temporary register is not accessible by
the programmer.
 The Flags register
– There is also the flags register whose bits are affected by the arithmetic &
logic operations.
• S-sign flag
– The sign flag is set if bit D7 of the accumulator is set after an
arithmetic or logic operation.
• Z-zero flag
– Set if the result of the ALU operation is 0. Otherwise is reset. This
flag is affected by operations on the accumulator as well as other
registers. (DCR B).
• AC-Auxiliary Carry
– This flag is set when a carry is generated from bit D3 and passed
to D4 . This flag is used only internally for BCD operations.
(Section 10.5 describes BCD addition including the DAA
instruction).
• P-Parity flag
– After an ALU operation if the result has an even # of 1’s the p-
flag is set. Otherwise it is cleared. So, the flag can be used to
indicate even parity.
• CY-carry flag
– Discussed earlier
Control Unit
Generates signals within uP to carry out the instruction,
which has been decoded. In
reality causes certain connections between blocks of the
uP to be opened or closed, so
that data goes where it is required, and so that ALU
operations occur.
Arithmetic Logic Unit
The ALU performs the actual numerical and logic
operation such as ‘add’, ‘subtract’,
‘AND’, ‘OR’, etc. Uses data from memory and from
Accumulator to perform
arithmetic. Always stores result of operation in
Accumulator.

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Registers
The 8085/8080A-programming model includes six
registers, one accumulator, and one flag register, as
shown in Figure. In addition, it has two 16-bit
registers: the stack pointer and the program counter.

The 8085/8080A has six general-purpose registers to

store 8-bit data; these are identified as B,C,D,E,H,
and L. They can be combined as register pairs - BC,
DE, and HL - to perform some 16-bit operations.
The programmer can use these registers to store or
copy data into the registers by using data copy
instructions.
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Program Counter (PC)
This 16-bit register deals with sequencing the execution of
instructions. This register is a memory pointer. Memory
locations have 16-bit addresses, and that is why this is a
16-bit register.

The microprocessor uses this register to sequence the

execution of the instructions.

The function of the program counter is to point to the

memory address from which the next byte is to be fetched.
When a byte (machine code) is being fetched, the program
counter is incremented by one to point to the next memory
location

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Stack Pointer (SP)
The stack pointer is also a 16-bit register used as a
memory pointer. It points to a memory location in
R/W memory, called the stack. The beginning of the
stack is defined by loading 16-bit address in the stack
pointer. The stack concept is explained
in the chapter "Stack and Subroutines."

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Instruction Register/Decoder
Temporary store for the current instruction of a
program. Latest instruction sent here from memory
prior to execution. Decoder then takes instruction
and ‘decodes’ or interprets the instruction. Decoded
instruction then passed to next stage.

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 Timing Diagram
• Following Buses and Control Signals
must be shown in a Timing Diagram:
• Higher Order Address Bus.
• •Lower Address/Data bus
• •ALE
• •RD
• •WR
• •IO/M
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 More on the 8085 machine
cycles
• The 8085 executes several types of instructions with
each requiring a different number of operations of
different types. However, the operations can be
grouped into a small set.
• The three main types are:
• Memory Read and Write.
• I/O Read and Write.
• Request Acknowledge.

• These can be further divided into various operations

(machine cycles).
Opcode Fetch Machine Cycle
• The first step of executing any instruction is the Opcode fetch
cycle.
– In this cycle, the microprocessor brings in the instruction’s
Opcode from memory.
• To differentiate this machine cycle from the very similar
“memory read” cycle, the control & status signals are set
as follows:
– IO/M=0, s0 and s1 are both 1.
– This machine cycle has four T-states.
• The 8085 uses the first 3 T-states to fetch the opcode.
• T4 is used to decode and execute it.
– It is also possible for an instruction to have 6 T-states in an
opcode fetch machine cycle.
Memory Read Machine Cycle
• The memory read machine cycle is
exactly the same as the opcode fetch
except:
– It only has 3 T-states
– The s0 signal is set to 0 instead.
The Memory Read Machine
Cycle
– To understand the memory read machine cycle, let’s study
the execution of the following instruction: 2000H 3E
• MVI A, 32 2001H 32
– In memory, this instruction looks like:
• The first byte 3EH represents the opcode for loading a
byte into the accumulator (MVI A), the second byte is the
data to be loaded.
– The 8085 needs to read these two bytes from memory before
it can execute the instruction. Therefore, it will need at least
two machine cycles.
– The first machine cycle is the opcode fetch discussed
earlier.
– The second machine cycle is the Memory Read Cycle.
– Figure 3.10 page 83.
Machine Cycles vs. Number of bytes in the instruction
• Machine cycles and instruction length, do not
have a direct relationship.
– To illustrate lets look at the machine cycles
needed to execute the following instruction.
• STA 2065H
• This is a 3-byte instruction requiring 4 machine cycles and 13
T-states. 32H 2010H
• The machine code will be stored 65H 2011H
in memory as shown to the right 20H 2012H

• This instruction requires the following 4 machine cycles:

– Opcode fetch to fetch the opcode (32H) from location 2010H, decode it and
determine that 2 more bytes are needed (4 T-states).
– Memory read to read the low order byte of the address (65H) (3 T-states).
– Memory read to read the high order byte of the address (20H) (3 T-states).
– A memory write to write the contents of the accumulator into the memory
location.
The Memory Write Operation
• In a memory write operation:
– The 8085 places the address (2065H) on
the address bus
– Identifies the operation as a memory write
(IO/M=0, s1=0, s0=1).
– Places the contents of the accumulator on
the data bus and asserts the signal WR.
– During the last T-state, the contents of the
data bus are saved into the memory
location.
 Memory interfacing
• There needs to be a lot of interaction between the
microprocessor and the memory for the exchange of
information during program execution.
– Memory has its requirements on control signals
and their timing.
– The microprocessor has its requirements as well.

• The interfacing operation is simply the matching of

these requirements.
 Memory structure & its requirements
ROM
Data Lines

RAM
Input Buffer WR

Address CS Address CS
Lines Lines

Output Buffer RD Output Buffer RD

Data Lines
Date
Lines

• The process of interfacing the above two chips is the

same.
– However, the ROM does not have a WR signal.
 Interfacing Memory
– Accessing memory can be summarized into the following
three steps:
– Select the chip.
– Identify the memory register.
– Enable the appropriate buffer.

– Translating this to microprocessor domain:

– The microprocessor places a 16-bit address on the
address bus.
– Part of the address bus will select the chip and the
other part will go through the address decoder to
select the register.
– The signals IO/M and RD combined indicate that a
memory read operation is in progress. The MEMR
signal can be used to enable the RD line on the
memory chip.
 Address decoding
• The result of address decoding is the identification of
a register for a given address.
– A large part of the address bus is usually
connected directly to the address inputs of the
memory chip.
– This portion is decoded internally within the chip.
– What concerns us is the other part that must be
decoded externally to select the chip.
– This can be done either using logic gates or a
decoder.
 The Overall Picture
• Putting all of the concepts together, we
get:
Chip Selection
A15- A10 Circuit

8085
CS
A15-A8

ALE
A9- A0 1K Byte
AD7-AD0 Latch Memory
A7- A0 Chip

WR RD IO/M D7- D0
RD WR