SYNTHESIS

EDA Tool: Design Compiler (DC)

Number of ports: 114
Number of cells: 3780
Technology Node: 32nm

Synthesis is the process of transforming technology-independent RTL code into

a technology-dependent gate-level netlist.
• All transformations and optimizations during synthesis are logical.
• During the synthesis process, all clocks are considered ideal because clock
tree synthesis has not yet been completed, and interconnect delays are not
realistic.
• Hold checks are not considered in synthesis because the clock is ideal and
interconnect delays are not realistic
• During synthesis, focus primarily on optimizing the data path and ensuring
that the combinational logic between the registers meets the setup timing
requirements.

Input and Output files

RTL Files
Reports
Constraints
SYNTHESIS
Reference Gate-level netlist
Libraries

Parasitic Files
 Stages in the synthesis process

Reading Files and

elaboration

Translation

Logical Optimization

Logical Mapping

Gate-level netlist

Reading Files
• We need to provide the essential files for the synthesis process, including the
RTL code, required reference libraries, design constraints, and parasitic
models.
• After reading these files, we need to check for any design mismatches and
then proceed with the elaboration process.
• In the elaboration process of synthesis, the tool takes the RTL description and
translates it into a more concrete representation, preparing it for
optimization and technology mapping.
• Elaborate builds WV Gtech modules for the specified top and its sub modules.
Translation
• In the translation process, the RTL code is converted into a represented
Boolean equation and then mapped to Gtech cells (generic technology).
• Gtech cells are a technology-independent logical representation of basic
digital logic gates.
• Gtech cells enable synthesis to optimize design before binding to specific
technology nodes (32nm, 14nm).
• These Gtech cells are not part of the final synthesis; they only exist in the
intermediate process of synthesis.

Logical Optimization
• After the translation process, the synthesis tool will perform logical
optimization on the design mapped to gtech cells, focusing on timing, area,
and power based on the given constraints.

Logical Mapping
• After logical optimization, the synthesis tool will map the design to standard
cells from the technology library.
• These cells are technology-dependent and correspond to various nodes like
32nm and 14nm.
 Synthesis using Design compiler tool

EDA Tool: Design compiler (Synopsys)

Technology Node: 32 nm technology node

Inputs and output files for Design Compiler

Technology file (.tf)

RTL Code (.v)

Reference Libraries (mw_libs)

Link library (.db) Gate-level netlist (.v)

DC Compiler
Target Library (.db)

Constraints (sdc)

Parasitic file (.tlu / .nxtgrd)

Sourcing all necessary libraries for the design compiler

1. Technology file (.tf):

set tech_file \
"../../main_project_phase1/libs/tech_files/saed32nm_1p9m_mw.tf"

• Reference libraries

set mw_ref_libs "../../main_project_phase1/libs/mw_libs/saed32_io_fc

../../main_project_phase1/libs/mw_libs/saed32nm_lvt_1p9m"

set synthetic_library dw_foundation.sldb

• Link Library

set link_library
"../../main_project_phase1/libs/standard_cell_libs/saed32lvt_ff1p16v125
c.db \
../../main_project_phase1/libs/standard_cell_libs/saed32io_fc_ff1p16v12
5c_2p75v.db $synthetic_library"

• Target Library
set target_library
"../../main_project_phase1/libs/standard_cell_libs/saed32lvt_ff1p16v125
c.db "

Parasitic Files(.tluplus)
set_tlu_plus_files \
-max_tluplus
../../main_project_phase1/libs/tlu_files/saed32nm_1p9m_Cmax.tluplus
\
-min_tluplus
../../main_project_phase1/libs/tlu_files/saed32nm_1p9m_Cmin.tluplus
\
-tech2itf_map
../../main_project_phase1/libs/tlu_files/saed32nm_tf_itf_tluplus.map

Creating Milkyway Library

file delete -force $my_mw_lib

create_mw_lib $my_mw_lib -technology $tech_file -mw_reference_library\

$mw_ref_libs -open

Reading RTL Files

analyze -format verilog [glob \

../../main_project_phase1/rtl/msrv32_integer_file.v]

elaborate msrv32_integer_file

current_design msrv32_integer_file
• Elaboration Process
Sourcing the Constraint Files (.sdc)

source -echo ../../scripts/constraints.sdc

Synthesis Stages Using the [compile_ultra] Command in Design Compiler

The compile_ultra command in Synopsys Design Compiler performs high-

performance, timing-driven synthesis by optimizing logic at multiple levels. It follows a
structured synthesis process, ensuring timing, area, and power constraints are met
efficiently.

compile_ultra -no_autoungroup -no_boundary_optimization -self_gating

Results and Reports

###################### results ################################

write_file -format verilog -hierarchy -output ../dc_results/integer.v

write_sdc ../dc_results/integer.sdc

write_parasitics -output ../dc_results/integer.spef

############################ reports ###########################

report_timing > ../dc_reports/timing.txt

report_cell > ../dc_reports/cell_count.txt

report_area > ../dc_reports/area.txt

report_power > ../dc_reports/power.txt

BLOCK DIAGRAM

Circuit Diagram
Gate-level netlist file (.v)

Checks after Synthesis

1. Functional equivalence check (formal verification)

• Verify whether the functionality of the RTL code matches that of the
gate-level netlist.
• By using tools such as "Formality" from Synopsys and "Conformal"
from Cadence, etc.

2. Timing Checks (setup)

• Check the timing regarding setup violations to ensure the design meets
our timing constraints.
• By using command [report_timing -delay_type max].
3. Power Analysis
• Estimate the dynamic and static power consumption after the
synthesis process.
• Ensure power meets design constraints.
• By using command report_power.

4. Area report checks

• To ensure that the synthesized design cell count fits within given area
constraints
• otherwise, we need to determine if further optimization is necessary.
• By using command report_area.

5. DRC (Design rule checks)

• Checking whether the synthesized design follows design rules is not.
• By using command check_design.

6. Checks for Multi-voltage and power domans (if used)

• Verifying the insertion of level shifters, isolation, and power gating cells
for multi-voltage designs.
• Ensure correct power domain crossing.
• Verifies low-power techniques (clock-gating, power-gating).

Report_timing (no timing violations)

Report_area

Report_power