Clipping and Clamping Circuits

AIM: To design and test diode clipping circuits for peak clipping and peak detection (both
Single ended and double ended circuits).

COMPONENTS/APPARTUS REQUIRED:
Required material Specification Qty
Bread board 1
CRO 20/30Mhz 1
Power supply DC +/- 12V/0-30V 2
Function Generator 1MHz 1
Resistors 1K, 470 2
Diodes IN4007 2

i) DIODE SHUNT CLIPPING above reference voltage.

(Positive peak clipping)

EXPECTED WAVEFORM:

Vo Vin
V0
(v)
Vref(v)
DESIGN:

Let the output voltage be clipped to say +2.8V i.e. V0 (max) = 2.8V
But V0 (max) = Vdiode + V ref
Vdiode= Diode forward voltage drop=0.7V
Vref=V0(max)-Vd=2.0.7=2.1V.
The value of resistor R is chosen to be R= Vi (max) – V0 (max)/ Id
Choose Diode forward current, Id = 1.5mA (Typically between 1mA to 10 mA)
Then R= (4 - 2.8) / 1.5mA = 800 Ω ≈ 1K Ω

THEORY:

Clipper circuits are used to remove the portion of a time varying input signal without distorting the
remaining part of the input waveform.

The circuit is as shown above. During positive half cycle of the input voltage (Vin) till Vin
<Vref the diode will not conduct. But when Vin =Vref, the diode will conduct & Vo=Vd+Vr. Throughout
the negative half cycle the diode is reversed biased and act an open circuit.Therefore Vo =Vin , thus the
waveform is as shown below in figure.

ii)DIODE SHUNT CLIPPING below reference voltage

(Negative peak clipping)

CIRCUIT
DIAGRAM:
DESIGN:

Let the output voltage be clipped to say -2.8V i.e V0(min) = -2.8V
But V0 (min) = -(Vdiode + V ref )
Vdiode= Diode forward voltage drop=0.7V
-Vref=V0(min) + Vd = -2.8 + 0.7= -2.1V.

The value of resistor R is chosen to be R= Vi (max) – V0 (min)/Id

Choose Diode forward current, Id = 1.5mA (Typically between 1mA to 10 mA)
Then R= (-4 + 2.8) / -1.5mA = 800 Ω ≈ 1K Ω

THEORY:

The circuit is as shown above. During positive half cycle the diode will be reversed
biased, hence Vo =Vin. Thus entire positive half cycle is reproduced as it is, when Vin<Vref,
the diode becomes forward biased & hence Vo=-(Vr+Vd).

EXPECTED WAVEFORM:

▲
VO(V)

Vref VoutVo

-2.8V
Vin
i)DIODE SERIES CLIPPING( above reference voltage_)
(Positive peak clipping)
CIRCUIT DIAGRAM:

EXPECTED WAVEFORM:

Vi
Vo(v)
2V
Vo
t sec

Fig 8: Output waveform

DESIGN:

Let the output voltage be clipped to say +2.0V i.e. V0 (max) = V ref = +2.0V
The value of resistor R is chosen to be R= Vi (max) – V0 (max)/Id
Choose Diode forward current, Id = 2mA (typically between 1mA to 10 mA)
Then R= (4 - 2) / 2mA = 1K Ω
ii) DIODE SERIES CLIPPING below reference voltage
(Negative peak clipping)

CIRCUIT DIAGRAM:

DESIGN:

Let the output voltage be clipped to say -2.0V i.e V0(min) = V ref = -2.0V

The value of resistor R is chosen to be R= (Vi (max) + V0 (min)) / Id

Choose Diode forward current, Id = 6mA (Typically between 1mA to 10 mA)
Then R= (4 + 2) / 6mA = 1K Ω

EXPECTED WAVEFORM:

Vo (v)
▲

►t sec
 i) CLIPPING AT TWO INDEPENDENT LEVELS
CIRCUIT
DIAGRAM:

DESIGN:

To obtain a slice of input voltage between 1V and 3.5V Let Vref1 > Vref2
Since V0(max) = 3.5V
But V0 (max) = Vdiode + V ref1
Vdiode= Diode forward voltage drop=0.7V Vref1=V0(max)-Vd=3.5-0.7=2.8V.
Since V0(min) = 1V
But V0 (min) = Vref2 - V diode
Vdiode= Diode forward voltage drop=0.7V Vref2=V0(min)+Vd=1 .0 +0.7=1.7V.
The value of resistor R is chosen to be R= (Vi (max) – V0 (max)) / Id
Choose Diode forward current, Id = 1mA (Typically between 1mA to 10 mA)
Then R= (4 – 3.5) / 1mA = 500 Ω ≈ 470Ω.
EXPECTED WAVEFORM:

Vo(v) ▲

Vi
3.5V Vo
1V ►t se c
 DOUBLE ENDED CLIPPER (Symmetrical square wave generator)

CIRCUIT DIAGRAM:

DESIGN:

To generate a symmetrical square wave of ±3V

i.e. V0 (max) = +3V and V0 (min) = -3V

But V0 (max) = Vdiode + V ref1

Vdiode= Diode forward voltage drop=0.7V Vref1=V0(max)-Vd=3.0 – 0.7=2.3V.

But V0 (min) = Vdiode + V ref2

Vdiode= Diode forward voltage drop=0.7V Vref2=V0(min)-Vd=3.0 – 0.7=2.3V.

The value of resistor R is chosen to be R= (Vi (max) – V0 (max)) / Id

Choose Diode forward current, Id = 1mA (Typically between 1mA to 10 mA)
Then R= (4 - 3) / 1mA = 1K Ω.

EXPECTED WAVEFORM:
 v)Vo(
Vi
3V
Vo

t sec

-3V

Fig 17: Output waveform

PROCEDURE: (Same for all the clipper circuits)

1)Double click on proteus 8 Professional software,select new project.

2)In New project pick devices related to circuit diagram.
3)Rig up the circuit as shown in the circuit diagrams.
4)Apply a sinusoidal signal of 1KHz and amplitude of 8Vp-p ( Peak amplitude should be
greater than clipping level) at input Vi.
5)Observe output signal on the CRO and verify it with the given waveform.

Result:

The clipping circuits are designed and output waveforms are verified.

Clamping Circuit
Positive peak or negative clamping:

DESIGN:
 To design a Clamper circuit to clamp negative peak of the output voltage at 3V
Vo (max) = Vref + Vd = 3V
Vref = Vo (max) - Vd
To Clamp Positive peak at +3V, Vref = 3 0.7 = 2.3V Given Frequency = 1 KHz, T=1/f=
1ms.
Choose RC >> T (so that tilt in the waveform is negligible, ie, C does not discharge)
Let RC = 10T = 10 X 1ms = 10ms
Choose C = 1µF, R = 10ms/1µ = 10KΩ

2] Negative peak or positive clamping:

DESIGN: To design a clamper circuit to clamp positive peak at 3V.
Vo (min) = - (Vref + Vd)
Vref = -Vo(min) + Vd Vref = -3 + 0.7 = -2.3V
Given Frequency = 1 KHz, T = 1ms.
Choose RC >> T (so that C does not discharge during positive half cycle ) Let RC = 10T = 10ms
Let C = 1 µF, R = 10ms/1 µ = 10KΩ

Expected Waveform

THEORY:

CLAMPER:The circuits which add a dc voltage to the ac input signal are called
clamper circuits. The clamper circuits are also called as DC restorer or DC inserter
circuits.Clampers are classified into two types:Negative clamper and positive clamper.

PROCEDURE:

1. Double click on proteus 8 Professional software,select new project.

2. In New project pick devices related to circuit diagram.
3. Rig up the circuit as shown in the circuit diagrams.
4. Apply a sinusoidal signal of 1KHz and amplitude of 12Vp-p ( Peak amplitude of input
 signal must be greater than clamping level)
5. Connect the output to CRO in DC Mode and compare the output with the given
6. waveforms.
7. Make Vref = 0V and observe that the corresponding peak is clamped to ±0.7V.

RESULT:

Clamped waveform at desired level is obtained and clamping circuits are studied.