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2043 1097 DOC Verilog Session 2

The document provides an overview of Verilog HDL syntax and semantics, including rules for comments, identifiers, and string representation. It explains number representation in Verilog, detailing sized and unsized numbers, base formats, and special values like 'x' and 'z'. Additionally, it outlines the structure of a Verilog module, including input/output declarations and behavioral statements.

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MADHU C S26
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13 views14 pages

2043 1097 DOC Verilog Session 2

The document provides an overview of Verilog HDL syntax and semantics, including rules for comments, identifiers, and string representation. It explains number representation in Verilog, detailing sized and unsized numbers, base formats, and special values like 'x' and 'z'. Additionally, it outlines the structure of a Verilog module, including input/output declarations and behavioral statements.

Uploaded by

MADHU C S26
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Verilog HDL Design [Session-2]

• Syntax & Semantics


• Comments

Verilog® HDL • Strings


• Identifiers
• Number Representation
• System Representation

Verilog HDL IIT Guwahati 1


Syntax & Semantics
The basic lexical convention used by Verilog HDL are similar to those in C programming
▪All keywords must be in LOWER case i.e. the language is case sensitive
▪White spaces makes code more readable but are ignored by compiler
▪Blank space(\b) , tabs(\t) , newline(\n) are ignored by the compiler
▪White spaces are not ignored by the compiler in strings
▪Comments
// single line comment style
/* multi line
comment style */
Nesting of comments not allowed
▪Each identifier including module name, must follow these rules
- It must begin with alphabet (a-z or A-Z) or underscore “_”.
- It may contain digits, dollar sign ( $ ).
- No space is allowed inside an identifier.

Verilog HDL IIT Guwahati 2


Syntax & Semantics
String
▪A string is a sequence of characters that are enclosed by double quotes.
▪Restriction on the string is that it must be contained on a single line only.
▪Strings are treated as a sequence of one – byte ASCII values.

E.g. “Hello Verilog HDL” // is a string

Identifiers
Identifiers are names given to objects so that can be referenced in the design.
▪Identifiers are made up of alphanumeric characters, the underscore( _ ) and dollar sign ( $ ).
▪Identifiers start with an alphanumeric character or an underscore.

E.g. reg value // value is an identifier

Verilog HDL IIT Guwahati 3


Syntax & Semantics

Escaped Identifiers
▪If a keyword or special character has to be used in an identifier, such an identifier must be preceded by
the backslash ( \ ) character and terminate with whitespace (space, tab, or newline).

▪All characters between backslash and whitespace are processed literally.

▪Any printable ASCII character can be included in escaped identifiers.

▪The backslash or whitespace is not considered a part of the identifier.

E.g. \reg //Keyword used


\valid! //Special character used

Verilog HDL IIT Guwahati 4


Number Representation

▪Two types of number specifications:

- Sized
<size>’<base format><number> e.g. 3’b101

- Unsized
’<base format><number> e.g. ’b101

▪Size: Specified in decimal only and represents NUMBER Of BITS in number. Unsized numbers default to a
compiler specific number of bits ( at least 32 bits ).

Verilog HDL IIT Guwahati 5


Number Representation

▪Base Format:
Represent the radix. Legal base formats are decimal (‘d or ‘D), hexadecimal (‘h or ‘H), binary (‘b or ‘B)
and octal (‘o or ‘O). Numbers, specified without a <base format> specification are decimal numbers by
default.

▪Number:
The number is specified as consecutive digits from 0,1,2,3,4,5,6,7,8,9,a,b,c,d,e,f. Only a subset of
these digits is legal for a particular base.
“Uppercase letters are legal for number specification.”

Verilog HDL IIT Guwahati 6


Number Representation

▪Negative numbers:
Negative numbers can be specified by putting a minus sign before the size for a constant number.
Size constants are always positive.

It is illegal to have a minus sign between < base format > and < number >.

E.g.

-6’d3 // 6 bit negative number stored as 2’s complement of 3


4’d-2 // illegal representation

Verilog HDL IIT Guwahati 7


Number Representation

▪X or Z values:
Verilog has two symbols for unknown and high impedance values. An unknown value is denoted by an
‘x’. A high impedance value is denoted by ‘z’.
▪‘x’ or ‘z’ sets –
4 bits for a number in hexadecimal base.
3 bits for a number in octal base.
1 bit for a number in binary base.
▪If MSB of a number is 0, x, z the number is automatically extended to fill the most significant bits,
respectively, with 0, x, z.
▪If the MSB is 1, then it is also zero extended.

Verilog HDL IIT Guwahati 8


Number Representation
▪When the size is less than the number specified, upper bits are truncated. E.g. 4’b11110000 is actually
“0000”.
▪When the size is larger than the number specified, then the number is extending with leading zero’s.
▪If MSB bits are either X or Z then number specified, then the number is extended with leading X or Z to fill
the size.

e.g. 8’b1111 = “00001111”


e.g. 8’bx111 = “xxxxx111”
e.g. 8’bz111 = “zzzzz111”
Note:
Always specify a width for a literal value when inferring hardware.
i.e. whenever representing numbers for any purpose in Verilog.
Always specify the correct size.

Verilog HDL IIT Guwahati 9


Number Representation

▪Underscore characters
▪An underscore character “_” is allowed anywhere in a number except the first character.
▪They are used only to increase readability and are ignored by Verilog.

E.g.

12’b1111_0000_1010 //use of underline characters

Verilog HDL IIT Guwahati 10


Number Representation

▪Question Marks:
▪A question mark “?” is Verilog HDL alternative for z in the context of numbers.
▪The ? Is used to enhance readability in the “casex” and “casez” statements.

- In casex and casez, all “z” values are treated as don’t care. Hence, to distinguish “z” in these
statements “?” is used.

- “?” is also used in context to the UDP with some different meaning.

Verilog HDL IIT Guwahati 11


Number Representation

Number Size Binary Equivalent


8’H FZ 8 Bit hex 8’b1111_ZZZZ
9’bX101 9 bit binary 9’bX_XXXX_X101
7’b1Z101 7 bit binary 7’b001_Z101
‘o7 Unsized octal 0…00111(32-bits)
6’hF0 6 bit hex 110000(truncated)
‘d10 Unsized decimal 0…01010(32-bits)

Note: The size ALWAYS means the TOTAL NUMBER of bits in the number and has nothing to
do with the base specified.

Verilog HDL IIT Guwahati 12


System Representation
Module Name,
Port List, Port Declarations
Parameters
Declarations of wire, regs and Data flow statements (assign)
other variables

Instantiation of lower-level Always and Initial blocks.


modules All behavioral statements go in
these blocks

Tasks and functions

endmodule statement

Verilog HDL IIT Guwahati 13


System Representation

module mux_4x2 (y,s1,s0,a,b,c,d);


Input [1:0]a,b,c,d,s1,s0;
Output [1:0]y;
reg [1:0] y;
always @(a or b or c or d or sel)
begin
case (sel)
2’b00: y = a;
2’b00: y = b;
2’b00: y = c;
2’b00: y = d;
default: y = 2’bx;
endcase
end
endmodule

Verilog HDL IIT Guwahati 14

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