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UNIT 3b

This document discusses various programmable microprocessor interfaces, including the 8255, 8253/54, 8251, and 8259, along with an overview of Direct Memory Access (DMA) and its controller. It explains the functionality of the 8255 as a parallel data transfer interface, the operation of the DMA controller with its registers, and the role of the 8259 as a Programmable Interrupt Controller to manage multiple interrupts. Key features and operational details of these components are also outlined.

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18 views54 pages

UNIT 3b

This document discusses various programmable microprocessor interfaces, including the 8255, 8253/54, 8251, and 8259, along with an overview of Direct Memory Access (DMA) and its controller. It explains the functionality of the 8255 as a parallel data transfer interface, the operation of the DMA controller with its registers, and the role of the 8259 as a Programmable Interrupt Controller to manage multiple interrupts. Key features and operational details of these components are also outlined.

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u041907
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UNIT-3

Programmable
Microprocessors Interfaces: 8255,
8253/54, 8251, 8259,
Overview of DMA &
DMA controller, ADC
and DAC interfacing
8255 is a programmable I/O device that acts as interface between peripheral devices
and the microprocessor for parallel data transfer.
Direct memory access (DMA) is a method that allows an
input/output (I/O) device to send or receive data directly to or
from the main memory, bypassing the CPU to speed up
memory operations. The process is managed by a chip known
as a DMA controller.
Each of four channels of 8257 has a pair of two registers,

1.DMA address register: The function of this register is to


store the address of the starting memory location, which
will be accessed by the DMA channel.

2. Terminal count register: The terminal count register are


initialized with the binary equivalent of the number of
required DMA cycles. After each DMA cycle, the terminal
count register content will be decremented by one and finally
it becomes zero after the required number of DMA cycles are
over.
Priority Resolver:

The priority resolver resolves the priority of the four DMA channels
depending upon whether normal priority or rotating priority is
programmed. When the fixed priority mode (normal) is selected, then
DRQ0 has the highest priority and DRQ3 has the lowest priority among
them.

Data Bus Buffer (D7 to D0)

These are bidirectional, data lines which are used to interface the system
bus with the internal data bus of DMA controller. In the Slave mode, it
carries command words to 8257 and status word from 8257. In the master
mode, these lines are used to send higher byte of the generated address to
the latch. This address is further latched using ADSTB signal.
HRQ: it is connected with HOLD input of the CPU.
ADSTB: Address Strobe Output Signal (like ALE signal 0f 8085)

This signal is used to convert the higher byte of the memory address generated by the
DMA controller into the latches.
Chip-Select

This is an active-low chip select line that enables the read/write operations from/to
8257, in slave mode. In the master mode, it is automatically disabled to prevent he
chip from getting selected (by CPU) while performing the DMA operation.

READY

This is an active-high asynchronous input used to stretch memory read and write
cycles of 8257 by inserting wait states. This is used while interfacing slower
peripherals.
What is PIC 8259?

The Intel 8259 is a Programmable Interrupt Controller (PIC) designed for


the Intel 8085 and Intel 8086 microprocessors. It is used to increase the
number of interrupts.

Why is it required?

8085 have 5 hardware interrupts whereas 8086 have only 2 hardware


interrupts. For systems requiring more interrupt, 8259 controller can be
used to increase the number of interrupts.
Features of 8259
 The Intel 8259A Programmable Interrupt Controller handles up to eight
vectored priority interrupts for the CPU.
 It is cascadable for up to 64 vectored priority interrupts without additional
circuitry
 It is packaged in a 28-pin DIP, requires +5V power supply.
 No Clock is required.
 Can be programmed to accept Level Triggered as well as Edge Triggered
Interrupt Signals.
 Can be programmed to mask individual interrupt request.
 Status of Pending Interrupts, In-Service Interrupts and Masked Interrupts
can be obtained by reading status word register.
BLOCK DIAGRAM OF PIC 8259

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