RV Institute of technology and Management

Rashtreeya Sikshana Samithi Trust's

Rashtreeya Vidyalaya Institute of Technology and Management
(RVITM), Bengaluru

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

SEMESTER-III

Course code: BEC302

Course Name: DIGITAL SYSTEM DESIGN USING VERILOG LAB

Prepared by

Dr. Shalini Shravan, Assistant Professor

Dept. of E & C Engineering, RVITM, Bengaluru

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CONTENTS

EXPERIMENTS

1.
To simplify the given Boolean expressions and realize using Verilog program

2.
To realize Adder/Subtractor(Full/half)circuits using Verilog data flow description.

3. To realize 4-bit ALU using Verilog program.

4. To realize the following Code converters using Verilog Behavioral description
a)Gray to binary and vice versa b)Binary to excess3 and vice versa
5.
To realize using Verilog Behavioral description:8:1mux, 8:3encoder, Priority encoder

6. To realize using Verilog Behavioral description:1:8Demux, 3:8 decoder,2 –bit Comparator

7. To realize using Verilog Behavioral description: Flip-flops:
a)JK type b)SR type c)T type and d)D type

8. To realize Counters-up/down (BCD and binary)using Verilog Behavioral description.

Demonstration Experiments (For CIE only–not to be included for SEE)

Use FPGA/CPLD kits for down loading Verilog codes and check the output for interfacing
experiments.
1. Verilog Program to interface a Stepper motor to the FPGA/CPLD and rotate the motor
in the specified direction (by N steps).
Verilog programs to interface Switches and LEDs to the FPGA/CPLD and demonstrate
2. its working.

Software Tools: Xilinx ISE Design Suite 13.1 Hardware:

Spartan 6 FPGA Development Board

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Verilog :

Verilog is a hardware description language (HDL) used to model electronic systems. The language supports the
design, verification, and implementation of analog, digital, and mixed - signal circuits at various levels of
abstraction The designers of Verilog wanted a language with syntax similar to the C programming language so
that it would be familiar to engineers and readily accepted. The language is casesensitive, has a preprocessor like
C, and the major control flow keywords, such as "if" and "while", are similar. The formatting mechanism in the
printing routines and language operators and their precedence are also similar.
The language differs in some fundamental ways. Verilog uses Begin/End instead of curly braces to
define a block of code. The concept of time, so important to a HDL won't be found in C The language differs
from a conventional programming language in that the execution of statements is not strictly sequential. A
Verilog design consists of a hierarchy of modules are defined with a set of input, output, and bidirectional ports.
Internally, a module contains a list of wires and registers. Concurrent and sequential statements define the
behavior of the module by defining the relationships between the ports, wires, and registers Sequential statements
are placed inside a begin/end block and executed in sequential order within the block. But all concurrent
statements and all begin/end blocks in the design are executed in parallel, qualifying Verilog as a Dataflow
language. A module can also contain one or more instances of another module to define sub-behavior.A subset of
statements in the language is synthesizable. If the modules in a design contains a netlist that describes the basic
components and connections to be implemented in hardware only synthesizable statements, software can be used
to transform or synthesize the design into the net list may then be transformed into, for example, a form
describing the standard cells of an integrated circuit (e.g. ASIC) or a bit stream for a programmable logic device
(e.g. FPGA).

HDL Programming using Xilinx ISE design suite:

Xilinx ISE means Xilinx® Integrated Software Environment (ISE), i.e programmable logic design tool in
electronics industry. This Xilinx ® design software suite allows taking design from design entry through Xilinx
device programming. The ISE Project Navigator manages and processes design through several steps in the ISE
design flow. These steps are Design Entry, Synthesis, Implementation, Simulation/Verification, and Device
Configuration. Xilinx is one of most popular software tool used to synthesize VHDL/Verilog code.

INTRODUCTION TO FPGA (FIELD PROGRAMMABLE GATE ARRAY):

FPGA contains a two dimensional arrays of logic blocks and interconnections between logic blocks. Both the
logic blocks and interconnects are programmable. Logic blocks are programmed to implement a desired function
and the interconnects are programmed using the switch boxes to connect the logic blocks. To implement a
complex design (CPU for instance), the design is divided into small sub functions and each sub function is
implemented using one logic block. All the sub functions implemented in logic blocks must be connected and
this is done by programming the interconnects.

XILINX FPGA :Xilinx logic block consists of one Look Up Table (LUT) and one Flip-flop. An LUT is used to
implement number of different functionality. The input lines to the logic block go into the LUT and enable it. The
output of the LUT gives the result of the logic function that it implements and the output of logic block is
registered or unregistered output from the LUT.
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Experiment No. -1
Aim: To simplify the given Boolean expressions and realize using Verilog program.

Theory

Boolean expression simplification is the process of reducing a Boolean algebraic expression to its simplest
form. In Boolean algebra, expressions are built using logic gates and can represent complex logical operations.
The goal of simplification is to find an equivalent expression that is simpler, containing fewer terms or
operations but still produces the same output for all possible input combination .
A binary Boolean algebra consists of a set B = {0, 1} and the operators + and ., having commutative and
distributive properties such that for two Boolean variables A and B having values in B, a + b = b + a, and a . b =
b . a. The operators + and . have identity elements 0 and 1, respectively, such that for any Boolean variable a, a
+ 0 = a, and a . 1 = a. Each Boolean variable a has a complement, denoted by a', such that a + a' = 1, and a . a' =
0.

Boolean expression simplification and its Logic circuit

Code

module boolean (A, B, Y);

input A, B;
output Y;
assign Y= (~A & B)+(A & ~B); endmodule

Expected waveform
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Experiment No. -2

Aim: To realize Adder/Subtractor(Full/half)circuits using Verilog data flow description.

Theory

Half Adder is a type of digital circuit to calculate the arithmetic binary addition of two single-bit numbers. It is a
circuit with two inputs and two outputs.
For two single-bit binary numbers A and B, half adder produces two single-bit binary outputs S and C, where S is the
Sum and C is the carry.
The operation of Half Adder is limited because it can only add two-bit binary digits. But in practical applications, we
need to add three or more bits.
This inability of the circuit puts a limitation on its use. Half-adders were used in early microprocessors and basic
digital circuits.
Full Adder is a digital circuit that adds three single-digit binary numbers. This is a three-input and two-output digital
circuit. For three single-bit binary numbers A, B, and Cin; the full adder circuit generates two single-bit binary
outputs S (Sum), and Cout (Carry).
Full Adders are used in-

 Digital Diaries
 Digital Calculator
 Digital Computer
 Arithmetic Logic Unit (ALU) of Microprocessors.

A Binary Subtractor is a digital circuit that performs the arithmetic binary subtraction between two numbers with
respect to the logic operations and laws of Boolean Algebra. The subtractors are used in combinational circuit design
and the Arithmetic Logic Unit (ALU) of the processor to calculate multiple addresses. Subtractor circuits reduce
sound distortion in amplifiers and the power of radio signals.
Half Subtractors are a type of digital circuit that calculates the arithmetic binary subtraction between two single-bit
numbers. It is a circuit with two inputs and two outputs.
For two single-bit binary numbers A and B, a half subtractor produces two outputs difference and borrow.
A full Subtractor is a digital circuit that performs the subtraction of three single-digit binary numbers. This is a three-
input and two-output digital circuit.
Full Subtractors are used in-

 Performing Arithmetical functions like subtraction in ALU of Microprocessors.

 Electronic Calculators
 Digital Devices
 Computing Address Tables in ALU.
 DSP and networking-based systems.

Logic circuit and truth table

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Code

module halfAdder (A, B, Sum, Cout);

input A, B;
output Sum, Cout;
assign Sum = A ^ B;
assign Cout = A & B;
endmodule
---------------------------------------------------------------------------------------------------
Test Bench
module half_adder_tb;
reg a,b;
wire sum,carry;

halfadder uut(a,b,sum,carry);
initial begin
a = 0; b = 0;#10
b = 0; b = 1;#10
a = 1; b = 0;#10
b = 1; b = 1;#10
$finish();
end
endmodule

Expected waveform
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Logic circuit and truth table

Code

module fullAdder (A, B, Cin, Sum, Cout);

input A, B, Cin;
output Sum, Cout;
assign Sum = A ^ B ^ Cin;
assign Cout= (A&B)|(B&C)|(C&A);
endmodule

Expected waveform

--------------------------------------------------------------------------------------------------------------------

Logic circuit and truth table

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Code

module halfsubtractor(input a, b, output D, B);

assign D = a ^ b;
assign B = ~a & b;
endmodule

Expected waveform

--------------------------------------------------------------------------------------------------------------

Logic circuit and truth table

Code
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module fullsubtractor(input a, b, Bin, output D, Bout);

assign D = a ^ b ^ Bin;
assign Bout = (~a & b) | (~(a ^ b) & Bin);
endmodule

Expected waveform
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Experiment No. -3

Aim: To realize 4-bit ALU using Verilog program.

Theory

The Arithmetic and Logic Unit is the functional part of a digital computer that carries out arithmetic and logical
operations on machine words that represent operands. It is usually a part of the central processing unit.Modern CPUs
contain very powerful and complex ALUs. In addition to ALU modern CPUs also contains control unit. Most of the
operations of the CPU are performed by one or more ALUs that load data from input registers.A register is a small
amount of storage available as part of a CPU. The control unit tells the ALU what operation to perform on that data
and the ALU stores the result in an output register.The control unit moves data between these registers, the ALU and
memory.
An Arithmetic and Logic Unit (ALU) is a digital circuit that performs arithmetic and logical operations on binary
numbers. It is a fundamental building block of the central processing unit (CPU) in a computer. The ALU is
responsible for performing operations such as addition, subtraction, multiplication, division, logical AND, logical
OR, and more.

Logic circuit

Truth Table

Code
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module ALU_4bit(
input [3:0] A, // 4-bit input A
input [3:0] B, // 4-bit input B
input [2:0] OP, // 3-bit control input for operation selection
output [3:0] Result // 4-bit output
// Define ALU operations based on OP
assign Result = (OP == 3'b000) ? A + B :
(OP == 3'b001) ? A — B :
(OP == 3'b010) ? A - 1 :
(OP == 3'b011) ? A + 1 :
(OP == 3'b100) ? A & B :
(OP == 3'b101) ? A | B :
(OP == 3'b110) ? ~A B :
(OP == 3'b111) ? A ^ B :
4'b0000; // Default to zero for other OP values
endmodule
Expected waveform
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Experiment No. -4

Aim: To realize the following Code converters using Verilog Behavioral description

a)Gray to binary and vice versa b)Binary to excess3 and vice versa
Theory

Gray code is a binary numeral system where consecutive values differ by only one bit. It finds applications in various
fields, including digital communication, rotary encoders, and error detection.
In Gray code, each binary number is represented in a way that only one bit changes at a time as we move from one
value to the next. This property is particularly useful in minimizing errors during transitions between consecutive
values.
Binary to Gray code conversion is a technique used in digital electronics to transform binary numbers into their
equivalent Gray code representation. Gray code is a binary numeral system where each successive value differs by
only one bit position, making it useful in applications where errors in counting or sensing can occur due to noise or
interference.
The conversion process involves taking the binary code and performing exclusive OR (XOR) operations between
adjacent bits to obtain the corresponding Gray code.
BCD (Binary Coded Decimal) is a coding scheme that represents each decimal digit with a 4-bit binary code. In
BCD, each digit is represented by a unique 4-bit binary value from 0000 to 1001. Each of these BCD codes
represents the respective decimal digit in binary format. For example, BCD code 0011 represents the decimal digit 3,
and BCD code 1001 represents the decimal digit 9.
Excess-3 code, also known as XS-3 or 3XS, is a self-complementing BCD code that is obtained by adding 3 (0011 in
binary) to each BCD digit. It is commonly used for arithmetic operations in digital systems.

a)Gray to binary code:

Logic circuit

Truth Table
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Code

module gray_to_binary (
input [3:0] gray, // Assuming 4-bit Gray code input
output reg [3:0] binary
);
always @(gray) begin
binary[3] = gray[3];
binary[2] = binary[3] ^ gray[2];
binary[1] = binary[2] ^ gray[1];
binary[0] = binary[1] ^ gray[0];
end
endmodule

Expected waveform
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Binary code to Gray code:

Logic circuit

Truth Table

Code

module Binary_to_Gray(
input [3:0] b,
output [3:0] g
);
assign g[0]=b[1]^b[0];
assign g[1]=b[2]^b[1];
assign g[2]=b[3]^b[2];
assign g[3]=b[3];
endmodule

Expected waveform
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b)Binary to excess3
Logic circuit

Truth Table

Code
module Bcd_excess3(b,e);
input [3:0] b;
output [3:0] e;
assign e[3]=b[3]|b[2]&b[1]|b[2]&b[0];
 RV Institute of technology and Management

assign e[2]=~b[2]&b[1]|~b[2]&b[0]|b[2]&~b[1]&~b[0];
assign e[1]=b[1]&b[0]|~b[1]&~b[0];
assign e[0]=~b[0];
endmodule

Expected waveform

Excess3 to BCD code:

Truth Table

Code
module excess3_to_bcd (
input [3:0] excess3, // Assuming 4-bit excess-3 input
output reg [7:0] bcd
);

always @(excess3) begin

// Convert each 4-bit excess-3 digit to BCD
// Using a case statement for simplicity
case (excess3)
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4'b0000: bcd = 4'b0000; // 0

4'b0001: bcd = 4'b0001; // 1
4'b0010: bcd = 4'b0010; // 2
4'b0011: bcd = 4'b0011; // 3
4'b0100: bcd = 4'b0100; // 4
4'b0101: bcd = 4'b0101; // 5
4'b0110: bcd = 4'b0110; // 6
4'b0111: bcd = 4'b0111; // 7
4'b1000: bcd = 4'b1000; // 8
4'b1001: bcd = 4'b1001; // 9
default: bcd = 4'b0000; // Default to 0 if input is invalid
endcase
end

endmodule
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Experiment No. -5

Aim: To realize using Verilog Behavioral description:8:1mux, 8:3encoder, Priority encoder

Theory:

The multiplexer or MUX is a digital switch, also called as data selector. Multiplexer is a
combinational circuit that has maximum of 2n data inputs, ‗n‘ selection lines and single output line.
One of these data inputs will be connected to the output based on the values of selection lines. Since
there are ‗n‘ selection lines, there will be 2n possible combinations of zeros and ones. So, each
combination will select only one data input. Multiplexer is also called as Mux. 8x1 Multiplexer has 8
data inputs, 3 selection lines and one output. These are mostly used to form a sele ted path between
multiple sources and a single destination. A basic multiplexer has various data input lines and a
single output line. These are found in many digital system applications such as data selection and
data routing, logic function generators, digital counters with multiplexed displays, telephone network,
communication systems, waveform generators, etc. In this article we are going to discuss about types
of multiplexers and its design. In all types of digital system applications, multiplexers find its
immense usage. Since these allows multiple inputs to be connected independently to a single output,
these are found in variety of applications including data routing, logic function generators, control
sequencers, parallel-to serial converters, etc. Data Routing: Multiplexers are extensively used in data
routing applications to route the data to a one particular destination from one of several sources.

Entity level diagram and truth table

S2 S1 S0 Y

0 0 0 10

0 0 1 11

0 1 0 12

0 1 1 13

1 0 0 14

1 0 1 15

1 1 0 16

1 1 1 17
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An Encoder is a combinational circuit that performs the reverse operation of Decoder. It has
maximum of 2n input lines and ‘n’ output lines; hence it encodes the information from 2n inputs into
an n-bit code. It will produce a binary code equivalent to the input, which is active High. Therefore,
the encoder encodes 2n input lines with ‘n‘ bits. Encoders are very common electronic circuits used
in all digital systems. Encoders are used to translate the decimal values to the binary in order to
perform the binary functions such as addition, subtraction, multiplication, etc. One of the main
disadvantages of standard digital encoders is that they can generate the wrong output code when
there is more than one input present at logic level ―1¦. One simple way to overcome this problem
is to ―Prioritise¦ the level of each input pin. if there is more than one input at logic level ―1¦ at the
same time, the actual output code would only correspond to the input with the highest designated
priority. Then this type of digital encoder is known commonly as a Priority Encoder or P-encoder
for short. The Priority Encoder solves the problems mentioned above by allocating a priority level
to each input. The priority encoders output corresponds to the currently active input which has the
highest priority. when an input with a higher priority is present, all other inputs with a lower priority
will be ignored. Priority encoders can be used to reduce the number of wires needed in a particular
circuits or application that have multiple inputs. Other applications especially for Priority Encoders
may include detecting interrupts in microprocessor applications.

Entity level diagram

Truth Table:
En D7 D6 D5 D4 D3 D2 D1 D0 Q2 Q1 Q0
0 X X X X X X X X Z Z Z
1 0 0 0 0 0 0 0 1 0 0 0

1 0 0 0 0 0 0 1 X 0 0 1
1 0 0 0 0 0 1 X X 0 1 0
1 0 0 0 0 1 X X X 0 1 1
1 0 0 0 1 X X X X 1 0 0

1 0 0 1 X X X X X 1 0 1
1 0 1 X X X X X X 1 1 0
1 1 X X X X X X X 1 1 1

1 1 X X X X X X X Z Z Z
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Verilog Code for 8:1 Multiplexer

module m81(out, D0, D1, D2, D3, D4, D5, D6, D7, S0, S1, S2);
input wire D0, D1, D2, D3, D4, D5, D6, D7, S0, S1, S2;
output reg out;
always@(*)
begin
case(S0 & S1 & S2)
3'b000: out=D0;
3'b001: out=D1;
3'b010: out=D2;
3'b011: out=D3;
3'b100: out=D4;
3'b101: out=D5;
3'b110: out=D6;
3'b111: out=D7;
default: out=1'b0;
endcase
end
endmodule

//Testbench
module top;
wire out;
reg D0, D1, D2, D3, D4, D5, D6, D7, D8, S0, S1, S2;
m81 uut(.D0(D0), .D1(D1), . D2(D2), .D3(D3), .D4(D4), .D5(D5), .D6(D6), .D7(D7),
.S0(S0), .S1(S1), .S2(S2), .out(out));
initial
begin
D0=1'b0; D1=1'b0; D2=1'b0; D3=1'b0; D4=1'b0; D5=1'b0; D6=1'b0; D7=1'b0;S0=1'b0;
S1=1'b0; S2=1'b0;
#500 $finish;
end
always #1 D0=~D0;
always #2 D1=~D1;
always #3 D2=~D2;
always #4 D3=~D3;
always #5 D4=~D4;
always #6 D5=~D5;
always #7 D6=~D6;
always #8 D7=~D7;
always #9 S0=~S0;
always #10 S1=~S1;
always #11 S2=~S2;
always@(D0 or D1 or D2 or D 3 or D4 or D5 or D6 or D7 or S0 or S1 or S2)
$monitor("At time = %t, Out put = %d", $time, out);
Endmodule

Verilog Code for 8:3 Encoder

module encoder (din, dout);

input [7:0] din;
output [2:0] dout;
 RV Institute of technology and Management

reg [2:0] dout;

always @(din)
begin
if (din ==8'b00000001) dout =3'b000;
else if (din==8'b00000010) dout=3'b001;
else if (din==8'b00000100) dout=3'b010;
else if (din==8'b00001000) dout=3'b011;
else if (din==8'b00010000) dout=3'b100;
else if (din ==8'b00100000) dout=3'b101;
else if (din==8'b01000000) dout=3'b110;
else if (din==8'b10000000) dout=3'b111;
else dout=3'bX;
end
endmodule

module encodert_b;
reg [0:7] din;
wire [2:0] dout;
encoder uut (.din(din), .do ut(dout));
initial begin
#10 din=8'b10000000;
#10 din=8'b01000000;
#10 din=8'b00100000;
#10 din=8'b00010000;
#10 din=8'b00001000;
#10 din=8'b00000100;
#10 din=8'b00000010;
#10 din=8'b00000001;
#10 $stop;
end
endmodule

Verilog Code for Priority encoder

module encoder_wp(D, Q, En);
input En;
input [7:0] D;
output [2:0] Q;
reg [ 2:0] Q;
always@ ( En,D)
begin if ( En ==1)
begin if ( D[7]== 1) Q = 3'b111;
else if ( D[6] == 1) Q = 3'b110;
else if ( D[5] == 1) Q = 3'b101;
else if ( D[4] == 1) Q = 3'b100;
else if ( D[3] == 1) Q = 3'b011;
else if ( D[2] == 1) Q = 3'b010;
else if ( D[1] == 1) Q = 3'b001;
else if ( D[0] == 1) Q = 3'b000;
else Q = 3'bzzz;
end
end
endmodule
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module prio_enco_8x3_tst;
reg [7:0] D;
reg En;
wire[2:0] Q;
encoder_wp uut (.D(D),.Q(Q ),.En(En));
initial
begin
En=1'b0;
#10 En=1'b1;

#10 D=8'b00000001;
#10 D=8'b00000010;
#10 D=8'b00000110;
#10 D=8'b00001010;
#10 D=8'b00010000;
#10 D=8'b00100010;
#10 D=8'b01000000;
#10 D=8'b10000110;
#10 D=8'b10001000;
#10 $stop;
end
endmodule

Expected Waveform for 8:1 Multiplexer

Expected Waveform for 8:3 encoder

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Expected Waveform for Priority encoder

Result:Verilog code for 8:1 mux, 8:3 encoder, Priority encoder are realized.
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Experiment 6
1:8Demux, 3:8 decoder, 2 bit comparator
Aim: Write a Verilog code for 1:8 Demux, 3:8 decoder, 2 bit comparator

Theory:
The 1:8 Demux consists of 1 data input bit, 3 control bits and 8 output bits. I0, I1, I2, I3, I4, I5, I6,
I7 are the eight output bits, S0, S1 an dS2 are the control bits and input D.

The applications include: Demultiplexers are used in clock data recovery solution . Demultiplexer
along with multiplexer is necessary for any communication system for data transmission.
Demultiplexers are used in ATM packets broadcasting. The output of Arithmetic Logic Unit is
stored in respective registers using Demultiplexers.
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Decoder- In this tutorial, you learn about the Decoder which is one of the most important topics
in digital electronics. In this article we will talk about the Decoder itself, we will have a look at
the 3 to 8 decoder, 3 to 8 line decoder designing steps, a technique to sim plify the Boolean
function, and in the end, we will draw a logic diagram of the 3 to 8 decoder.
A digital decoder converts a set of digital signals into corresponding decimal code. A decoder is also
the most commonly used circuit prior to the use of an encoder. The encoded data is decoded for the
user interface in most of the output devices like monitors, calculator displays, printers, etc.

A magnitude digital Comparator is a combinational circuit that compares two igital or binary
numbers in order to find out whether one binary number is equal, less than, o r greater than the
other binary number. We logically design a circuit for which we will have two inputs one for A and
the other for B and have three output terminals, one for A > B condition, one for A = B condition,
and one for A < B condition.
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Verilog Program for 1:8 Demux

module Demultiplexer(in,s0, s1,s2,d0,d1,d2,d3,d4,d5,d6,d7);

input in,s0,s1,s2;
output d0,d1,d2,d3,d4,d5,d6 ,d7;
assign d0=(in & ~s2 & ~s1 & ~s0),
d1=(in & ~s2 & ~s1 &s0),
d2=(in & ~s2 & s1 &~s0),
d3=(in & ~s2 & s1 &s0),
d4=(in & s2 & ~s1 &~s0),
d5=(in & s2 & ~s1 &s0),
d6=(in & s2 & s1 &~s0),
d7=(in & s2 & s1 &s0);
endmodule

module TestModule;
// Inputs
reg in;
reg s0;
reg s1;
reg s2;

// Outputs
wire d0;
wire d1;
wire d2;
wire d3;
wire d4;
wire d5;
wire d6;
wire d7;

// Instantiate the Unit Und er Test (UUT)

Demultiplexer uut (
.in(in),
.s0(s0),
.s1(s1),
.s2(s2),
.d0(d0),
.d1(d1),
.d2(d2),
.d3(d3),
.d4(d4),
.d5(d5),
.d6(d6),
.d7(d7)
);
initial begin
// Initialize Inputs
in = 0;
s0 = 0;
s1 = 0;
s2 = 0;
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// Wait 100 ns for global reset to finish

#100;
in = 1;
s0 = 0;
s1 = 1;
s2 = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
d1 = 0;
d2 = 0;
d3 = 0;
d4 = 1;
d5 = 1;
d6 = 0;
d7 = 1;
sel = 5;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

end
endmodule

Verilog Program 8:3 decoder.

module Decoder(a,b,c,d0,d1,d2,d3,d4,d5,d6,d7);
input a,b,c;
output d0,d1,d2,d3, d4,d5,d6,d7;
assign d0=(~a&~b&~c ),
d1=(~a&~b&c),
d2=(~a&b&~c),
d3=(~a&b&c),
d4=(a&~b&~c),
d5=(a&~b&c),
d6=(a&b&~c),
d7=(a&b&c);
endmodule

module TestModule;
// Inputs
reg a;
reg b;
reg c;

// Outputs
wire d0;
wire d1;
wire d2;
 RV Institute of technology and Management

wire d3;
wire d4;
wire d5;
wire d6;
wire d7;

// Instantiate the Unit Under Test (UUT)

Decoder uut (
.a(a),
.b(b),
.c(c),
.d0(d0),
.d1(d1),
.d2(d2),
.d3(d3),
.d4(d4),
.d5(d5),
.d6(d6),
.d7(d7)
);
initial begin
// Initialize Inputs
a = 0;
b = 0;
c = 0;
// Wait 100 ns for global r eset to finish
#100;
a = 1;
b = 0;
c = 1;
// Wait 100 ns for global r eset to finish
#100;
end
endmodule

Verilog Program 4bit comparator.

module comparator(
Data_in_A, //input A
Data_in_B, //input B
less, //high when A is less than B
equal, //high whe n A is equal to B
greater //high when A is greater than B
);

//what are the input po rts.

input [3:0] Data_in_A;
input [3:0] Data_in_B;
//What are the output p orts.
output less;
output equal;
output greater;
 RV Institute of technology and Management

//Internal variables
reg less;
reg equal;
reg greater;

//When the inputs and A or B are changed execute this block

always @(Data_in_A or D ata_in_B)
begin
if(Data_in_A > Data _in_B) begin //check if A is bigger than B.
less = 0;
equal = 0;
greater = 1; end
else if(Data_in_A = = Data_in_B) begin //Check if A is equal to B
less = 0;
equal = 1;
greater = 0; end
elsebegin //Oth erwise - check for A less than B.
less = 1;
equal = 0;
greater =0;
end
end
endmodule

Testbench for Comparator:

module tb_tm;

// Inputs
reg [3:0] Data_in_A;
reg [3:0] Data_in_B;

// Outputs
wire less;
wire equal;
wire greater;

// Instantiate the Unit Under Test (UUT)

comparator uut (
.Data_in_A(Data_in_ A),
.Data_in_B(Data_in_ B),
.less(less),
.equal(equal),
.greater(greater)
);

initial begin
//Apply inputs
Data_in_A = 10;
Data_in_B = 12;
#100;
Data_in_A = 15;
Data_in_B = 11;
#100;
 RV Institute of technology and Management

Data_in_A = 10;
Data_in_B = 10;
#100;
end

endmodule

Expected Waveform for 1:8 Demultiplier

Expected Waveform for 3:8 Decoder

 RV Institute of technology and Management

Expected Waveform for 4 bit comparator

 RV Institute of technology and Management

Experiment 7
SR flip flop , JK flip flop, T flipflop,D flip flop
Aim: Write a Verilog code for SR,JK,D flip flop and verify the functionality using FPGA board.

Theory:
A flip flop is an electronic circuit with two stable states that can be used to store binary data. The
stored data can be changed by applying varying inputs. Flip-flops and latches are fundamental
building blocks of digital electronics systems used in computers, communications, and many other
types of systems. Flip-flops and latches are used asdata storageelements. It is the basic storage
element in sequential logic. The basic building block that makes computer memories possible and
is also used in many sequential logic circuits is the flip-flop or bistable circuit. Just two inter-
connected logic gates make up the basic form of this circuit whose output has two stable output
states.

The SR flip-flop can be considered as a 1-bit memory since it stores the input pulse even after it
has passed. Flipflops (or bi-stables) of different types can be made from logic gates and, as with
other combinations of logic gates, the NAND and NOR gates are the most versatile, the NAND
being most widely used. This is because, as well as being universal, i.e. it can be made to mimic
any of the other standard logic functions, it is also cheaper to construct. Other, more widely used
types of flip-flop are the JK, the D type and T type. Applications of flipflops include Registers,
Counters, Event Detectors, Data Synchronizers, Frequency Dividers.

The SR (Set-Reset) flip-flop is one of the simplest sequential circuits. The output of each gate is
connected to one of the inputs of the other gate, giving a form of positive feedback or ‗cross-
coupling‘. This SR flip flop circuit has a
|
set input (S) and a reset input (R). In this circuit when ―S¦ is active the output ―Q¦ would be
high and ―Q ¦ will be low. The indeterminate or uncertain logic state only occurs if the inputs
change from 0,0 to 1,1 together. This should be avoided in normal operation but is likely to
happen when power is first applied. This could lead to uncertain results, but the flip-flop will work
normally once an input pulse is applied to either input. The SR Flip-flop is therefore, a simple 1-
bit memory.
 RV Institute of technology and Management

Entity level diagram:

Truth Table:

S R CLK Q(t+1) Comments

0 0 X Q(t) No change

0 1 0 Reset

1 0 1 Set

1 1 ? Invalid

Verilog Code :SR Flipflop

module srff_behave(s,r,clk, q, qbar);

input s,r,clk;
output reg q, qbar;

always@(posedge clk)
begin

if(s == 1)
begin
q = 1;
qbar = 0;
end
else if(r == 1)
begin
 RV Institute of technology and Management

q = 0;
qbar =1;
end
else if(s == 0 & r == 0)
begin
q <= q;
qbar <= qbar
end
end
endmodule

//test bench for d flip flo p

//1. Declare module and por ts

module dff_test;
reg S,R, CLK;
wire Q, QBAR;

//2. Instantiate the module we want to test. We have instantiated the

srff_behavior

srff_behavior dut(.q(Q), .q bar(QBAR), .s(S), .r(R), .clk(CLK)); // instantiation

by port name.

//3. Monitor TB ports

$monitor("simtime = %g, CLK = %b, S = %b, R = %b, Q = %b, QBAR = %b", $time,
CLK, S, R, Q, QBAR);

//4. apply test vectors

initial begin
clk=0;
forever #10 clk = ~clk ;
end
initial begin
S= 1; R= 0;
#100; S= 0; R= 1;
#100; S= 0; R= 0;
#100; S= 1; R=1;
end
endmodule
 RV Institute of technology and Management

Expected Waveform

Verilog Code for D Flip Flop

module DFF( Q,

Qbar,

D,

Clk,

Reset

);

output reg Q;

output Qbar;

input D,

Clk,

Reset;

assign Qbar = ~Q;

always @(posedge Clk)

begin

if (Reset == 1'b1) //If no t at reset

 RV Institute of technology and Management

Q = 1'b0;

else

Q = D;

end

endmodule

module DFF_tb;

// Inputs

reg D;

reg Clk;

reg Reset;

// Outputs

wire Q;

wire Qbar;

// Instantiate the Unit Un der Test (UUT)

DFF uut (

.Q(Q),

.Qbar(Qbar),

.D(D),

.Clk(Clk),

.Reset(Reset)

);

initial begin

// Initialize Inputs

D = 1'b0;

Clk = 1'b0;

Reset = 1'b1;

// Wait 100 ns for global reset to finish

 RV Institute of technology and Management

#100;

// Add stimulus here

Reset = 1'b0;

#20;

forever #40 D = ~ D;

end

always #10 Clk = ~Clk;

endmodule

Expected Waveform:

Verilog Code for T Flip Flops

module T_flipflop (
input clk, rst_n,
input t,
output reg q,
output q_bar
);
 RV Institute of technology and Management

// always@(posedge clk or negedge rst_n) // for asynchronous reset

always@(posedge clk) begi n // for synchronous reset
if(!rst_n) q <= 0;
else begin
q <= (t?~q:q);
end
end
assign q_bar = ~q;
endmodule

EXPECTED WAVEFORM

Verilog Code for JK Flip Flops

module jkff_behave(clk,j,kn q,qbar);

input clk,j,k;
output reg q,qbar;

always@(posedge clk)
begin
if(k = 0)
begin
q <= 0;
qbar <= 1;
end
always@(posedge clk)
begin
if(k = 0)
begin
q <= 0;
qbar <= 1;
end
else if(j = 1)
begin
 RV Institute of technology and Management

q <= 0;
qbar <= 0;
end
else if(j = 0 & k = 0)
begin
q <= q;
qbar <= qbar;
end
else if(j = 1 & k = 1)
begin
q <= ~q;
qbar <= ~qbar;
end
end

endmodule

//test bench for JK flip fl op

//1. Declare module and por ts

module jkff_test;
reg J,K, CLK;
wire Q, QBAR;

//2. Instantiate the module we want to test. We have instantiated the

jkff_behavior
jkff_behavior dut(.q(Q), .q bar(QBAR), .j(J), .k(K), .clk(CLK)); // instantiation
by port name.

//3. Monitor TB ports

$monitor("simtime = %g, CLK = %b, J = %b, K = %b, Q = %b, QBAR = %b", $time,
CLK, J, K, Q, QBAR);

//4. apply test vectors

initial begin
clk=0;
forever #10 clk = ~clk ;
end
initial begin
J= 1; K= 0;
#100; J= 0; K= 1;
#100; J= 0; K= 0;
#100; J= 1; K=1;
end
endmodule

Expected Waveform:
RV Institute of technology and Management
 RV Institute of technology and Management

Experiment 8
BCD synchronous counter,up/down binary counter
Aim: Write a Verilog code for 4-bit BCD synchronous counter, up/down binary counter and verify
the functionality using FPGA board.

Software Tools: Xilinx ISE Design Suite 13.1

Hardware: Spartan 6 FPGA Development Board

Theory:
In digital electronics, counter is a sequential logic circuit consisting of a series of flip-flops which is
used to counts the number of occurrences of input in terms of negative or positive edge transitions.
Countersare of two types depending upon clock pulse applied. These counters are: Asynchronous
counter, and Synchronous counter. In Asynchronous Counter is also known asRippleCounter,
different flip flops are triggered with different clock, not simultaneously. While in Synchronous
Counter, all flip flops are triggered with same clock simultaneously and Synchronous Counter is
faster than asynchronous counter in operation. In synchronous counter, all flip flops are triggered
with same clock simultaneously. Synchronous Counter is faster than asynchronous counter in
operation. Synchronous Counter does not produce any decoding errors. Synchronous Counter is
also called Parallel Counter. Synchronous Counter designing as well implementation are complex
due to increasing the number of states. Synchronous Counter will operate in any desired count
sequence. Synchronous Counter examples are:Ringcounter,Johnsoncounter. n synchronous
counter, propagation delay is less.

Synchronous counters are used in Alarm Clock, Set AC Timer, Set time in camera to take the
picture, flashing light indicator in automobiles, car parking control etc. Counting the time allotted
for special process or event by the scheduler. The one advantage of synchronous counter over
asynchronous counter is, it can operate on higher frequency than asynchronous counter as it does
not have cumulative delay because of same clock is given to each flip flop.

Synchronous Counter:
 RV Institute of technology and Management

Truth Table of Synchronous Counter

clk(rising edge) rst q[4:0]

1 0 0000
1 0 0001
1 0 0010
1 0 0011
1 0 0100
1 1 0000
1 0 0001
1 0 0010
1 0 0011
1 0 0100
1 0 0101
1 0 0110
1 0 0111
1 0 1000
1 0 1001
1 0 0000

Truth Table of Binary up/down Counter

BCD synchronous counter

Verilog Code:[ Simulation]

modulebcd_counter(clk,rst,q);
inputrst; input clk;
output [3:0]q;
 RV Institute of technology and Management

reg[3:0]q=4'b0000;
always@(posedgeclk)
begin if(rst==1 ||
q==4'b1001)
q=4'b0000; else
q=q+1; end
endmodule

Verilog code for testbench:

moduletest_bcd_counter;

// Inputs
regclk; regrst;

// Outputs
wire [3:0] q;

// Instantiate the Unit Under Test (UUT)

bcd_counteruut (
.clk(clk),
.rst(rst),
.q(q)
);

initial begin
clk = 0;
rst = 1;
#5 rst=0;
#150 rst=1;
#10 rst=0; #200
$finish;
end
always #5 clk=~clk;

endmodule

Verilog Code:
 RV Institute of technology and Management

modulebcd_counter_synt(clk,rst,q);
inputrst,clk; output [3:0]q;
reg [3:0]q=4'b0000; reg
[31:0] clkdiv=25'd0;
always@(posedgeclk)
clkdiv=clkdiv+1;
always@(posedgeclkdiv[24])
begin
if(rst==1 || q==4'b1001)
q=4'b0000; else
q=q+1; end endmodule

# PlanAhead Generated physical constraints

NET "clk" LOC = P56;
NET "q[0]" LOC = P98;
NET "q[1]" LOC = P99;
NET "q[2]" LOC = P100;
NET "q[3]" LOC = P101;
NET "rst" LOC = P121;

Verilog code for up-down counter

moduleup_down_counter(inputclk, reset,up_down, output[3:0] counter
);
reg [3:0] counter_up_down;

// down counter
always @(posedgeclkorposedge reset)
begin
if(reset)
counter_up_down<=4'h0;
elseif(~up_down)
counter_up_down<=counter_up_down+4'd1
;else
counter_up_down<=counter_up_down-4'd1;
end
assign counter =counter_up_down;
endmodule

Testbench Verilog code for up-down counter

moduleupdowncounter_testbench();
regclk, reset,up_down;
wire [3:0] counter;
up_down_counterdut(clk, reset,up_down, counter);
initialbegin
clk=0;
forever #5clk=~clk;
end
initialbegin
 RV Institute of technology and Management

reset=1;
up_down=0;
#20;
reset=0
;#200;
up_down=1;
end
endmodule

Expected Waveform:

BCD Counter:

Binary Counter

Verilog code for 4-bit BCD synchronous counter, up/down binary counterare verified using
Result:
FPGA board.
 RV Institute of technology and Management

DEMONSTRATION EXPERIMENTS
 RV Institute of technology and Management

Experiment 9
Verilog Program to interface a Stepper motor to the FPGA and rotate the motor
in the specified direction (by N steps).

Aim:Interface a Stepper motor to FPGA and write Verilog code to control the Stepper motor
rotation

Software Tools: Xilinx ISE Design Suite 13.1

Hardware: Spartan 6 FPGA Development Board

Theory:
A stepper motor is a special type of electric motor that moves in increments, or steps, rather than
turning smoothly as a conventional motor does. Typical increments are 0.9 or 1.8 degrees, with 400
or 200 increments thus representing a full circle. The speed of the motor is determined by the time
delay between each incremental movement.

U8 is a Driver Buffer (ULN2003) device connected to LPC-1768 Device and can be used for
driving Stepper Motor. On the LPC-1768, P1.22 to P1.25 is used to generate the pulse sequence
required to run the stepper Motor. Also, the Stepper Motor is powered by its own power supply pin
(COM), which is connected to a 12V supply. Table shows connections for stepper Motor.
Construction & Working Principle

The construction of a stepper motor is fairly related to a DC motor. It includes a p rmanent

e magnet
like Rotor which is in the middle & it will turn once force acts on it. This rotor is enclosed through a
no. of the stator which is wound through
r a magnetic coil all over it. The stator is arranged near to
rotor so that magnetic fields within the stators can control the movement of the rotor.
The stepper motor can be controlled by energizing every stator one by one. So the stator will
magnetize & works like an electromagnetic pole which uses repulsive energy on the rotor to move
forward. The stator’s alternative magnetizing as well as demagnetizing will shift the rotor
gradually &allows it to turn through great control. The stepper motor working principle is
Electro-Magnetism. It includes a rotor which is made with a permanent magnet whereas a stator is
with electromagnets. Once the supply is provided to the winding of the stator then the magnetic
field will be developed within the stator. Now rotor in the motor will start to move with the
rotating magnetic field of the stator. So this is the fundamental working principle of this motor

The applications of stepper motor include the following.

1. Industrial Machines – Stepper motors are used in automotive gauges and machine tooling
automated production equipment.
2. Security – new surveillance products for the security industry.
3. Medical – Stepper motors are used inside medical scanners, samplers, and also found
m pumps, respirators, and blood analysis machinery.
insidedigital dental photography, fluid
 RV Institute of technology and Management

4. Consumer Electronics – Stepper motors in cameras for automatic digital camera focus and zoom
functions.
And also have business machines applications, computer peripherals applications

Block Diagram:

Verilog Program:
module step_motor(input clk, output reg[3:0]stp, input dipsw1, input dipsw2, input
dipsw3); reg[20:0]count=21'd0; reg[3:0]stpval=4'b0001; always@(posedgeclk)
begin
count=count+1;
if(count==21'd20000000)
begin stp=stpval;
if(dipsw1==1)
begin
stpval=stpval>>1;
if(stpval==4'b0000)stpval=4'b1000;
end
else if(dipsw2==1)
begin
stpval=stpval>>1;
if(stpval==4'b0000)stpval=4'b1000;
end
else if(dipsw3==1)
begin count=0;
stpval=stpval<<1;
if(stpval==4'b0000)stpval=4'b0001;
end
endend
endmodule

UCF
 RV Institute of technology and Management

NET "clk" LOC = P56;

NET "stp[0]" LOC = P29;
NET "stp[1]" LOC = P30;
NET "stp[2]" LOC = P32;
NET "stp[3]" LOC = P33;
NET " dipsw1" LOC = P121;
NET " dipsw2" LOC = P123;
NET " dipsw3" LOC = P124;

Result:Verilog code to control the Stepper motor rotation is written and verified.
 RV Institute of technology and Management

Experiment 10
Verilog Program to interface Switches and LEDsto FPGA

Aim: Write a Verilog programs to interface Switches and LEDs to the FPGA/CPLD and
demonstrate its working.

Software Tools: Xilinx ISE Design Suite 13.1

Hardware: Spartan 6 FPGA Development Board

Block Diagram:

A digital circuit contains a power supply, devices, and conduction nets. Some nets provide the
circuit with inputs from the “outside world,” while others, conversely, provide information from the
circuit to the outside world. The nets that provide an interface between the circuit and the outside
world are called ports.

Circuits need input devices to generate input signals. Input devices can take many forms, among
them keyboards (such as on a PC), buttons, and switches. Circuits also need output devices to
communicate their state to the user. In this project, a switch is used as the input device and an LED
is used as the output device. The digital circuit we will build is called the “led_sw,” as shown in
Fig. 1 below. The circuit created in this project will be implemented inside the FPGA board. The
board has an input port called “sw,” which receives an input signal from the external switch in the
circuit and an output port called “led,” which drives the external LED in the circuit. The “led_sw” is
a simple circuit that bypasses the signal
s on the input port and directly sends information to the
output port. You can view this as a direct wired connection between the net “sw” and the net “led.”
The circuit will be implemented using Verilog HDL. On different FPGA boards, switches and
LEDs are connected to different pinss on an FPGA chip. Thus, a user constraint file (XDC) is needed
to map the input and output net of the circuit to the physical pin location on the FPGA chip. Take
Nexys3 as an example, the Slide Switch 0 (SW0) is connected to FPGA pin T10, and FPGA pin
U16 drives LED 0 (LD0). When you slide the switch to the ON position, a high voltage will be
placed on FPGA pin T10, which is mapped to the input port of the circuit “led_sw.” The digital
circuit then transmits the signal onto the output port LED, which is connected to FPGA pin U16.
The high voltage on the output port “led” will cause a voltage drop between node A and node B.
This voltage drop will drive current through the LED, which will light the LED and inform the user
that the switch is on.

Verilog Code:

module example (
inputclk,
inputrst,
input push,
output regled_on
);
 RV Institute of technology and Management

reg on;
reg off;

regt_on_off;
regt_off_on;

always @* begin
t_on_off = on & (push);
end

always @* begin
t_off_on = off & (push);
end

always @(posedgeclk or posedgerst) begin

if (rst) on <= 1'b0;
else if (t_off_on) on <= 1'b1;
else if (t_on_off) on <= 1'b0;
end

always @(posedgeclk or posedgerst) begin

if (rst) off <= 1'b1;
else if (t_off_on) off <= 1'b0;
else if (t_on_off) off <= 1'b1;
end

always @* begin
led_on = on;
end

endmodule

Result: Verilog programs to interface Switches and LEDs using the FPGA is verified
 RV Institute of Technology and Management, Bengaluru

END

---------

IIIrd semester DSDV Lab Manual

Page 53 of 53