8051 INTERRUPTS

Difference Between Interrupts vs polling:

A single microcontroller can serve several devices. There are two ways to do that: interrupts or
polling. In the interrupt method, whenever any device needs its service, the device notifies the
microcontroller by sending it an interrupt signal. Upon receiving an interrupt signal, the
microcontroller interrupts whatever it is doing and serves the device. The program associated with
the interrupt is called the interrupt service routine (ISR) or interrupt handler. In polling, the
microcontroller continuously monitors the status of a given device; when the status condition is
met, it performs the service. After that, it moves on to monitor the next device until each one is
serviced. Although polling can monitor the status of several devices and serve each of them as
certain conditions are met, it is not an efficient use of the microcontroller. The advantage of
interrupts is that the microcontroller can serve many devices (not all at the same time, of course);
each device can get the attention of the microcontroller based on the priority assigned to it. The
polling method cannot assign priority since it checks all devices in a round-robin fashion. More
importantly, in the interrupt method the microcontroller can also ignore (mask) a device request
for service. This is again not possible with the polling method. The most important reason that the
interrupt method is preferable is that the polling method wastes much of the microcontroller’s time
by polling devices that do not need service. So in order to avoid tying down the microcontroller,
interrupts are used. For example, in discussing timers in Chapter 9 we used the instruction “JNB
TF, target”, and waited until the timer rolled over, and while we were waiting we could not do
anything else. That is a waste of the microcontroller’s time that could have been used to perform
some useful tasks. In the case of the timer, if we use the interrupt method, the microcontroller can
go about doing other tasks, and when the TF flag is raised the timer will interrupt the
microcontroller in whatever it is doing.
Interrupt service routine
For every interrupt, there must be an interrupt service routine (ISR), or interrupt handler. When an
interrupt is invoked, the microcontroller runs the interrupt service routine. For every interrupt,
there is a fixed location in memory that holds the address of its ISR. The group of memory
locations set aside to hold the addresses of ISRs is called the interrupt vector table, shown in Table
Steps in executing an interrupt
Upon activation of an interrupt, the microcontroller goes through the following steps.
1. It finishes the instruction it is executing and saves the address of the next
instruction (PC) on the stack.
2. It also saves the current status of all the interrupts internally (i.e., not on the
stack).
3. It jumps to a fixed location in memory called the interrupt vector table that
holds the address of the interrupt service routine.
4. The microcontroller gets the address of the ISR from the interrupt vector table
and jumps to it. It starts to execute the interrupt service subroutine until it
reaches the last instruction of the subroutine, which is RETI (return from inter
rupt).
5. Upon executing the RETI instruction, the microcontroller returns to the place
where it was interrupted. First, it gets the program counter (PC) address from
the stack by popping the top two bytes of the stack into the PC. Then it starts
to execute from that address.
Notice from Step 5 the critical role of the stack. For this reason, we must be careful in manipulating
the stack contents in the ISR. Specifically, in the ISR, just as in any CALL subroutine, the number
of pushes and pops must be equal.
Six interrupts in the 8051

In reality, only five interrupts are available to the user in the 8051, but many manufacturers’ data
sheets state that there are six interrupts since they include reset. The six interrupts in the 8051 are
allocated as follows.
Reset. When the reset pin is activated, the 8051 jumps to address location
0000. This is the power-up reset.
Two interrupts are set aside for the timers: one for Timer 0 and one for Timer
Memory locations OOOBH and 001BH in the interrupt vector table belong
to Timer 0 and Tinier 1, respectively.
Two interrupts are set aside for hardware external hardware interrupts. Pin
numbers 12 (P3.2) and 13 (P3.3) in port 3 are for the external hardware inter
rupts INTO and INT1, respectively. These external interrupts are also referred
to as EX1 and EX2. Memory locations 0003H and 0013H in the interrupt vec
tor table are assigned to INTO and INT1, respectively.
Serial communication has a single interrupt that belongs to both receive and
transmit. The interrupt vector table location 0023H belongs to this interrupt.
Notice in Table 1 that a limited number of bytes is set aside for each interrupt. For example, a total
of 8 bytes from location 0003 to OOOOA is set aside for INTO, external hardware interrupt 0.
Similarly, a total of 8 bytes from location OOOBH to 0012H is reserved for TFO, Timer 0
interrupt.They are ROM address locations 0, 1, and 2. Address location 3 belongs to external
hardware interrupt 0. For this reason, in the program an LJMP as the first instruction and redirect
the processor away from the interrupt vector table,

Upon reset, all interrupts are disabled (masked), meaning that none will be responded to by the
microcontroller if they are activated. The interrupts must be enabled by software in order for the
microcontroller to respond to them. There is a register called IE (interrupt enable) that is
responsible for enabling (unmasking) and disabling (masking) the interrupts. Figure 11-2 shows
the IE register. Note that IE is a bit-addressable register.
From Figure 2 notice that bit D7 in the IE register is called EA (enable all). This must be set to 1
in order for the rest of the register to take effect. D6 is unused. D5 is used by the 8052. The D4 bit
is for the serial interrupt, and so on.
Steps in enabling an interrupt
To enable an interrupt, we take the following steps: .1. Bit D7 of the IE register (EA) must be set
to high to allow the rest of register
to take effect.
2. If EA = 1, interrupts are enabled and will be responded to if their corresponding bits in IE are
high. If EA = 0, no interrupt will be responded to, even if the associated bit in the IE register is
high.

Figure 2. IE (Interrupt Enable) Register

Example 1
 PROGRAMMING TIMER INTERRUPTS

Roll-over timer flag and interrupt

The timer flag (TF) is raised when the timer rolls over. In that chapter, we also showed how to
monitor TF with the instruction “JNB TF, target”. In polling TF, we have to wait until the TF is
raised. The problem with this method is that the microcontroller is tied down while waiting for TF
to be raised, and cannot do any thing else. Using interrupts solves this problem and avoids tying
down the controller. If the timer interrupt in the IE register is enabled, whenever the timer rolls
over, TF is raised, and the microcontroller is interrupted in whatever it is doing, and jumps to the
interrupt vector table to service the ISR. In this way, the microcontroller can do other things until
it is notified that the timer has rolled over.
Notice the following points about the program in Example below

1. We must avoid using the memory space allocated to the interrupt vector table. Therefore,
we place all the initialization codes in memory starting at 30H.
2. The LJMP instruction is the first instruction that the 8051 executes when it is powered up.
LJMP redirects the controller away from the interrupt vector table.
3. The ISR for Timer 0 is located starting at memory location OOOBH since it is
small enough to fit the address space allocated to this interrupt.
4. Enable the Timer 0 interrupt with “MOV IE, #10000010B” in MAIN.
5. While the PO data is brought in and issued to P1 continuously, whenever Timer
0 is rolled over, the TFO flag is raised, and the microcontroller gets out of the
“BACK” loop and goes to OOOOBH to execute the ISR associated with Timer 0.
6. In the ISR for Timer 0, notice that there is no need for a “CLR TFO” instruc
tion before the RETI instruction. This is because the 8051 clears the TF flag
internally upon jumping to the interrupt vector table.
Example
Write a program that continuously gets 8-bit data from PO and sends it to PI while simultaneously
creating a square wave of 200 (as period on pin P2.1. Use Timer 0 to create the square wave.
Assume that XTAL =11.0592 MHz.
Solution:

In Example the interrupt service routine was short enough that it could be placed in memory
locations allocated to the Timer 0 interrupt.
Example
Write a program to generate a square wave of 50 Hz frequency on pin PI .2. Use an interrupt for
Timer 0. Assume that XTAL = 11.0592MHz.
PROGRAMMING EXTERNAL HARDWARE INTERRUPTS
The 8051 has two external hardware interrupts. Piri 12 (P3.2) and pin 13 (P3.3) of the 8051,
designated as INTO and INT1, are used as external hardware interrupts. Upon activation of these
pins, the 8051 gets interrupted in whatever it is doing and jumps to the vector table to perform the
interrupt service routine. In this section we study these two external hardware interrupts of the
8051 with some examples.

Activation of INTO and INT1

External interrupts INTO and INT1

There are only two external hardware interrupts in the 8051: INTO and INT1. They are located on
pins P3.2 and P3.3 of port 3, respectively. The interrupt vector table locations 0003H and 0013H
are set aside for INTO and INT1, respectively. There are two types of activation for the external
hardware interrupts: (1) level triggered, and (2) edge triggered.
Level-triggered interrupt
In the level-triggered mode, INTO and INT1 pins are normally high (just like all I/O port pins)
and if a low-level signal is applied to them, it triggers the interrupt. Then the microcontroller stops
whatever it is doing and jumps to the interrupt vector table to service that interrupt. This is called
a level-triggered or level-activated interrupt and is the default mode upon reset of the 8051.

The low-level signal at the INT pin must be removed before the execution of the last instruction
of the interrupt service routine, RETI; otherwise, another interrupt will be generated. In other
words, if the low-level interrupt signal is not removed before the ISR is finished it is interpreted
as another interrupt and the 8051 jumps to the vector table to execute the ISR again.
Example
Assume that the INT1 pin is connected to a switch that is normally high. Whenever it goes low, it
should turn on an LED. The LED is connected to PI .3 and is normally off. When it is turned on it
should stay on for a fraction of a second. As long as the switch is pressed low, the LED should
stay on.
Solution:

In this program, the microcontroller, is looping continuously in the HERE loop. Whenever the
switch on INT1 (pin P3.3) is activated, the microcontroller gets out of the loop and jumps to vector
location 0013H. The ISR for INT1 turns on the LED, keeps it on for a while, and turns it off before
it returns. If by the time it executes the RETI instruction, the INT1 pin is still low, the
microcontroller initiates the interrupt again. Therefore, to end this problem, the INT1 pin must be
brought back to high by the time RETI is executed.
Significance of TCON REGISTER of 8051:-Edge-triggered interrupts

As stated before, upon reset the 8051 makes INTO and INT1 low-level triggered interrupts. To
make them edge-triggered interrupts, we must program the bits of the TCON register. The TCON
register holds, among other bits, the ITO and IT1 flag bits that determine level- or edge-triggered
mode of the hardware interrupts. ITO and IT1 are bits DO and D2 of the TCON register,
respectively. They are also referred to as TCON.O and TCON.2 since the TCON register is bit-
addressable. Upon reset, TCON.O (ITO) and TCON.2 (III) are both Os, meaning that the external
hardware interrupts of INTO and INT1 pins are low-level triggered. By making the TCON.O and
TCON.2 bits high with instructions such as “SETB TCON. 0″ and “SETB TCON. 2″, the external
hardware interrupts of INTO and INT1 become edge-triggered. For example, the instruction
“SETB CON. 2″ makes INT1 what is called an edge-triggered interrupt, in which, when a high-
to-low signal is applied to pin P3.3, in this case, the controller will be interrupted and forced to
jump to location 0013H in the vector table to service the ISR (assuming that the interrupt bit is
enabled in the IE register).

TF1 TCON.7 Timer 1 overflow flag. Set by hardware when timer/counter 1

overflows. Cleared by hardware as the processor vectors to the interrupt service routine.
TR1 TCON.6 Timer 1 run control bit. Set/cleared by software to turn
timer/counter 1 on/off.
TF0 TCON.5 Timer 0 overflow flag. Set by hardware when timer/counter 0
overflows. Cleared by hardware as the processor vectors to the service routine.
TR0 TCON.4 Timer 0 run control bit. Set/cleared by software to turn
timer/counter 0 on/off.
IE1 TCON.3 External interrupt 1 edge flag. Set by CPU when the
external interrupt edge (H-to-L transition) is detected. Cleared by CPU when the interrupt is
processed. Note: This flag does not latch low-level triggered interrupts.
IT1 TCON.2 Interrupt 1 type control bit. Set/cleared by software to
specify falling edge/low-level triggered external interrupt.
IE0 TCON.1 External interrupt 0 edge flag. Set by CPU when external
interrupt (H-to-L transition) edge is detected. Cleared by CPU when interrupt is
processed. Note: This flag does not latch low-level triggered interrupts.
IT0 TCON.0 Interrupt 0 type control bit. Set/cleared by software to specify
falling edge/low-level triggered external interrupt.

Example
What is the difference between the RET and RETI instructions? Explain why we cannot use RET
instead of RETI as the last instruction of an ISR.
Solution:
Both perform the same actions of popping off the top two bytes of the stack into the program
counter, and making the 8051 return to where it left off. However, RETI also performs an
additional task of clearing the interrupt-in-service flag, indicating that the servicing of the interrupt
is over and the 8051 now can accept a new interrupt on that pin. If you use RET instead of RETI
as the last instruction of the interrupt service routine, you simply block any new interrupt on that
pin after the first interrupt, since the pin status would indicate that the interrupt is still being
serviced. In the cases of TFO, TF1, TCON.l, and TCON.3, they are cleared by the execution of
RETI.

PROGRAMMING THE SERIAL COMMUNICATION INTERRUPT

Rl and Tl flags and interrupts

TI (transfer interrupt) is raised when the last bit of the framed data, the stop bit, is transferred,
indicating that the SBUF register is ready to transfer the next byte. RI (received interrupt), is raised
when the entire frame of data, including the stop bit, is received. In other words, when the SBUF
register has a byte, RI is raised to indicate that the received byte needs to be picked up before it is
lost (overrun) by new incoming serial data. As far as serial communication is concerned, all the
above concepts apply equally when using either polling or an interrupt. The only difference is in
how the serial communication needs are served. In the polling method, we wait for the flag (TI or
RI) to be raised; while we wait we cannot do anything else. In the interrupt method, we are notified
when the 8051 has received a byte, or is ready to send the next byte; we can do other things while
the serial communication needs are served.

In the 8051 only one interrupt is set aside for serial communication. This interrupt is used to both
send and receive data. If the interrupt bit in the IE register (IE.4) is enabled, when RI or TI is raised
the 8051 gets interrupted and jumps to memory address location 0023H to execute the ISR. In that
ISR we must examine the TI and RI flags to see which one caused the interrupt and respond
accordingly. See Example 11-8.

Single Interrupt for Both TI and RI

Example

Write a program in which the 8051 reads data from PI and writes it to P2 continuously while giving
a copy of it to the serial COM port to be transferred serially. Assume that XTAL = 11.0592 MHz.
Set the baud rate at 9600.
Solution:

In the above program notice the role of TI and RI. The moment a byte is written into SBUF it is
framed and transferred serially. As a result, when the last bit (stop bit) is transferred the Tl is raised,
which causes the serial interrupt to be invoked since the corresponding bit in the IE register is high.
In the serial ISR, we check for both TI and RI since both could have invoked the interrupt. In other
words, there is only one interrupt for both transmit and receive.
Clearing RI and TI before the RETI instruction
Notice in Example 11-9 that the last instruction before the RETI is the clearing of the RI or TI
flags. This is necessary since there is only one interrupt for both receive and transmit, and the 8051
does not know who generated it; therefore, it is the job of the ISR to clear the flag. Contrast this
with the external and timer interrupts where it is the job of the 8051 to clear the interrupt flags. By
contrast,
Example
Write a program in which the 8051 gets data from PI and sends it to P2 continuously while
incoming data from the serial port is sent to PO. Assume that XTAL = 11.0592 MHz. Set the baud
rate at 9600.
Solution:
in serial communication the RI (or TI) must be cleared by the programmer using software
instructions such as “CLR TI” and “CLR RI” in the ISR. See Example 11-10. Notice that the last
two instructions of the ISR are clearing the flag, followed by RETI.

Before finishing this section notice the list of all interrupt flags given in Table 11-2. While the
TCON register holds four of the interrupt flags, in the 8051 the SCON register has the RI and TI
flags.
INTERRUPT PROGRAMMING IN C
8051 C interrupt numbers
The 8051 C compilers have extensive support for the 8051 interrupts with two major features as
follows:
1. They assign a unique number to each of the 8051 interrupts, as shown in Table
11-4.
2. It can also assign a register bank to an ISR. This avoids code overhead due to
the pushes and pops of the RO – R7 registers.
Table 11-4: 8051/52 Interrupt Numbers in C
Example

Write a C program that continuously gets a single bit of data from PI. 7 and sends it to Pl.0, while
simultaneously creating a square wave of 200 (as period on pin P2.5. Use timer 0 to create the
square wave. Assume that XTAL = 11.0592 MHz.
Solution:
Example
Write a C program that continuously gets a single bit of data from PI. 7 and sends it to Pl.O in the
main, while simultaneously (a) creating a square wave of 200 us period on pin P2.5, and (b)
sending letter ‘A’ to the serial port. Use Timer 0 to create the square wave. Assume that XTAL =
11.0592 MHz. Use the 9600 baud rate.
Solution:
Example
Write a C program using interrupts to do the following:
1. Receive data serially and send it to PO,
2. Read port PI, transmit data serially, and give a copy to P2,
3. Make timer 0 generate a square wave of 5 kHz frequency on PO.l.
Assume that XTAL = 11.0592 MHz. Set the baud rate at 4800.
Solution:
Example
Write a C program using interrupts to do the following:
1. Generate a 10000 Hz frequency on P2.1 using TO 8-bit auto-reload,
2. Use timer 1 as an event counter to count up a 1-Hz pulse and display it on PO. The
pulse is connected to EX1.
Assume that XTAL = 11.0592 MHz. Set the baud rate at 9600.