EE-808 Fall 2024

Digital Integrated Circuit Design

Lecture # 07
Combinational Logic using Dynamic CMOS

Muhammad Imran
[email protected]
Acknowledgement
2

▪ Content from following resources has been used in these lectures

▪ Introduction to Digital Electronic Circuits, Adam Teman, BIU, Israel
▪ Jan. M. Rabaey, Digital Integrated Circuits, 2nd Ed.
▪ Book + Slides
▪ EE-141, UC Berkley, Fall 2010
▪ Sung-Mo Kang, CMOS Digital Integrated Circuits, 3rd Ed.
Contents
3

▪ Dynamic Logic
▪ Motivation
▪ Working
▪ Properties
▪ Signal Integrity Issues in Dynamic Logic
▪ Charge Loss
▪ Charge Sharing
▪ Cascading Dynamic Gates
Dynamic Logic
Motivation
5

▪ Ratioed logic reduces area

▪ But has drawbacks
▪ Vt drop
▪ Static power consumption
▪ Loss of regenerative property
▪ In certain situations, slow transitions!

▪ Alternate logic with still less area

▪ Dynamic logic
▪ Efficient and fast!
▪ N+2 transistors for N inputs
▪ Low static power consumption
▪ High speed!
Dynamic Logic
6

▪ Dynamic Circuits operate in two phases:

▪ Precharge:
▪ Set an initial output state
▪ Evaluation:
▪ Change the precharged output to the legal
state

▪ Basic architecture that includes:

▪ A standard PDN network
▪ Complementary precharge switches

▪ This is an “n-type” network

▪ The same can be accomplished using a
“p-type” Pull-Up network
Dynamic Logic – Precharge
7

▪ Precharge occurs when the clock is low

▪ Discharge path blocked
▪ Pull up path enabled

▪ Output capacitance charged to ‘1’ through

the top pMOS (the Precharge Transistor)

▪ The bottom nMOS eliminates static current

and ratioed behavior
Dynamic Logic – Evaluation
8

▪ Evaluation occurs when the clock is high

▪ Precharge Transistor turned off

▪ Blocking any additional charge to the
output capacitance

▪ The bottom nMOS (the Evaluation

Transistor) is turned on
▪ Enables a conditional path to ground

▪ The output is discharged, depending on

the input values and the combinational
function of the PDN
▪ Similar to static logic families
 Example – Dynamic Inverter
9

clk precharge evaluate precharge evaluate

CLK P1
t
VDD
A Cout
‘1’ ‘0’
t
A N2
Vout

CLK N1
t
▪ When the clock is low, the capacitance is charged
▪ When the clock goes high
▪ The output is discharged if the input is high
▪ If the input is low, the output stays high
Dynamic Logic Properties
10

▪ Implementation
▪ N+2 transistors required for gate implementation
▪ The logic is Non-Ratioed
▪ Sizing doesn’t affect functionality

▪ Static Power Consumption is low

▪ Dynamic Power Consumption is higher than Standard CMOS
▪ More switching activity, however, lower switched capacitance

▪ Switching speeds are higher than Standard CMOS

▪ Reduced Load Capacitance, Zero Short-Circuit Current
▪ Ability to optimize only one swing (tpHL)
Dynamic Logic VTC
11

▪ An interesting VTC Vout

▪ Until VTn, the output is VOH VDD

▪ Once we pass VTn

▪ There is no partially open pMOS
combating the PDN
▪ Output will fully discharge

▪ The VTC drops STRAIGHT down to VOL

▪ Bounded with time, the VTC will be
more gradual
Vin
VTn VDD

▪ NML=VTn
▪ This is very low!
 Logical Effort in Dynamic Logic
12

tpHL:
CLK W
Req = 2
Rn p = Rgate  Cd ,gate = 3 = 1
2 = Rinv Rinv Cd ,min 3
Cout
C g ( A ) = 2C g min Rgate C g ,gate 2
A 2W LE =  =
Cd = 3Cd min Rinv Cg ,min 3

CLK 2W
tpLH: p = 0, LE = 0

▪ Therefore, we get a very fast gate!

▪ For a 2-input NAND, we get:
4
pNAND = , LENAND = 1
3
Switching Activity in Dynamic Logic
13

▪ Transition from 0 to 1 during precharge

▪ Occurs only if output was discharged in preceding evaluate phase
▪ Therefore, 𝛼0→1 = 𝑝0 instead of 𝑝0 𝑝1 as in static CMOS!
▪ For 2-input NOR gate
3
▪ 𝛼0→1 = 0.75 instead of being for static CMOS NOR!
16
▪ For 2-input NAND gate
3
▪ 𝛼0→1 = 0.25 instead of being for static CMOS NAND!
16

▪ Higher switching activity

▪ But lower physical capacitance!
▪ Must account both when analyzing power consumption!
Signal Integrity Issues in Dynamic Logic
Dynamic Logic Problems
15

▪ Basic consideration of using Dynamic vs. Static Logic

▪ Speed vs. Power.

▪ However, high output degradation can occur in Dynamic Logic in the

following cases:
▪ Input Glitches
▪ Leakage Currents
▪ Charge Sharing
▪ Cascading dynamic gates
Charge Loss
16

▪ Output pulled up only during the Precharge

phase
▪ Any current that is discharged can only be
replenished at the next clock phase!

▪ If a low input (that cuts off the PDN, leaving a

high output) “glitches” from ‘0’ to ‘1’
▪ Path to ground temporarily opens, discharging
some of the output

▪ In addition, leakage current degrades the output

level
 Charge Loss – Input Glitch Example
17

▪ Only 0 to 1 transition allowed at input!

clk
CLK P1
Cout
t
A A N2

t CLK N1

Vout

t
Charge Loss – Leakage
18

CLK
Clk Mp
Out

A= 0 CL

VOut Evaluate
Clk Me
Precharge

Leakage sources

Dominant component is subthreshold current

Charge Loss – Solution
19

▪ Use Keeper device

▪ A pseudo-nMOS style pMOS to restore lost charge!
▪ Causes VOLmin > 0
▪ Static power dissipation
Charge Loss – Solution
20

▪ Feedback Keeper device

▪ A better way to attach keeper device
▪ Keeper device is cut off when Vout = 0

▪ Benefits
▪ Rail to rail swing
▪ No static power dissipation
▪ No glitching!

▪ Drawback
▪ Ratioed logic
▪ Extra transistors
Charge Sharing
21

▪ Charge Sharing occurs

▪ When the PDN is closed
▪ But one or more stacked transistors next to the
output are open
▪ Charge shared between the output capacitance
and the diffusion capacitance of the conducting
transistor
 Charge Sharing – Example
22

clk

CLK P1
VfiDnD
t
A
Cout
B N3
t Vfinal
B
C2
tA N2

Vout
C1
CLK N1

t
Charge Sharing – Voltage Drop
23

▪ When ∆𝑉𝑜𝑢𝑡 < 𝑉𝑇𝑛

▪ 𝑉𝑥 𝑓𝑖𝑛𝑎𝑙 = 𝑉𝐷𝐷 − 𝑉𝑇𝑛 (𝑉𝑥 )

▪ Using charge conservation:

▪ 𝐶𝐿 𝑉𝐷𝐷 = 𝐶𝐿 𝑉𝑜𝑢𝑡 (𝑓𝑖𝑛𝑎𝑙) + 𝐶𝑎 (𝑉𝐷𝐷 −𝑉𝑇𝑛 (𝑉𝑥 ))

▪ ∆𝑉𝑜𝑢𝑡 = 𝑉𝑜𝑢𝑡 𝑓𝑖𝑛𝑎𝑙 − 𝑉𝐷𝐷

𝐶
= − 𝐶𝑎 (𝑉𝐷𝐷 − 𝑉𝑇𝑛 (𝑉𝑥 ))
𝐿
Charge Sharing – Voltage Drop
24

▪ When ∆𝑉𝑜𝑢𝑡 > 𝑉𝑇𝑛

▪ 𝑉𝑥 𝑓𝑖𝑛𝑎𝑙 = 𝑉𝑜𝑢𝑡 𝑓𝑖𝑛𝑎𝑙

▪ Using charge conservation:

▪ 𝐶𝐿 𝑉𝐷𝐷 = 𝐶𝐿 𝑉𝑜𝑢𝑡 (𝑓𝑖𝑛𝑎𝑙) + 𝐶𝑎 (𝑉𝑜𝑢𝑡 (𝑓𝑖𝑛𝑎𝑙))

▪ ∆𝑉𝑜𝑢𝑡 = 𝑉𝑜𝑢𝑡 𝑓𝑖𝑛𝑎𝑙 − 𝑉𝐷𝐷

𝐶𝐿 𝑉𝐷𝐷
= − 𝑉𝐷𝐷
𝐶𝐿 +𝐶𝑎

𝐶𝐿 𝐶𝑎
= 𝑉𝐷𝐷 − 1 = −𝑉𝐷𝐷
𝐶𝐿 + 𝐶𝑎 𝐶𝐿 + 𝐶𝑎
Charge Sharing – Voltage Drop
25

▪ Summary
▪ When ∆𝑉𝑜𝑢𝑡 < 𝑉𝑇𝑛
𝐶𝑎
▪ ∆𝑉𝑜𝑢𝑡 = − (𝑉𝐷𝐷 − 𝑉𝑇𝑛 (𝑉𝑥 ))
𝐶𝐿

▪ When ∆𝑉𝑜𝑢𝑡 > 𝑉𝑇𝑛

𝐶𝑎
▪ ∆𝑉𝑜𝑢𝑡 = −𝑉𝐷𝐷
𝐶𝐿 +𝐶𝑎

▪ Boundary between two cases:

▪ When ∆𝑉𝑜𝑢𝑡 = 𝑉𝑇𝑛

𝐶𝑎 𝑉𝑇𝑛
▪ =
𝐶𝐿 𝑉𝐷𝐷 −𝑉𝑇𝑛

𝐶𝑎
▪ When is smaller than this, use case 1, otherwise case 2!
𝐶𝐿
Charge Sharing – Voltage Drop Example
26

▪ Maximum internal capacitance for maximum charge sharing = 30 fF

ҧ
▪ Occurs for 𝐴𝐵𝐶 ത
𝑜𝑟 𝐴𝐵𝐶
▪ Worst case voltage drop = 30/(30+50)*2.5 = 0.94
▪ Cascaded inverter’s switching threshold should be below 2.5-0.94=1.56V!
Charge Sharing – Solution
27

▪ Precharge internal nodes

 Back-Gate Coupling
28

▪ Dynamic gate output voltage can be reduced by backgate coupling

Dynamic NAND Static NAND

Clk Mp
Out1 =1
Out2=0
A=0 In
CL1 CL2

B=0

Clk Me
Clock Feed-Through
29

▪ Coupling between CLK & OUT can affect output

▪ Coupling through CGD of precharge device
▪ OUT can rise above VDD / below VSS
▪ Slower evaluation/precharge

Clock feedthrough
Clk Mp 2.5
Out
1.5
A CL
0.5 Out
B
-0.5
In & Clk
0 0.5 1
Clk Me Time, ns
Cascading Dynamic Gates
30

▪ Biggest drawback of Dynamic Logic:

▪ Dynamic Gates cannot be (simply)
cascaded
▪ During Precharge,
▪ Output of the Driving Gate is charged to
VDD
▪ Turning on the PDN of the Cascaded Gate
▪ During the Evaluation
▪ It takes time to discharge the output of the
Driving Gate (considering it should be Low)
▪ During this time, the PDN of the Cascaded
Gate is incorrectly conducting, discharging
its output
Solution for Cascading Dynamic Gates – Domino Logic
31

▪ Domino Logic
▪ One solution to cascading problem

▪ Each Dynamic Gate is connected to an Inverter

▪ Causing the input of the next gate to be Low after Precharge
▪ Drawback?
▪ Implements only non-inverting logic!
 Domino Logic Example
32

clk

t
A
CLK P1 P2
Vout,1 Vout,2
t
A N2 N4
Vout,1

CLK N1 CLK N3
t
Vout,2

t
Domino Logic – Additional Benefit
33

▪ Can freely add feedback keeper transistor!

PB
CLK P1
VX
Vout
A N2

CLK N1
8-input Complex Logic Gate
34

Using conventional CMOS logic Domino CMOS logic

Domino Logic – Reducing Transistor Count
35

▪ Output of domino is always low during precharge

▪ We don’t actually need the evaluation transistor!

▪ Also known as footless domino!

▪ Drawback?
▪ The precharge must now propagate, creating a constraint on the
precharge time!
Domino Logic – Universality Problem
36

▪ Can only implement non-inverting logic

▪ Sometimes, logic restructuring works

= ABC

= I1 I 2  I 3  I 4 I 5 =
= I1 I 2 + I 3 + I 4 I 5

=G+H
Domino Logic – Universality Problem
37

▪ Using Dual Rail Domino – Similar to DCVSL

▪ It is not ratioed – Thus very useful!

Cascading Dynamic Logic – np-CMOS
38

Clk Mp Clk Me
1→1
Out1
1→0
In1 In4 PUN
In2 PDN In5
In3 0→0
Out2
0→1
(to PDN)
Clk Me Clk Mp

To avoid accidental discharge of Out2

Only 0 → 1 transitions allowed at inputs of PDN
Only 1 → 0 transitions allowed at inputs of PUN
Cascading Dynamic Logic – np-CMOS
39

Clk Mp Clk Me
1→1
Out1
1→0
In1 In4 PUN
In2 PDN In5
In3 0→0
0→1
Out2
(to PDN)
Clk Me Clk Mp

to other to other
PDN’s PUN’s
Choosing a Logic Style
40

▪ Static vs Dynamic
Relevant Reading
41

▪ Jan. M. Rabaey, Digital Integrated Circuits, 2nd Ed.

▪ Chapter 6
▪ Section 6.3!