EE-808 Fall 2024

Digital Integrated Circuit Design

Lecture # 06
Combinational Logic using Static CMOS

Muhammad Imran
[email protected]
Acknowledgement
2

▪ Content from following resources has been used in these lectures

▪ Introduction to Digital Electronic Circuits, Adam Teman, BIU, Israel
▪ Jan. M. Rabaey, Digital Integrated Circuits, 2nd Ed.
▪ Book + Slides
▪ EE-141, UC Berkley, Fall 2010
▪ Sung-Mo Kang, CMOS Digital Integrated Circuits, 3rd Ed.
Contents
3

▪ Combinational Logic in CMOS

▪ Building CMOS Gates
▪ Transistor Sizing for Performance
▪ Fan-In Consideration
▪ Fan-Out Consideration
▪ Power Consumption in Static CMOS
▪ Combinational Logic using Non-Standard Static CMOS
▪ Ratioed Logic
▪ Pass Transistor Logic
Combinational Logic in CMOS
Combinational vs. Sequential Logic
5

▪ Combinational Logic Circuit

▪ The output if function of its current input signals

In Out
Combinational Combinational
In Logic Out Logic
Circuit Circuit

State

Combinational Sequential

𝑶𝒖𝒕𝒑𝒖𝒕 = 𝒇(𝒊𝒏𝒑𝒖𝒕) 𝑶𝒖𝒕𝒑𝒖𝒕 = 𝒇(𝒊𝒏𝒑𝒖𝒕, 𝒑𝒓𝒆𝒗𝒊𝒐𝒖𝒔 𝒊𝒏𝒑𝒖𝒕)

Static vs Dynamic CMOS Circuit
6

▪ Static CMOS
▪ At every point in time, (except during the switching transients) output of
the gate
▪ Is connected to either VDD or VSS via a low-resistive path
▪ Assumes the value of the Boolean function implemented by the circuit
▪ Easier to implement, low-power consumption (at low activity)

▪ Dynamic CMOS
▪ Relies on temporary storage of signal values on the capacitance of high
impedance circuit nodes
▪ Faster and smaller in size
▪ Complex design, more sensitive to noise
Static Complementary CMOS
7

▪ PUN/PDN between VDD-output / GND-output

▪ For every set of input logic values, only one of pull-up or pull-down
network makes connection to VDD or GND
▪ Output node is always at low impedance

VDD

In1
In2 PUN (PMOS only)

InN
F(In1,In2,…InN)
In1
In2 PDN (NMOS only)
InN
PUN and PDN are dual logic networks
Threshold Drops
8

▪ The primary reason for PDN with NMOS / PUN with PMOS is that:
▪ NMOS transistors produce “strong zeros”
▪ PMOS devices generate “strong ones”
NMOS in Series and Parallel
9

▪ Transistors can be thought as a switch controlled by its gate signal

▪ NMOS switch closes when switch control input is high

A B

X Y Y = X if A and B

X B Y = X if A OR B
Y

NMOS Transistors pass a “strong” 0 but a “weak” 1

PMOS in Series and Parallel
10

▪ PMOS switch closes when switch control input is low

A B

X Y Y = X if A AND B = A + B

X B Y = X if A OR B = AB
Y

PMOS Transistors pass a “strong” 1 but a “weak” 0

Building CMOS Gates
Gate Building Methodology
12

▪ Goal is to create a logic function

▪ 𝐹(𝑥1 , 𝑥2 , 𝑥3 , … )

▪ Pull up network should connect output to VDD when

− − −
▪ 𝐹 𝑥1 , 𝑥2 , 𝑥3 , … = 1

▪ Pull down network should connect output to GND when

▪ 𝐹ത 𝑥1 , 𝑥2 , 𝑥3 , … = 1
Building a NAND Gate
13

▪ Original logic:
▪ 𝐹(𝐴, 𝐵) = 𝐴. 𝐵

▪ PD logic:
▪ 𝐹ത 𝐴, 𝐵 = 𝐴. 𝐵

▪ PU logic:
▪ 𝐹 𝐴,ҧ 𝐵
ത = 𝐴ҧ + 𝐵ത
Building a NAND Gate
14

▪ When both A and B are high, output is

low
▪ When either A or B is low, output is high
NOR Gate
15

▪ Original logic:
▪ 𝐹(𝐴, 𝐵) = 𝐴 + 𝐵

▪ PD logic:
▪ 𝐹ത 𝐴, 𝐵 = 𝐴 + 𝐵

▪ PU logic:
▪ 𝐹 𝐴,ҧ 𝐵
ത = 𝐴.ҧ 𝐵ത
NOR Gate
16

▪ When both A and B are low, output is high

▪ When either A or B is high, output is low
Complex Gate
17

▪ Given logic:
▪ 𝐹(𝐴, 𝐵, 𝐶, 𝐷) = 𝐴. 𝐵 + 𝐶. 𝐷

▪ PD logic:
▪ 𝐹ത 𝐴, 𝐵, 𝐶, 𝐷 = 𝐴. 𝐵 + 𝐶. 𝐷
▪ AB, CD: series
▪ (AB)+(CD): parallel

▪ PU logic:
▪ 𝐹 𝐴,ҧ 𝐵,
ത 𝐶,ҧ 𝐷
ഥ = 𝐴ҧ + 𝐵ത . (𝐶ҧ + 𝐷)
ഥ
 Complex Gate – Duality of PDN and PUN
18

▪ Given logic: VDD VDD

▪ 𝐹(𝐴, 𝐵, 𝐶, 𝐷) = 𝐷 + 𝐴. (𝐵 + 𝐶)
C
A
B
SN1 F SN4
F
SN2 D
A A
D SN3 F
D
B C B C A
D
Deriving the pull-up network B C
pull-down network hierarchically by identifying
sub-nets
complete gate
Complementary CMOS Properties
19

▪ Full rail-to-rail swing (VDD or GND)

▪ high noise margins
▪ No direct path steady state current between power and ground
▪ no static power dissipation
▪ Always a path to VDD or GND in steady state
▪ low output impedance
▪ Nearly zero steady-state input current to gate
▪ extremely high input resistance

▪ Complementary gate is naturally inverting

▪ Implements NAND, NOR, XNOR
▪ To implement non-inverting functions, need to add inverter!

▪ Number of transistors to implement N-input logic gate is 2N

Static Property – Data Dependence
20

▪ Noise margins are input pattern dependent

Propagation Delay of Complementary CMOS Gates
21

▪ Propagation delay depends on input patterns

▪ Let’s ignore internal node capacitance for now

Rp Rp
▪ Example : NAND gate
▪ Low to high transition A B
▪ both inputs go low
▪ delay is 0.69 (Rp/2) CL Rn CL
▪ one input goes low
B
▪ delay is 0.69 Rp CL
▪ High to low transition Rn
▪ both inputs go high Cint
▪ delay is 0.69 2Rn CL A
 Delay Dependence on Input Patterns
22

3
Input Data Delay
A=B=1→0
2.5
Pattern (psec)

2 A=B=0→1 67
A=1, B=0→1 64
Voltage [V]

1.5 A=1, B= 1→0 A= 0→1, B=1 61

1 A=B=1→0 45
A=1, B=1→0 80
A= 1→0, B=1 81
0.5
A= 1→0, B=1
0
0 100 200 300 400
-0.5
time [ps]

NMOS = 0.5m/0.25 m
PMOS = 0.75m/0.25 m
CL = 100 fF
Transistor Sizing for Performance
Transistor Resistance
24

▪ Intuitively consider a transistor’s channel

as a resistor
L L
R= =
A W H
▪ H = channel depth
▪ Usually, a constant I
▪ Widening a transistor will reduce the
resistance L
▪ A longer channel will increase the
resistance H

W
Transistor Resistance
25

▪ A series connection of constant width transistors is equivalent to

increasing the length

2R
W/L W/L
W/2L
I
I
▪ A parallel connection of constant length transistors is equivalent to
increasing the width

W/L
R/2
2W/L
W/L
I
I
Transistor Sizing for Timing
26

▪ Approach 1: Match the delay of an inverter

1 1 𝑘′𝑝 = 𝜇 𝑝𝐶 𝑜𝑥
𝑘′𝑝 = 𝑘′𝑛 𝒐𝒓 𝜇𝑝 = 𝜇𝑛
2 2 𝑘′𝑛 = 𝜇 𝑛𝐶 𝑜𝑥
We design for wort-case delay

4
2 2
4
2

2 1 1

Inverter NAND NOR

Transistor Sizing for Timing
27

▪ Stacking PMOS in series should be avoided because of less mobility

of holes – extra large size can increase capacitance
▪ NAND logic is preferred

4
2 2
4
2

2 1 1

Inverter NAND NOR

Transistor Sizing for Timing
28

▪ Approach 2: Match rise and fall time

▪ Example 1
▪ To obtain tr = tf, what is ratio between WP and WN?

▪ Assume 1
𝑘′𝑝 = 𝑘′𝑛 We design for wort-case delay
3

1 1 1 9

9
1
9
1

1 1 1 1
Transistor Sizing for Timing
29

▪ Approach 2: Match rise and fall time

▪ Example 2
▪ To obtain tr = tf, what is ratio between WP and WN? VDD VDD

▪ Assume 1 C 4.5
𝑘′𝑝 = 𝑘′𝑛 A
3
here we want the same down and up resistance . at the bottom we have 2R B 4.5
and up worst case is 9R cause 3R cause of 3L multiply by mobility 3 factor ,
so overall we nee 2R but we have 9R so divide 9R by 4.5( it is the upsize of
all transistor)
D 4.5
F
A 1
D

1 B C
1 1
Fan-In Consideration
Fan-In Considerations
31

▪ Now, let’s consider internal node capacitance (diffusion cap, intrinsic

parasitic cap)
▪ Complex gates with large fan-ins, the internal node capacitance
becomes significant
Propagation Delay with Fan-In
32

▪ Problems of CMOS design

▪ In CMOS logic, for fan-in of N, 2N transistors are required
▪ Unloaded intrinsic propagation delay of the gate increases rapidly as
fan-in increases

▪ For N-input NAND gate :

▪ For L-H transition:
▪ Intrinsic parasitic cap: ~Linear Increase
▪ Pull-up resistance: unchanged
▪ Delay: Linear Increase
▪ For H-L transition:
▪ Intrinsic parasitic cap: >Linear Increase
▪ Pull-down resistance: increases
▪ Delay: Quadratic Increase
Propagation Delay with Fan-In
33

➔ Gates with fan-in greater than 4 should be avoided

Design Techniques for Larger Fan-In
34

▪ Transistor Sizing
▪ Sizing up all TRs
▪ Effective as long as fan-out capacitance dominates (not intrinsic cap)

▪ Progressive Sizing
▪ According to resistance contribution!
▪ Non-uniform scaling
▪ Make TRs closer to output smaller
▪ Can reduce delay by >20%
Design Techniques for Larger Fan-In
35

▪ Input Reordering
▪ Place critical-path transistors closer to output

1 charged 0→1
charged
1 charged 1
discharged
charged 1
0→1 discharged

▪ Logic Restructuring (Boolean manipulations)

▪ Distribute fan-in
Fan-Out Consideration
Designing a Logical Network for Performance
37

▪ Example: Implement F = ABCDEFGH

▪ Which implementation is best?

Designing a Logical Network for Performance
38

CL CL

▪ Is it better to drive a big capacitive load directly with the NAND gate
or after some buffering?
▪ To answer these questions:
▪ We extend the buffer sizing problem to CMOS gates!
Fanout Consideration – Inverter Chain Review
39

Chain Delay:

Stage Delay:
Delay of NAND Gate
40

▪ Consider NAND gate sized for equal resistance as an optimal

inverter

▪ Note
4
▪ 𝐶𝑔,𝐴 = 𝐶𝑔,𝐵 = 4𝐶𝑔,𝑚𝑖𝑛 = 𝐶𝑔,𝐼𝑁𝑉
3
▪ 𝐶out ,𝑁𝐴𝑁𝐷 ≈ 6𝐶𝑑,𝑚𝑖𝑛 𝐶out ,𝐼𝑁𝑉 ≈ 3𝐶𝑑,𝑚𝑖𝑛

▪ Delay of NAND Gate:

▪ 𝑡𝑝,𝑁𝐴𝑁𝐷 = 0.69𝑅NAND 𝐶out = 0.69𝑅INV 𝐶out , NAND + 𝐶Load
Delay of NAND Gate
41

𝐶𝑜𝑢𝑡,𝑁𝐴𝑁𝐷 6𝐶 3
▪
𝐶𝑜𝑢𝑡,𝐼𝑁𝑉
≈ 3𝐶𝑑,𝑚𝑖𝑛 = 2 𝐶𝑔,𝐼𝑁𝑉 = 4 𝐶𝑔,𝑁𝐴𝑁𝐷
𝑑,𝑚𝑖𝑛

▪ 𝑡𝑝0 = 0.69𝑅𝐼𝑁𝑉 𝐶𝑜𝑢𝑡,𝐼𝑁𝑉

𝐶𝑑,𝑚𝑖𝑛
▪ 𝛾= ⇒ 𝐶𝑜𝑢𝑡,𝐼𝑁𝑉 = 𝛾𝐶𝑔,𝐼𝑁𝑉
𝐶𝑔,𝑚𝑖𝑛

▪ 𝑡𝑝,𝑁𝐴𝑁𝐷 = 0.69𝑅𝐼𝑁𝑉 𝐶𝑜𝑢𝑡,𝑁𝐴𝑁𝐷 + 𝐶𝐿

𝐶𝑜𝑢𝑡,𝐼𝑁𝑉 𝛾𝐶𝑜𝑢𝑡,𝑁𝐴𝑁𝐷 𝛾𝐶𝐿

= 0.69𝑅𝐼𝑁𝑉 𝛾 𝐶𝑜𝑢𝑡,𝐼𝑁𝑉
+ 𝐶𝑜𝑢𝑡,𝐼𝑁𝑉

𝑡𝑝0 6𝐶𝑑,𝑚𝑖𝑛 𝛾𝐶𝐿 𝑡𝑝0 𝐶𝐿

= 𝛾+ = 2𝛾 + 3
𝛾 3𝐶𝑑,𝑚𝑖𝑛 𝛾𝐶𝑔,𝐼𝑁𝑉 𝛾 𝐶
4 𝑔,𝑁𝐴𝑁𝐷

4
= 𝑡𝑝0 2 + 3𝛾 𝑓
Delay of NAND Gate
42

4
▪ 𝑡𝑝,𝑁𝐴𝑁𝐷 = 𝑡𝑝0 2 + 𝑓
3𝛾

▪ Compared to
𝑓
▪ 𝑡𝑝,𝐼𝑁𝑉 = 𝑡𝑝0 1 +
𝛾

▪ Conclusions
▪ The intrinsic (unloaded) delay is twice that of an inverter
▪ The fanout increases the delay at a faster pace than an inverter
▪ It is better to drive a load with an inverter than a NAND
Delay of NOR Gate
43

5
▪ 𝑡𝑝,𝑁𝑂𝑅 = 𝑡𝑝0 2 +
3𝛾
𝑓 Derive this as an exercise …

▪ A NOR gate is less efficient than a NAND at driving a load

Fanout Consideration – Inverter vs. Logic Gates
44

▪ Assuming logic gates are sized to have same drive current

▪ Delay increases with different slope
Fanout Consideration – Generalized Basic Delay Equation
45

𝐶𝑒𝑥𝑡
▪ Inverter: 𝑡𝑝 = 𝑡𝑝0 1 + = 𝑡𝑝0 (1 + 𝑓/𝛾)
𝛾𝐶𝑔
logical effort for 2 inputs can be different for example for A input cap is 12 for B its 16 here
we are taking PUN and PDN both so for A logical effort would be 12/3(inv) and B = 16/3(inv)

▪ Logic Gate: 𝑡𝑝 = 𝑡𝑝0 (𝑝 + 𝑔𝑓/𝛾)

▪ Normalize to inverter & assume 𝛾=1: 𝒅 = 𝒑 + 𝒈𝒇 = 𝒑 + 𝒉

▪ 𝒕𝒑𝟎 ∙ 𝒑 : Intrinsic delay (inherent to the gate without loading)

▪ 𝒕𝒑𝟎 ∙ 𝒈𝒇/𝜸 : Effort delay (dependent on fanout of the gate)

▪ 𝒑 : ratio of the intrinsic delay of a complex gate to simple inverter

▪ 𝒈 : Logical effort: function of topology, independent of sizing
▪ 𝒇 : Electrical effort: effective fanout
▪ 𝒉 : Gate effort
Fanout Consideration – Generalized Basic Delay Equation
46

𝐶𝑒𝑥𝑡
▪ Inverter: 𝑡𝑝 = 𝑡𝑝0 1 + = 𝑡𝑝0 (1 + 𝑓/𝛾)
𝛾𝐶𝑔

gate cap involves Gate source , Cox , gate drain of both

Nmos and PMOS
▪ Logic Gate: 𝑡𝑝 = 𝑡𝑝0 (𝑝 + 𝑔𝑓/𝛾) while C intrinsic contains drain body or diff cap + miller
gate drain caps of both N and P mos inverter
C extrinsic contains C wire plus gate caps of next inverter
thats the reason p is called parasitic , Cdmin , Cint is
basically the same thing
▪ In general,
𝑅𝑔𝑎𝑡𝑒 𝐶𝑑,𝑔𝑎𝑡𝑒 𝑅𝑔𝑎𝑡𝑒 𝐶𝑔,𝑔𝑎𝑡𝑒
▪ 𝑝= 𝑔=
𝑅𝑖𝑛𝑣 𝐶𝑑,𝑖𝑛𝑣 𝑅𝑖𝑛𝑣 𝐶𝑔,𝑖𝑛𝑣

▪ Mostly, gates are sized to have 𝑅𝑔𝑎𝑡𝑒 = 𝑅𝑖𝑛𝑣 !

Intrinsic Delay
47

𝒅 = 𝒑 + 𝒈𝒇
Logical Effort
48

𝒅 = 𝒑 + 𝒈𝒇
▪ Logical effort is the ratio of input capacitance of a gate to the input
capacitance of an inverter with the same output current

Cin = 3 unit Cin = 4 unit Cin = 5 unit

g = 4/3 g = 5/3
Logical Effort
49

𝒅 = 𝒑 + 𝒈𝒇
▪ Logical effort is a function of topology, independent of sizing
▪ Logical effort of a gate presents the ratio of its input capacitance to the
inverter capacitance when sized to deliver the same current
▪ Logical effort increases with the gate complexity
▪ Inverter has the minimum logical effort!

▪ Effective fanout (electrical effort) is a function of load/gate size

Logical Effort – Example 1
50

▪ Estimate the frequency of N-stage ring oscillator

▪ Logical Effort: g=1

▪ Electrical Effort: f=1
▪ Parasitic Delay: p=1
▪ Stage Delay: d=2
▪ Frequency: fosc = 1/(2*N*d) = 1/4N
Logical Effort – Example 2
51

▪ Estimate the delay of a fanout-of-4 (FO4) inverter

▪ 𝑑 = 𝑝 + 𝑔. 𝑓
▪ Parasitic delay: p = 1
▪ Logical effort: g = 1
▪ Fanout: f = 4
▪ Delay = 1+4×1 = 5
 Logical Effort
52

𝒅 = 𝒑 + 𝒈𝒇

▪ Logical effort represents that, for a

given load, complex gates need to
work harder than an inverter to
produce similar results

▪ Logical effort tells how much

worse it is at producing output
current than an inverter
Branching Effort
53

▪ When you consider ‘path effort’ branching slows down!

▪ 𝒃: branching effort: how much more effort to put for achieving same
delay with branching

𝐶on−path + 𝐶𝑜𝑓𝑓−𝑝𝑎𝑡ℎ
𝑏𝑖 =
𝐶on−path
Multi-Stage Network
54

▪ Stage delay: 𝒅 = 𝒑 + 𝒈 ∙ 𝒇
▪ p = intrinsic delay, g = logical effort, f = fanout

▪ Path delay: 𝑫 = σ𝑵
𝒊=𝟏 𝒑𝒊 + 𝒈𝒊 ⋅ 𝒇𝒊
𝐶
▪ Path electrical effort: 𝐹 = out
𝐶𝑖𝑛

▪ Path logical effort: 𝐺 = 𝑔1 ⋅ 𝑔2 ⋅ … ⋅ 𝑔𝑁

▪ Path branching effort: 𝐵 = 𝑏1 ⋅ 𝑏2 ⋅ … ⋅ 𝑏𝑁

𝑓1 𝑓2 𝑓 𝑓 .𝑓 .…𝑓
F= . .…. 𝑁 = 1 2 𝑁
𝑏1 𝑏2 𝑏𝑁 𝐵

▪ Total path effort: 𝐻 = 𝐺 ⋅ 𝐹 ⋅ 𝐵 = 𝑔1 𝑓1 ⋅ 𝑔2 𝑓2 ⋅ … ⋅ 𝑔𝑁 𝑓𝑁

▪ Effort delay: 𝐷ℎ = σ𝑁
𝑖=1 ℎ𝑖 where ℎ𝑖 = 𝑔𝑖 ⋅ 𝑓𝑖

▪ Parasitic (intrinsic) delay: 𝑃 = σ𝑁

𝑖=1 𝑝𝑖

▪ Path delay: 𝐷 = σ𝑁 𝑁 𝑁
𝑖=1 𝑑𝑖 = σ𝑖=1 𝑝𝑖 + σ𝑖=1 ℎ𝑖
Multi-Stage Network – Example
55

▪ G = g1 x g2 x g3 x g4 = 20/9
▪ F = Cout/Cin = 20 / 10 = 2
▪ H = G x F x B = 40/9
▪ f1 = x/10, f2 = y/x, f3 = z/y, f4 = 20/z
Multi-Stage Network – Example with Branch
56

▪ G = 1(1 × 1) = 1
▪ F = 90/5 = 18
▪ F.G = 18 Start
▪ B = (15+15)/15=2
▪ f1 = (15+15)/5 = 6 End
▪ f2 = 90/15 = 6
▪ H = g1g2f1f2 = 36
▪ Note H ≠ G×F
▪ H = G ×F ×B = 1 ×18 ×2 = 36
Optimizing Effort for Minimum Delay
57

▪ Each stage should bear the same effort

▪ Stage efforts: ℎ1 = ℎ2 … = ℎ𝑁 ℎ𝑖 = 𝑔𝑖 ⋅ 𝑓𝑖
ℎ𝑁 = 𝐻
𝑁
ℎ= 𝐻
▪ Effective fanout of each stage: 𝑓𝑖 = ℎ/𝑔𝑖

▪ Minimum path delay

෡ = σ 𝑝𝑖 + 𝑔𝑖 𝑓𝑖 = 𝑁𝑝𝑖𝑛𝑣 + 𝑁ℎ = 𝑁𝑝𝑖𝑛𝑣 + 𝑁𝐻1/𝑁
▪ 𝐷
෡ = σ 𝑝𝑖 + 𝑔𝑖 𝑓𝑖 = σ𝑝𝑖 + 𝑁ℎ
▪ 𝐷
Example – Sizing Combinational Logic for Min. Delay
58

▪ Assuming
1
1 b c
▪ 𝑘′𝑝 = 𝑘′
2 𝑛
a
5
Stage 1 Stage 2 Stage 3 Stage 4

▪ Sizing Gates:
▪ Inverter P:N = 2:1 → Size 1 inverter: P=2/3, N=1/3
▪ Size k inverter: P=2k/3, N=1k/3

▪ n-input NAND P:N = 2:n → Size 1 NAND2: P = 2/(2+n), N=n/(2+n)

▪ Size k NAND2: P = 2k/(2+n), N=nk/(2+n)

▪ n-input NOR P:N = 2n:1 → Size 1 NOR2: P = 2n(2n+1), N

= 1/(2n+1)
▪ Size k NOR2: P = 2nk(2n+1), N =
k/(2n+1)
Example – Sizing Combinational Logic for Min. Delay
59

▪ Assuming
1
1 b c
▪ 𝑘′𝑝 = 𝑘′
2 𝑛
a
5
Stage 1 Stage 2 Stage 3 Stage 4

▪ Stage Effort:
▪ Stage 1 2 3 4
▪ Logical Effort (g) 1 5/3 5/3 1
▪ Electrical Effort(f) a/1 b/a c/b 5/c
Example – Sizing Combinational Logic for Min. Delay
60

▪ Assuming
1
1 b c
▪ 𝑘′𝑝 = 𝑘′
2 𝑛
a
5
Stage 1 Stage 2 Stage 3 Stage 4

▪ Path Effort:
▪ F = 5/1 = 5
▪ G = 1 × 5/3 × 5/3 × 1 = 25/9
▪ B=1
▪ H = B × G × F = 125/9
▪ Optimal h
𝑁 4
▪ ℎ= 𝐻= 125/9 = 1.93
Example – Sizing Combinational Logic for Min. Delay
61

▪ Assuming
1
1 b c
▪ 𝑘′𝑝 = 𝑘′
2 𝑛
a
5
Stage 1 Stage 2 Stage 3 Stage 4

▪ Calculating Transistor Sizes:

Stage 1 2 3 4

Stage 𝑎 𝑏 𝑐 5
𝑔1 × = 1.93 𝑔2 × = 1.93 𝑔3 × = 1.93 𝑔4 × = 1.93
Effort (h=gf) 1 𝑎 𝑏 𝑐

𝑎 𝑏 𝑐 5
1 = × 𝑔1 𝑎 = 1.93 × 𝑔2 𝑏= × 𝑔3 𝑐= × 𝑔4
TR size 1.93 1.93 1.93
= 1 (confirm) = 1.93 = 2.23 = 2.59
▪ If there is a branch, stage effort should be calculated with branch effort:
ℎ=𝑏∙𝑔∙𝑓
Example – Sizing with Branch Effort
62

▪ Select gate size y and z for minimum delay from A to B

▪ Path Effort
▪ F = 4.5C/1C = 4.5
▪ G = 4/3×4/3×4/3 = 64/27
▪ B=2×3=6
▪ H = B × G × F = 64
▪ h=4

𝟒.𝟓𝑪 𝟒.𝟓𝑪 𝟒
▪ 𝒛= × 𝒈𝟑 = × 𝟑 = 𝟏. 𝟓𝑪
𝟒 𝟒
𝒛 𝟏.𝟓𝑪 𝟒
▪ 𝒚= × 𝑩𝟐 × 𝒈𝟐 = × 𝟑 × 𝟑 = 𝟏. 𝟓𝑪
𝟒 𝟒
𝒚 𝟏.𝟓𝑪 𝟒
▪ 𝑪= × 𝑩𝟏 × 𝒈𝟏 = × 𝟐 × 𝟑 = 𝟏𝑪
𝟒 𝟒
Another Example
63

▪ Select gate sizes x and y for least delay from A to B

▪ Path Effort
▪ F = 45/8 = 5.625
▪ G = 4/3×4/3×5/3 = 80/27
▪ B=3×2=6
▪ H = B × G × F = 100
3
▪ h= 100 = 4.64

▪ (45/y)(5/3) = 4.64 → y = 16.16

▪ (y/x)(2)(4/3) = 4.64 → x = 9.287
▪ Verifying: (size of 1st NAND): 8=(x/4.64).(3)(4/3)
Method of Logical Effort – Summary
64

▪ Compute the path effort: 𝑯 = 𝑩𝑮𝑭

𝒏
▪ Compute the optimal stage effort: 𝒉 = 𝑯

▪ Sketch the path with this number of stages

▪ Work from either end to back-calculate size

𝑪𝒐𝒖𝒕 𝑪𝒐𝒖𝒕
𝑪𝒊𝒏 = =
𝒇 𝒉/𝒈
Power Consumption in Static CMOS
Power Consumption
66

▪ Power consumption in CMOS:

2
▪ 𝛼0→1 CL VDD 𝑓
▪ Impacted by:
▪ Gate size
▪ Determines capacitance
▪ Rise/fall time
▪ Determines short-circuit power
▪ Device threshold and temperature
▪ Determine leakage power
▪ Switching activity
▪ 𝛼0→1
▪ Static component: function of topology of logic network
▪ Dynamic component: Timing of circuit – glitching!
Switching Activity Factor
67

▪ Dependence on logic function

▪ Assuming, statistically independent inputs
▪ Probability that output will be 0 in one cycle → 𝑝0
▪ Probability that output will be one in next cycle → 𝑝1
▪ Switching activity factor:
▪ 𝛼0→1 = 𝑝0 ∙ 𝑝1 = 𝑝0 ∙ 1 − 𝑝0
Switching Activity Factor
68

▪ Dependence on logic function

▪ 𝛼0→1 = 𝑝0 ∙ 𝑝1 = 𝑝0 ∙ 1 − 𝑝0
▪ For independent and uniformly distributed inputs:
𝑁0 𝑁1 𝑁0 ∙ 2𝑁 −𝑁0
▪ 𝛼0→1 = ∙ =
2𝑁 2𝑁 22𝑁

▪ 𝑁0 / 𝑁1 : Number of zero/one entries in output column of truth table

▪ Example: 2-input NOR gate

𝑁0 ⋅ 2𝑁 −𝑁0 3∙ 22 −3 3
▪ 𝛼0→1 = = =
22𝑁 22⋅2 16
Switching Activity Factor
69

▪ Signal Statistics
▪ Inputs may not be uniformly distributed as assumed earlier!
▪ Now let’s assume inputs are uncorrelated but not uniformly distributed!
▪ Consider a 2-input NOR gate
▪ 𝑝𝑎 / 𝑝𝑏 - Probabilities that inputs A and B are 1!
▪ The probability that output is 1:
▪ 𝑝1 = (1 − 𝑝𝑎 ) ∙ 1 − 𝑝𝑏

▪ Probability of 0 to 1 transition:
▪ 𝛼0→1 = 𝑝0 𝑝1
▪ = [1 − (1 − 𝑝𝑎 ) 1 − 𝑝𝑏 ][(1 − 𝑝𝑎 ) 1 − 𝑝𝑏 ]
Switching Activity Factor
70

▪ Signal Statistics
▪ Transition probabilities for other gates

▪ Derive these as an exercise …

Switching Activity Factor
71

▪ Inter-signal Correlation
▪ Signals may not be uncorrelated as assumed!
▪ Example:

▪ If A and B are uncorrelated and uniformly distributed:

▪ Probability of node C to be 0 → ½
▪ Probability of node C to be 1 → ½
▪ For AND gate:
▪ 𝛼0→1 = 𝑝0 ∙ 𝑝1 = (1 − 𝑝𝑎 𝑝𝑏 ) 𝑝𝑎 𝑝𝑏
1 1 1 1 3
▪ = 1− . . =
2 2 2 2 16
Switching Activity Factor
72

▪ Inter-signal Correlation
▪ Signals may not be uncorrelated as assumed!
▪ Example:

▪ Now C and B are interdependent!

▪ Proceeding as earlier, the resulting 𝛼0→1 = 3/16
▪ Which is wrong!
▪ Since, 𝑍 = 𝐶. 𝐵 = 𝐴.ҧ 𝐴 = 0!
▪ No transition ever takes place!
Switching Activity Factor
73

▪ Inter-signal Correlation
▪ Signals may not be uncorrelated as assumed!
▪ Example:

▪ So, how to incorporate interdependence of B and C?

▪ Use conditional probabilities:
▪ Z equals one if and only if both C and B are 1
▪ 𝑝 𝑍 = 1 = 𝑝(𝐵 = 1, 𝐶 = 1)
▪ If B and C are independent, 𝑝 𝐵 = 1, 𝐶 = 1 = 𝑝 𝐵 . 𝑝 𝐶
▪ And we get same result as before!
Switching Activity Factor
74

▪ Inter-signal Correlation
▪ Signals may not be uncorrelated as assumed!
▪ Example:

▪ 𝑝 𝑍 = 1 = 𝑝(𝐵 = 1, 𝐶 = 1)
▪ If B and C are dependent!
𝑝 𝐵=1 𝑎𝑛𝑑 𝐶=1
▪ 𝑝 𝐶=1𝐵=1 =
𝑝 𝐵
P(B|A) = P(A∩B) / P(A)
▪ 𝑝 𝑍 = 1 = 𝑝 𝐵 = 1, 𝐶 = 1 = 𝑝 𝐶 𝐵 . 𝑝 𝐵 = 0 as 𝑝 𝐶 𝐵 = 0!
 so when 1 comes at all outputs like all of
them will try to go to zero as ( 1 1 = 0)
but for instance after out 1 goes below
certain threshold , out 2 will
Dynamic or Glitching Transitions go up as (1 0 = 1 )and out 3 will go down steadily
according to NAND logic and at out 4 same
thing as out 2 will happen
75

▪ Due to non-zero propagation delay from one logic block to the next!
Reducing Switching Activity
76

▪ Logic Restructuring
▪ Example: F = A.B.C.D

▪ Ignoring glitching and assuming inputs are uncorrelated and uniformly

distributed!
▪ Which one consumes less power?
▪ Calculate transition probabilities!
Reducing Switching Activity
77

▪ Logic Restructuring
▪ Example: F = A.B.C.D

• Chain structure has lower switching activity

• However, tree structure has 0 glitching, so there’s a tradeoff!
Reducing Switching Activity
78

▪ Input ordering

▪ Which one is better for given probabilities?

▪ Activity at output node is same!
▪ Activity at intermediate node:
▪ First case: (1 − 0.5 × 0.2)(0.5 × 0.2) = 0.09
▪ Second case: (1 − 0.2 × 0.1)(0.2 × 0.1) = 0.0196
▪ It is good to postpone the introduction of signals with high transitions (A in
this case)!
Reducing Switching Activity
79

▪ Time-multiplexing sources

▪ Option (b) reduces wiring but what about switching activity?

▪ Assuming same throughput
▪ Time multiplexed version has half the physical capacitance, switched at
twice the frequency!
▪ For random data, both behave same!
▪ But what happens when inputs have some correlation?
 serial ide has to togle between 0 and 1 to send as the
same information as in case of constant A 1 and B 0
so serial has to constantly toggle while paralled are
calm at A 1 and B 0 so we have to see wether we are
Reducing Switching Activity getting random inputs or some constant inputs
serial is good for random switching but for constant
its of no use
80

▪ Time-multiplexing sources

▪ Suppose A is almost always 1 and B is almost always 0!

▪ Parallel network
▪ Switched capacitance is very low because of fewer transitions!
▪ Time-multiplexed network
▪ Bus toggles between 0 and 1!
▪ So, do not time-multiplex a data stream with distinct properties!
Relevant Reading
81

▪ Jan. M. Rabaey, Digital Integrated Circuits, 2nd Ed.

▪ Chapter 6
▪ Sections 6.1 and 6.2!
Combinational Logic using Non-Standard Static CMOS
https://www.youtube.com/watch?v=G0MsZwzf6hc&list=PLOTpKcFOwiQSP6tqPjR7xXylPXTpiIOGD&index=17

Ratioed Logic
Non-Standard CMOS Families
84

▪ Standard CMOS – Leading design family

▪ Drawback?
▪ 2N transistors for N-input logic

▪ Alternatives
▪ Not as robust but take less area!
Ratioed Logic
85

▪ Standard CMOS
▪ Sizing considerations improved the performance (=speed) of the logic
gates, but not their functionality

▪ Ratioed Logic
▪ To ensure functionality, a certain ratio of sizes has to be kept between
various devices that make up the gate
▪ Benefit of Ratioed Logic?
▪ Fewer transistors!
▪ Drawback
▪ Static power consumption, slower response
Ratioed Logic
86

▪ Basic concept
▪ Use the same Pull-Down Network as CMOS
▪ Use a simple Load as its Pull Up Network
▪ Load constantly leaks current from the supply to
the output capacitance
▪ The output is charged when the PDN is closed,
providing a ‘1’
▪ Load’s resistance is much larger than that of
an open PDN
▪ When the PDN is open, the output is pulled
down to VOL
▪ Ratio between the resistance of the Load and
the PDN is crucial in designing such a gate,
hence it is called “Ratioed” Logic.
Ratioed Logic – Resistive Load
87

▪ N transistors + Load
V DD
▪ VOH = V DD

Resistive
▪ V = R PN
OL Load RL
RPN + RL

▪ Asymmetrical response
F
▪ Static power consumption
In1
▪ tpLH= 0.69 RLCL
In2 PDN
In3

VSS
Ratioed Logic – Resistive Load
88

▪ Load Implementation
▪ Early Ratioed Logic designs used a simple resistor as the Load.
▪ This approach had several drawbacks, especially with the difficulty in
resistor implementation in VLSI
Ratioed Logic – Resistive Load
89

▪ Load Implementation
▪ Accordingly, the Load was replaced with a Diode-connected nMOS
(VGD=0) a.k.a. Saturated Load Inverter
▪ This circuit stopped conducting at VGS=VDD-VTn (weak ‘1’) providing a
reduced swing
Ratioed Logic – Resistive Load
90

▪ Load Implementation
▪ To improve the swing, the enhancement nMOS was replaced with a
“Depletion Mode” nMOS.
▪ A special, highly doped nMOS with negative threshold voltage (VTn<0)
▪ Used for some time until the Pseudo nMOS inverter was invented
▪ Replacing the nMOS load with a pMOS connected to ground
Psedudo-NMOS
91

▪ Pseudo-NMOS
▪ Reduced number of transistors over V DD
complementary CMOS
▪ Using a pMOS in the PUN, we get a Strong ‘1’ PMOS
Load
when the PDN is closed
VSS
▪ VOHmax=VDD
F
▪ When the PDN is open, there is a “fight” between In1
the PDN and the pMOS load In2 PDN
In3

V SS
Pseudo-NMOS
Psedudo-NMOS
92

▪ To calculate VOLmin
▪ Equate the pMOS saturation current with the PDN current, assuming
that it consists of nMOS devices in Linear Mode
▪ The drive strength of the PDN is kneq
▪ Assume short channel devices
2
𝑉𝐷𝑆𝐴𝑇 1 2
▪ 𝐼𝐷𝑝 = 𝑘𝑝 𝑉𝐷𝐷 − 𝑉𝑇𝑝 𝑉𝐷𝑆𝐴𝑇 − = 𝐼𝐷𝑛 = 𝑘𝑛𝑒𝑞 𝑉𝐷𝐷 − 𝑉𝑇𝑛 𝑉𝑂𝐿 − 𝑉𝑂𝐿
2 2

𝑘𝑝 𝑉𝐷𝐷 − 𝑉𝑇𝑝 𝑉𝐷𝑆𝐴𝑇 𝜇𝑝 ⋅𝑊𝑝

▪ 𝑉𝑂𝐿 ≈ ≈ ⋅ 𝑉𝐷𝑆𝐴𝑇
𝑘𝑛𝑒𝑞 𝑉𝐷𝐷 −𝑉𝑇𝑛 𝜇𝑛 ⋅𝑊𝑛𝑒𝑞
Psedudo-NMOS
93

𝑘𝑝 𝑉𝐷𝐷 − 𝑉𝑇𝑝 𝑉𝐷𝑆𝐴𝑇 𝜇𝑝 ⋅𝑊𝑝

▪ 𝑉𝑂𝐿 ≈ ≈𝜇 ⋅ 𝑉𝐷𝑆𝐴𝑇
𝑘𝑛𝑒𝑞 𝑉𝐷𝐷 −𝑉𝑇𝑛 𝑛 ⋅𝑊𝑛𝑒𝑞

▪ To get a Low VOLmin

▪ The pMOS should be much smaller than the equivalent width of the nMOS
network
▪ Making the pMOS small means a small charge current
▪ Resulting in a large tpLH!
Psedudo-NMOS
94

▪ Static power dissipation

▪ Direct path between VDD and GND when outputting a ‘0’

2
𝑉𝐷𝑆𝐴𝑇
▪ 𝑃low = 𝑉𝐷𝐷 𝐼low ≈ 𝑉𝐷𝐷 𝑘𝑝 𝑉𝐷𝐷 − 𝑉𝑇𝑝 𝑉𝐷𝑆𝐴𝑇 − 2

▪ Pseudo nMOS won’t usually be used in low power or high frequency

applications
Psedudo-NMOS if PMOS network(PUN) was used there would had been more transistors so for large FAN in
psuedo NMOS is good option.

95

▪ When large fan-in gates are needed, the reduced transistor count
can be attractive
Pseudo nMOS Characteristics
96

▪ Small β ratio (small pMOS, big PDN):

▪ Lower VOL
▪ Better Gain
▪ Less static power
▪ Fast tpHL

▪ But…
▪ Slow tpLH
▪ Bigger capacitive load

▪ In general:
▪ N+1 Transistors
▪ Only 1 NMOS load to previous stage
▪ Make sure RPMOS resistance at least 4 x RPDN
Differential Cascode Voltage Switch Logic (DCVSL)
97
DCVSL Example
98
Pass Transistor Logic
Pass Transistor Logic A bar and B bar require inverters in PTL and simple Static topology
so for PTL 4( 2 + inv2 ) and for stat its 6 (4 + inv2)

100

▪ Basic concept
▪ Reduce the number of transistors required to implement logic
▪ By allowing the primary inputs to drive source and drain terminals in
addition to the gate terminals
▪ Using PTL, number of transistors to implement a 2-input AND gate is
reduced to 4 (instead of 6 for Standard CMOS)
▪ Broadening the PTL Concept, we can make some more interesting
gates
Relay Multiplexer
101

▪ The Pass Transistor concept is based on the use of relay switches

▪ A number of inputs are connected to switches and only one of the
switches is chosen to be transferred to the output
▪ In essence, we have created a Multiplexer

Switch Out
Network
Inputs
 NMOS
source = out put
Pass Transistor Logic drain = input

102

▪ A simplification of the relay multiplexer:

▪ Connect two inputs to a single nMOS transistor
▪ One to the gate and the other to one of the diffusions (source/drain):

Y = A B

▪ It looks like we got an AND gate with a single transistor:

▪ When B=‘1’, it passes A to the output
▪ When B=‘0’ it blocks the output
▪ But this is incorrect
▪ When the nMOS is switched off and the output node stays floating
▪ Its value depends on its previous state
Pass Transistor Logic – AND Gate
103

▪ In fact, this type of a switch is often used in digital and analog

circuits
▪ But it is not an AND gate

▪ How to get an actual AND gate?

▪ By adding a path to GND when B=‘0’

▪ We can get this by adding an nMOS

ത
▪ With its gate connected to 𝐵
▪ And its source connected to GND

▪ This is a basic AND Gate in PTL!

Y = A B
Pass Transistor Logic – AND Gate
104

▪ This AND gate has a drawback

▪ nMOS transistors passes a Weak ‘1’

▪ VOHmax of this gate is only VDD-VTn, at

which point the switch will turn off

Y = A B
▪ We cannot drive another PTL gate input
with this output

Y = VDD − 2 VTn
Pass Transistor Logic – AND Gate
105

▪ Multiple Vth drop should be avoided

Cascading Pass Transistor Logic AND Gate
106

▪ However, we can connect the output to the next

gate’s diffusion input

Y = VDD − VTn

Y = A B
▪ There is some signal degradation
▪ Need to add a CMOS Inverter every few gates to
replenish the level

▪ This gate requires less power than a CMOS AND

(lower capacitance, reduced swing)
▪ It may cause static power on the partially on
inverters it drives
Static Power Consumption
EDI

■
due to body effect the output after
1st stage can be near vdd/2 as Vt
is more than ususal case , body
effect is due to some reverse bias
in body terminal which increase
1
Example -An inverter after a PTL AND gate and drive the input high
Vsap =Vrn 3

the vt if body and source are not x VDD-VTn

=
common etc look at google
for proper definition. so it will
cause both transistor to conduct
even 1 is fully working and 2nd is

..
is working partially for example
PMOS partially and NMOS fully
it will cause to loose power
and our output will not be good 1

• The output will be pulled up to V00-Vrn

• But due to the body effect,Vrn >Vrno·
• The input to the next stage provides VsGp = V00-(V00-Vrn)
• If this is larger than Vrp, then
• The PMOS is conducting, and static current will flow freely
• Even if it VsGp<Vrp, this transistor is in weak inversion and dissipates
substantial static power
Pass Transistor Logic and VTC
108

▪ To analyze the static properties of the PTL

AND gate B

▪ Let’s draw its VTC A M1 Out

▪ We’ll start with the VTC from A to Out with B
M2
B=‘1’

▪ The output simply follows the input until the

pass transistor closes at VDD-VT
VDD-VT

▪ This input doesn’t have the required

regenerative property for a digital gate

A
VDD-VT
Pass Transistor Logic and VTC
109

▪ What about the VTC from B to Out with A=‘1’? B

▪ Starting at B<VT, M1 is off and M2 is on
▪ We get Vout=0
A M1 Out
▪ M2 is on until B=VDD/2
Out
▪ But when B=VT, M1 turns on B M2
▪ Vout will slowly rise with B
▪ At B=VDD/2, M2 turns off and
▪ M1 has no contention VDD-VT
▪ Vout will “jump” to VDD/2-VT
▪ And rise linearly until
▪ VOHmax=VDD-VT
VDD/2-VT

VDD/2
VT
Pass Transistor Logic – Characteristics
110

▪ PTL gates are non-regenerative and therefore not digital.

▪ To use them as digital gates they must be followed by a CMOS buffer!

▪ PTL gates do not present a rail-to-rail swing

▪ Therefore, cascaded stages may dissipate static power.
▪ Cascading PTL gates through gate inputs causes loss of signal and is
therefore not allowed

▪ However, certain functions can be implemented with fewer

transistors than CMOS
▪ And in certain cases, specific transitions may be faster
Robust Pass Transistor Design
111

▪ Level Restoration
▪ Solving the problem of Weak ‘1’
▪ PTL AND gate, followed by an inverter with
a feedback loop to a pMOS transistor
▪ When node X is high (VDD-VTn),
▪ The Inverter outputs a ‘0’, opening
the pMOS “bleed” transistor
▪ This restores the level at X to VDD
▪ When node X makes a ‘1’ to ‘0’
transition
▪ There is a “fight” between the bleed
transistor and the low input

▪ Need careful Ratioed Sizing to make

the circuit work properly
Robust Pass Transistor Design
112

▪ Level Restorer Sizing

▪ The level restorer “fights” the pass transistor
▪ When pulling down through the diffusion input
▪ Therefore, the pass transistor must be strong enough
▪ To flip the cascaded inverter
▪ We can solve this problem by disconnecting the feedback

B P1 P1
AA
M1 Vx Out M1
B
M2
Robust Pass Transistor Design
113

▪ Level Restorer Sizing

▪ Now we just have to make sure that the stable state
of VX is lower than the inverter’s VM

I DSn (sat ) = I SDp (vel. sat )

VSGp=VDD
V
find kn k  Vx  DD VSDp=VDD-Vx
p 2 P1
M1

VGSn=VDD
VDSn=Vx
Complementary Pass Transistor Logic
114

▪ Differential / Complementary Transmission Logic

▪ Inherently differential outputs

▪ Logic function and its complement
▪ Reduced transistor count as no extra inverters needed
▪ Helps realize complex functions such as XOR and Adders using small number of
transistors!
▪ All CPL gates have same topology, using 4 pass transistors and complementary
inputs!
▪ Purely nMOS pass-transistor network
▪ Elimination of pMOS → Reduce the parasitic cap significantly
Complementary Pass Transistor Logic
115

▪ AND / NAND

B B A B f
0 0
0 1
A N1 1 0
1 1
B N2 AB
A B f
0 0
N3
A 0 1
1 0

B N4 AB 1 1
Complementary Pass Transistor Logic
116

▪ OR / NOR

B B A B f
0 0
0 1
A N1 1 0
1 1
B N2 A+B
A B f
0 0
N3
A 0 1
1 0

B N4 A+B 1 1
Complementary Pass Transistor Logic
117

▪ XOR / XNOR

B B A B f
0 0
0 1
A N1 1 0
1 1
A N2 A⊕B
A B f
0 0
N3
A 0 1
1 0

A N4 A⊕B 1 1
Complementary Pass Transistor Logic
118

▪ Problems
▪ Process complexity : Complementary input signals
▪ Threshold-voltage drop : Reduced noise margin
▪ Low threshold-voltage is needed : Subthreshold conduction
▪ Similar complexity as conventional CMOS realization
▪ CPL-based XOR gate

• Cross-coupled pMOS pull-up

transistors : Speed up the output
response

• Level restoration
• Less of a ratio problem
• The restorer is turned off by
the opposite circuit
Transmission Gates
Transmission Gates
120

▪ Commonly used implementation of PTL

▪ nMOS and pMOS connected in parallel
▪ We get both strong 1 and strong 0, achieving a
full swing

▪ Transmission gate is a bidirectional switch

▪ Allows signals to pass when control signal is on
▪ 4 transistors for implementation
B = A, if C = '1'
Transmission Gate Example
121

▪ Consider 0->1 transition

VGSn=VDD-Vout
VDSn=VDD-Vout
N1
Vin Vout
P1
VSGp=VDD
VSDp=VDD-Vout
▪ At the beginning of the transition:
▪ Vout=0, so both transistors are strongly velocity saturated
▪ As the output is charged,
▪ The resistance of the nMOS rises, while the resistance of the pMOS stays
relatively constant
Resistance of Transmission Gate
122

VGSn=VDD-Vout
VDSn=VDD-Vout
N1
Vin Vout
P1
VSGp=VDD
VSDp=VDD-Vout

𝑉𝐷𝑆𝑛 𝑉𝐷𝑆 1 1 1
▪ 𝑅𝑛 = = 𝑉2
= 𝑉 = 𝑉 −𝑉 = 𝑉𝐷𝐷 𝑉𝑜𝑢𝑡
𝐼𝐷𝑆𝑛
𝑘𝑛 𝑉𝐺𝑆 −𝑉𝑇𝑛 𝑉𝐷𝑆 − 𝐷𝑆 𝑘𝑛 𝑉𝐺𝑆 −𝑉𝑇𝑛 − 𝐷𝑆 𝑘𝑛 𝑉𝐷𝐷 −𝑉𝑜𝑢𝑡 −𝑉𝑇𝑛 − 𝐷𝐷 𝑜𝑢𝑡 𝑘𝑛 − −𝑉𝑇𝑛
2 2 2 2 2

𝑉𝐷𝑆𝑝 𝑉𝐷𝑆 1 1 1
▪ 𝑅𝑝 = = 𝑉2
= 𝑉 = 𝑉 −𝑉 = 𝑉 𝑉
𝐼𝐷𝑆𝑝
𝑘𝑝 𝑉𝐺𝑆 −𝑉𝑇𝑝 𝑉𝐷𝑆 −𝐷𝑆 𝑘𝑝 𝑉𝐺𝑆 −𝑉𝑇𝑝 − 𝐷𝑆 𝑘𝑛 −𝑉𝐷𝐷 −𝑉𝑇 − 𝑜𝑢𝑡 𝐷𝐷 𝑘𝑛 − 𝐷𝐷 − 𝑜𝑢𝑡 −𝑉𝑇
2 2 2 2 2
Resistance of Transmission Gate
123
2-Input Mux using CMOS
124

▪ 2-Input Multiplexer
▪ F = A S + BS

▪ Implementation in CMOS
▪ PDN:

F = A S + B  S
▪ PUN:

( )
F = A  S + B  S = A  S  B  S = A + S  (B + S )

▪ Requires 10 transistors!
2-Input Mux using Transmission Gate Logic
125

▪ Uses only 6 transistors

F = A S + B  S
4-Input Mux using Transmission Gate Logic
126
2-Input XOR using CMOS
127

▪ Using standard CMOS

▪ PUN:

F = A B + A B
▪ PDN: F = A B + A B

(
F = A B + A B = A B  A  B = A + B )(A + B )
▪ Requires 12 transistors
2-Input XOR using Transmission Gate Logic
128

▪ Only 6 transistors needed!

▪ When B=‘1’:
▪ The input stage is a CMOS inverter and
the Transmission Gate is closed!
▪ Hence:

Y = A B
▪ When B = ‘0’:
▪ The input stage closes both transistors,
but the Transmission Gate is open!
▪ Hence: Y = A  B + A B

Y = A B
2-Input XOR using Transmission Gate Logic
129
Tri-State Buffer
130

▪ A transmission gate enables a high impedance output state

▪ This will enable the decoupling of input and output
▪ This structure is used for driving buses
Pass Transistor Logic – Summary
131

▪ Pass transistor logic is a low transistor count CMOS alternative, but:

▪ It is non-digital, so every few stages we must insert a CMOS gate
▪ It suffers from depleted high levels, so we should consider using a
level-restorer
▪ It is very asymmetric, so we should carefully analyze each path before
using it
▪ However, the concept of a pass transistor can be very useful:
▪ We can build special gates (transmission gate, XOR, MUX)
▪ We can use it as a switch
▪ We can build interesting logic families (CPL, GDI, etc.)
Relevant Reading
132

▪ Jan. M. Rabaey, Digital Integrated Circuits, 2nd Ed.

▪ Chapter 6
▪ Section 6.2!