Second Year of Computer Engineering (2019 Course)

210254:MICROPROCESSOR
Savitribai Phule Pune University
Ganeshkhind Rd, Ganeshkhind, Pune, Maharashtra

Presented by:

Assistant Professor Computer Engineering

LoGMIEER , Nashik
Teaching/Examination Scheme
Microprocessor
 Microprocessor

 Unit 1: Introduction to 80386

 Unit 2: Bus Cycles and System Architecture

 Microprocessor

 Unit 1: Introduction to 80386

 Unit 2: Bus Cycles and System Architecture

Brief History of Intel Processors
 Intel
 1971 - 4004
• First microprocessor
• All CPU components on a single chip
• 4 bit, Single Core

 Followed in 1972 by 8008

• 8 bit, Single Core
• Both designed for specific applications

 1974 - 8080
• Intel’s first general purpose microprocessor (8 bit)
 x86 Evolution
• 80286
– 16 bit
• 8086
– much more powerful
– 16 bit • 80386
– instruction cache, prefetch few – 32 bit
instructions – Support for multitasking
– 8088 (8 bit external bus) used in first
IBM PC • 80486
– sophisticated powerful cache and
instruction pipelining
– built in maths co-processor
 x86 Evolution
• Pentium • Pentium III
• Superscalar • Additional floating point instructions for 3D
graphics
• Multiple instructions executed in parallel
• Pentium 4
• Pentium Pro
• Note Arabic rather than Roman numerals
• Increased superscalar organization
• Further floating point and multimedia
• Aggressive register renaming enhancements
• branch prediction
• data flow analysis
• Core
• speculative execution • First x86 with dual core

• Pentium II • Core 2
• MMX technology • 64 bit architecture
• graphics, video & audio processing • Core 2 Quad – 3GHz – 820 million transistors
• Four processors on chip
Refer Intel web pages for detailed information on processors
80386 DX Features and Architecture,
Programmers Model
 Features of 80386DX
• Flexible 32-bit Microprocessor
– 8, 16, 32-Bit Data Types • Hardware Debugging Support
– 8 General Purpose 32-Bit Registers
– 32 bit ALU • 3 stage Pipeline
– 32 bit Data Bus(4 memory Bank)
• Multitasking
– 32 bit Address Bus( 4 GB Memory)
• Operating Speed-16,20,25,33 MHz
• Very Large Address Space
– 4 Gigabyte Physical • SX (16 bit Data Bus)
– 64 Terabyte Virtual DX(32 bit Data Bus)
– 4 Gigabyte Maximum Segment Size
• Integrated Memory Management Unit
– Segmentation and Paging
– 4 Levels of Protection
– Fully Compatible with 80286
 80386DX Architecture

Memory Management Unit

Bus Control Unit

Central Processing Unit

 80386DX Architecture

The Intel386DX consists of

• A central processing unit,
• Execution unit
• Instruction unit

• A memory management unit and

• Segmentation unit
• Paging unit

• A bus interface.
• offers address pipelining, dynamic data bus sizing, and direct Byte Enable signals for
each byte of the data bus
 Execution Unit
• The execution unit contains the
 Eight 32-bit general purpose registers which are used for both address calculation, data
operations and

 A 64-bit barrel shifter used to speed shift, rotate, multiply, and divide operations.

• The multiply and divide logic uses a 1-bit per cycle algorithm.

• The multiply algorithm stops the iteration when the most significant bits of the multiplier are
all zero.

• This allows typical 32-bit multiplies to be executed in under one microsecond.

 Execution Unit (Cont…)
 The linear address consists of two components:
• The segment base address and
• An effective address.

 The effective address is calculated by using four address elements:

• DISPLACEMENT: An 8-, 16- or 32-bit immediate value
• BASE: The contents of any general purpose register. It is generally used by compilers to point
to the start of the local variable area.
• INDEX: The contents of any general purpose register except for ESP. The index registers are
used to access the elements of an array, or a string of characters.
• SCALE: The index register's value can be multiplied by a scale factor, either 1, 2, 4 or 8. Scaled
index mode is especially useful for accessing arrays or structures.

EA = Base Register + (Index Register * Scaling) + Displacement.

 Instruction and Segmentation
Unit
Instruction Unit:

The instruction unit decodes the instruction opcodes and stores them in the decoded
instruction queue for immediate use by the execution unit.

Segmentation Unit:

Segmentation allows the managing of the logical address space by providing an extra
addressing component, one that allows
 easy code
 data relocatability, and
 efficient sharing
 Paging Unit
• The paging mechanism operates beneath and is transparent to the segmentation
process, to allow management of the physical address space.

• Each segment is divided into one or more 4K byte pages.

 Programmers Model
• Intel386 DX base architecture registers:

 General data and address registers

 Segment selector registers

 Instruction pointer

 Flags register
Register Organization of 80386
Flags Register
Operating modes, Addressing modes
and data types
 Processing Modes
• The Intel386 DX modes of operation: • Protected mode:
– Real Address Mode (Real Mode), and – Natural 32-bit environment, in which all
– Protected Virtual Address Mode instructions and features are available.
(Protected Mode). – It provides access to the sophisticated
– Virtual 8086 mode (V86 Mode). memory management, paging and privilege
capabilities of the processor

• Real-address mode (Real mode):

– Power on default mode :mode of the • Virtual 8086 mode (V86 Mode):
processor immediately after RESET. – It is a dynamic mode within protected mode.
– Upward Compatibility. – processor can repeatedly and rapidly switch
– Faster 8086: In this mode the Intel386 between V86 mode and protected mode.
DX operates as a very fast 8086, – CPU enters V86 mode from protected mode
– but with 32-bit extensions if desired. to execute an 8086 program, then leaves
V86 mode and enters protected mode to
continue executing a native 80386 program
 80386 Addressing Modes
 Addressing modes indicate a way of locating data or operands.
 Describes the type of operands and the way they are accessed for executing an instruction.
 The method by which address of source data and destination address of result is given in the
instruction is called as “ Addressing Modes”.
 The 80386 Microprocessor Provide 11 addressing modes
• Register addressing Mode
• Scaled Index addressing Mode
• Immediate addressing Mode
• Based Index addressing Mode
• Direct addressing Mode
• Based Scaled Index addressing Mode
• Register Indirect addressing Mode
• Based Index addressing Mode with Displacement
• Based addressing Mode
• Based Scaled Index addressing Mode with
Displacement
• Index addressing Mode
 Register Addressing Modes
• The data is stored in a register and it is referred using a particular register.

• All register accept IP used in this addressing mode.

• The 8/16/32 bit data required to execute an instruction is present in 8/16/32 bit register is
given along with the instruction is called “Register addressing mode.”

 Example : ADD EAX,EBX

 Immediate addressing mode
• In this addressing mode, immediate data is part of instruction.

• The 8/16/32 bit data required to execute an instruction is given directly along with the
instruction is called “Immediate addressing mode”.

 Example: Mov AX,0020H

 Direct and Register Indirect
addressing mode
• Direct addressing mode
The operand's offset is contained as part of the instruction as an 8-, 16- or 32-bit
displacement.
In Direct addressing mode the effective address of memory location where the operand
is present is written directly in the instruction.
 Example: MOV AX, [5000H]

• Register Indirect Mode:

A BASE register contains the address of the operand.

 Example: MOV EAX, [EBX]

 Based and Index addressing
mode
• Based addressing mode
Based Mode: In this addressing mode, the offset address of the operand is given by the
sum of the contents of Base Register and Displacement.
 Example: MOV ECX, [EAX+24]

• Index addressing Mode:

An INDEX register's contents is added to a DISPLACEMENT to form the operands offset.

 Example: ADD EAX, TABLE[ESI]

 Scaled Index & Based Index
addressing mode
• Scaled Index addressing mode
An INDEX register's contents is multiplied by a scaling factor which is added to a
DISPLACEMENT to form the operands offset.

 Example: IMUL EBX, TABLE[ESI*4],7

• Based Index addressing Mode:

The contents of a BASE register is added to the contents of an INDEX register to form the
effective address of an operand.

 Example: MOV EAX, [ESI] [EBX]

 Other addressing mode
• Based Scaled Index addressing mode: The contents of an INDEX register is multiplied by a
SCALING factor and the result is added to the contents of a BASE register to obtain the
operands offset.

 Example: MOV ECX, [EDX*8] [EAX]

• Based Index addressing Mode with Displacement: The contents of a BASE register is added
to the contents of an INDEX register to form the effective address of an operand.

 Example: ADD EDX, [ESI] [EBP+00FFFFF0H]

• Based Scaled Index addressing Mode with Displacement: The contents of an INDEX register
are multiplied by a SCALING factor, the result is added to the contents of a BASE register and a
DISPLACEMENT to form the operand's offset.

 Example: MOV EAX, LOCALTABLE[EDI*4] [EBP+80]

 Data Types
Fundamental Data Types:
• Byte
• Word
• Doubleword
Byte, word and doubleword in
memory
80386 Data Types
80386 Instruction Set
 Agenda
• Data Movement Instructions
• Binary Arithmetic Instructions
• Decimal Arithmetic Instructions
• Logical Instructions
• Control Transfer Instructions
• String and Character translation Instructions
• Instructions for Block-Structured Languages
• Flag Control Instructions
• Coprocessor Interface Instructions
• Segment Register Instructions
• Miscellaneous Instructions
 Data Movement Instructions
• Provides convenient methods for moving bytes, words or
doublewords of data between memory and the register.

• Various Classes
o General purpose data movement instructions
o Stack manipulation instructions
o Type-conversion instructions
 General Purpose data movement
instructions
• MOV (Move): Transfers a byte, word or doubleword from the source operand
to the destination operand

• Operand options
– To a register from memory
– To memory from a register
– Between general registers
– Immediate data to a register
– Immediate data to a memory

• Memory to Memory and Segment register to segment register, not allowed

• MOVS: string manipulation instruction for memory to memory moves
 Example: MOV EAX, EBX ; Moves contents of EBX to EAX
• XCHG (Exchange): Swaps the contents of two operands.

• Operands may be two registers or a register with memory

 Example: XCHG EAX, EBX
(it exchanges the contents of register with an another register or the content of
register with content on memory location and vice-versa.)

• Does not require temporary location to save the contents of one

operand while the other is being loaded
 Stack manipulation Instructions
• PUSH

• PUSHA

• POP

• POPA
 Type Conversion Instructions

• Converts bytes to words, words to •CBW: (Convert byte to word)

doublewords and doublewords to 64-bit AL  AX
items •CWD: (Convert word to doubleword)
AX  DX:AX
• Specially useful for converting signed
•CDQ: (Convert doubleword to quadword)
integers
EAX  EDX:EAX
• Two classes: •CWDE: (Convert word to doubleword extended)
 The forms CBW, CWD, CDQ and CWDE AX  EAX
(Operates on EAX) •MOVSX: (Move with sign extension) sign-extends
 MOVSX and MOVZX (One register an 8-bit to 16-bits and 8- or 16- bit value to 32- bit
operand and other may be register or value
memory) •MOVZX: (Move with zero extension) zero-
extended
 Binary Arithmetic Instructions
• Addition and subtraction instructions
– ADD (Add integers)
– ADC (Add integers with carry)
– INC (Increment)
– SUB (Subtract integers)
– SBB (Subtract integers with borrow)
– DEC (Decrement)

• Comparison and Sign change

– CMP (Compare)
– NEG (Negate) subtract from zero
 Binary Arithmetic Instructions
• Multiplication Instructions: • Division Instructions:
• MUL (Unsigned Integer multiply) • DIV (Unsigned Integer division)

Source Accumulator Result Size of Source Dividen Result Result

(Multiplier (Multiplicand (Product) operand d (Quotien (Remainder)
) ) [Double-length] (Divisor) t)
8-bit AL AX 8-bit AX AL AH
16-bit AX DX:AX 16-bit DX:AX AX DX
32-bit EAX EDX:EAX 32-bit EDX:EAX EAX EDX

• IDIV (Signed Integer division)

• IMUL (Signed Integer multiply) Same register combinations
Three variations: One-, two- and three-
operand form
 Decimal Arithmetic Instructions
 Decimal arithmetic is performed in
 Packed BCD Adjustment instructions
combination with binary arithmetic
• DAA (Decimal adjust after addition)
instructions.
• DAS (Decimal adjust after subtraction)

• To adjust the results of a previous binary

arithmetic operation to produce a valid
packed or unpacked decimal result  Unpacked BCD Adjustment instructions
• AAA (ASCII Adjust after Addition)
• To adjust the input to a subsequent binary • AAS (ASCII Adjust after Subtraction)
arithmetic operation so that the operation • AAM (ASCII Adjust after Multiplication)
will produce a valid packed or unpacked • AAD (ASCII Adjust before division)
decimal result
 Logical Instructions
 The Boolean operation instructions

Bit test and modify instructions

Bit scan instructions

Rotate and shift instructions

Byte set on condition

 Logical Instructions (Cont…)
 The Boolean operation instructions
Boolean operation instructions:

Bit test and modify instructions • NOT:

• AND:
Bit scan instructions
• OR:
Rotate and shift instructions
• XOR:

Byte set on condition

 Logical Instructions (Cont…)
 The Boolean operation instructions

Bit test and modify instructions

Bit scan instructions

Rotate and shift instructions

Byte set on condition

 Logical Instructions (Cont…)
Bit test and modify instructions: Bit Scan Instructions:
• Operates on single bit within the
operand (Register or Memory) • Scan a word or doubleword for a one-bit
and store the index of the first set bit into a
register
• Bit location is specified as an offset
from low-order end of the operand
Instruction Effect on Effect on Selected • ZF is set if entire operand is zero
CF Bit  BSF (Bit Scan Forward)
BT (Bit test) CF  BIT (none)  BSR (Bit Scan Reverse)
BTS (Bit test and Set) CF  BIT BIT  1
BTR (Bit test and Reset) CF  BIT BIT  0
BTC (Bit test and CF  BIT BIT  NOT (BIT)
Complement)
 Logical Instructions (Cont…)
 The Boolean operation instructions

Bit test and modify instructions

Bit scan instructions

Rotate and shift instructions

Byte set on condition

 Logical Instructions (Cont…)
• Shift and Rotate Instructions: Byte set on Condition instructions:
– Shift instructions
• SAL (Shift Arithmetic Left) • Sets a byte to Zero or One depending on any
• SHL (Shift Logical Left) of the 16 conditions defined by the status
• SHR (Shift Logical Right) flags
• SAR (Shift Arithmetic Right)
SETcc (Set byte on condition cc)
– Double shift instructions
• SHLD (Shift Left Double) • Test Instructions:
• SHRD (Shift Right Double)
TEST (Test) performs the logical “and”
– Rotate instructions
• ROL, ROR, RCL, RCR
 Control Transfer Instructions

Control Transfer Instructions  Unconditional transfer Instructions

(Near and Far)

Unconditional Transfer
• JMP (Jump)- one way transfer of execution
Instructions

• CALL (Call procedure)

Conditional Transfer
Instructions
• RET (Return from procedure)

• IRET (Return from interrupt)

 Control Transfer Instructions
 Conditional transfer instructions
• Conditional jump instructions
 Control Transfer Instructions

 Loop Instructions: (before testing the Software generated interrupts

condition/s it decrements ECX) • INT n (Software interrupt)
• LOOP (Loop while ECX not zero)
• LOOPE (Loop while equal) and • INTO (Interrupt on Overflow)
LOOPZ (Loop while zero)
• LOOPNE (Loop while not equal)
and LOOPNZ (Loop while not • BOUND (Detect value out of range. BOUND
ensures that a signed array index is within
zero) the limits specified by a block of memory
consisting of an upper and a lower bound.)
 Executing a Loop or Repeat zero
times
• JCXZ (Jump if ECX zero)
 String and Character translation
instructions
• Set of primitive string instructions Repeat prefixes
(Operand B/W/D) • REP: repeat while ECX not zero
–MOVS: Move string • REPE / REPX: repeat while equal or zero
–CMPS: Compare string • REPNE / REPNZ: repeat while not equal or
–SCAS: Scan string not zero
–LODS: Load string
–STOS: Store string

• Indirect, indexed addressing with auto-

incrementing/decrementing index
–Indexes: ESI & EDI
–Control flag: DF
–Control flag instruction: CLD and STD
 Instructions for Block-
Structured Languages
To provide machine-language support for functions normally
found in high-level languages

– ENTER (Enter Procedure): ENTER creates the stack frame

required by most block-structured high-level languages.

– Leave (Leave procedure): LEAVE reverses the actions of

the ENTER instruction. By copying the frame pointer to the
stack pointer, LEAVE releases the stack space used by a
procedure for its local variables.
 Flag Control Instructions
Carry and Direction Flag control instructions
 Flag transfer instructions

• LAHF (Load AH from Flags)

• SAHF (Store AH into Flags)

• PUSHF (Push flags)

• POPF (Pop flags)

• Segment-register transfer instructions • Data pointer instructions
–MOV –LDS (Load pointer using DS)
–POP –LES (Load pointer using ES)
–PUSH –LFS (Load pointer using FS)
–LGS (Load pointer using GS)
–LSS (Load pointer using SS)
•Far control transfer instructions
–Direct far JMP
–Indirect far JMP
–Far CALL
–Far RET
 Miscellaneous Instructions
 Address calculation instruction
• LEA (Load effective address)

 No-operation instruction
• NOP (No operation)

 Translate instruction
• XLAT
 Microprocessor

 Unit 1: Introduction to 80386

 Unit 2: Bus Cycles and System Architecture

 Unit 2:
Bus Cycles and System Architecture
 Unit 2:
Bus Cycles and System Architecture

Initialization
 Initialization

• After a signal on the RESET pin, certain registers of 80386 are

set to predefined values.

• These values are adequate to enable execution of a bootstrap

program.
 Processor State after RESET

• Contents of EAX depends on results power-up self test

• Self-test may be requested externally by assertion of BUSY# at the end of

RESET (EAX=0 if the 80386 passed the test, else 80386 unit is faulty)

• If self-test is not requested , EAX is undefined

• DX holds a component identifier and revision number

(DH=3, indicates 80386, DL=unique identifier of the revision level)
 Processor State after RESET

• Control Register 0 (CR0) contains

State of flags and other registers
Functional Pin Diagram
Pin Description Table
Pin Description Table (Cont…)
 I/O Addressing

The 80386 allows input/output to be performed in either of two

ways:
a. By means of a separate I/O address space (using specific I/O
instructions)

b. By means of memory-mapped I/O (using generalpurpose

operand manipulation instructions )
 Separate I/O address space
(An Isolated I/O)
 I/O devices treated separately from memory.
• Hardware and software architecture of
8088/8086 support separate memory I/O
address space.

 Can be accessed as either byte-wide or word-wide.

 Can be treated as either independent byte-wide

I/O ports or word-wide I/O ports.

 Page 0:
• Certain I/O instructions can only perform
operations to ports in this part of the address
range.
• Other I/O instructions can input/output data
for ports anywhere in the address space.
Separate I/O address space
(An Isolated I/O)
Advantages: -
 1 MByte memory address space is available for use
with memory.
 Special instructions have been provided in the
instruction set of 8088/8086 to perform isolated
I/O input and output operations.
 These instructions have been tailored to maximize
I/O performance.

Disadvantages: -
 All input and output data transfers must take place
between AL or AX register and the I/O port
 Memory-mapped I/O

I/O devices is placed in memory

address space of the
microcomputer.
• The memory address space is
assigned to I/O devices.

• MPU looks at the I/O port as

though it is a storage location in
memory.

• Make use of instructions that affect

data in memory rather than special
input/output instructions.
Memory-mapped I/O
Advantages:
 Many more instructions and addressing
modes are available to perform I/O
operations.
 I/O transfers can now take place
between I/O port and internal registers
other than just AL/AX.

Disadvantages:
 Memory instructions tend to execute
slower than those specifically designed
for isolated I/O.
 Part of the memory address space is lost
 I/O Instructions

There are two classes of I/O instruction:

1. Those that transfer a single item (byte, word, or doubleword)
located in a register.

2. Those that transfer strings of items (strings of bytes, words, or

doublewords) located in memory.

These are known as "string I/O instructions" or "block I/O

instructions".
 Register I/O Instructions

• The I/O instructions IN and OUT

are provided to move data
between I/O ports and the EAX
(32-bit I/O), the AX (I6-bit I/O), or
AL (8-bit I/O) general registers.

• IN and OUT instructions

addresses I/O ports either
directly, with the address of one of
up to 256 port
 Block I/O Instructions

• The block (or string) I/O instructions INS and OUTS move blocks of
data between I/O ports and memory space.

• Block I/O instructions use the DX register to specify the address of a

port in the I/O address space.

• Block I/O instructions use either SI or DI to designate the source or

destination memory address.

• For each transfer, SI or DI are automatically either incremented or

decremented as specified by the direction bit in the flags register.
 Read and Write Cycles
• Data transfers occur as a result of bus cycles, • When pipelining is selected and the
classified as read or write cycles. Intel386 DX has a bus request pending
internally, the address and definition of the
• Two choices of address timing are next cycle is made available even before the
dynamically selectable: non-pipelined, or current bus cycle is acknowledged by
pipelined. READY#.

• After a bus idle state, the processor always • Terminating a read cycle or write cycle, like
uses non-pipelined address timing. any bus cycle, requires acknowledging the
cycle by asserting the READY# input.
• However, the NA# (Next Address) input may
be asserted to select pipelined address • Until acknowledged, the processor inserts
timing for the next bus cycle. wait states
Non-pipelined read & write
cycles
 Non-pipelined read & write
cycles
• At the end of the second bus state within the bus cycle,
READY# is sampled

• If asserted the bus cycle terminates

• Else the cycle continues another bus state (a wait state) and
READY# is sampled again at the end of that state.

• This continues indefinitely until the cycle is acknowledged by

READY# asserted.
 Unit 2:
Bus Cycles and System Architecture

System Architecture
 Systems Registers
• EFLAGS

• Memory Management Registers

• Control Registers

• Debug Registers

• Test Registers
 Systems Registers
 EFLAGS

• Memory Management Registers

• Control Registers

• Debug Registers

• Test Registers
 EFLAGS

System Flags of EFLAG REGISTER

 Systems Registers
• EFLAGS

 Memory Management Registers

• Control Registers

• Debug Registers

• Test Registers
 Memory-Management Registers
• Four registers of the 80386 locate the data structures that control segmented
memory management:
 GDTR Global Descriptor Table Register
 LDTR Local Descriptor Table Register

• These registers point to the segment descriptor tables GDT and LDT.

• IDTR Interrupt Descriptor Table Register

This register points to a table of entry points for interrupt handlers (the IDT).

• TR Task Register
This register points to the information needed by the processor to define the
current task.
 Systems Registers
• EFLAGS

• Memory Management Registers

 Control Registers

• Debug Registers

• Test Registers
Control Registers
 Systems Registers
• EFLAGS

• Memory Management Registers

• Control Registers

 Debug Registers

• Test Registers
 Debug Registers
• Six registers: to control debug
features
• Accessed by variants of the MOV
instruction
• debug registers are privileged
resources

Registers are:
 Debug Address Registers (DRO-
DR3)
 Debug Status Register (DR6)
 Debug Control Register (DR7)
 Systems Registers
• EFLAGS

• Memory Management Registers

• Control Registers

• Debug Registers

 Test Registers
 Test Registers
• Two test registers are provided for the purpose of testing.

• TR6 is the test command register, and TR7 is the test data
register.

• The test registers are privileged resources; in protected mode,

the MOV instructions that access them can only be executed at
privilege level 0
 The Test Command Register
(TR6)
• C: Command bit, two commands: ‘0’- write • V: The Valid bit for this TLB entry. The TLB uses the
entries into the TLB and ‘1’ perform TLB valid bit to identify entries that contain valid data.
lookups Entries of the TLB that have not been assigned values
have zero in the valid bit. All valid bits can be cleared
• Linear Address: by writing to CR3.
 on a TLB write command, a TLB entry is
allocated to this linear address and the rest of • D, D#: The dirty bit for/from the TLB entry
that TLB entry is set as per the values of TR7 • U, U#: The U/S bit for/from the TLB entry
& TR6 • W, W#: The R/W bit for/from the TLB entry
 on a TLB lookup command, the TLB is
interrogated as per this value and if one and Meaning of D, U, and W Bit Pairs
only one TLB entry matches, the rest of the
fields of TR6 & TR7 are set from the matching
TLB entry.
 The Test Data Register (TR7)
Holds data read from or data to be written to the TLB

• Physical Address: This is the data field of the TLB. On a write to the TLB, the TLB
entry allocated to the linear address in TR6 is set to this value. On a TLB lookup, if
HT is set, the data field (physical address) from the TLB is read out to this field. If
HT is not set, this field is undefined.

• HT: For a TLB lookup, the HT bit indicates whether the lookup was a hit (HT <- 1)
or a miss (HT <- 0). For a TLB write, HT must be set to 1.

• REP: For a TLB write, selects which of four associative blocks of the TLB is to be
written. For a TLB read, if HT is set, REP reports in which of the four associative
blocks the tag was found; if HT is not set, REP is undefined.
 Test Operations
 To write a TLB entry
• Move a doubleword to TR7 that contains the desired physical address, HT, and
REP values. HT must contain 1. REP must point to the associative block in
which to place the entry
• Move a doubleword to TR6 that contains the appropriate linear address, and
values for V, D, U, and W. Be sure C=0 for "write" command.

 To look up (read) a TLB entry

• Move a doubleword to TR6 that contains the appropriate linear address and
attributes. Be sure C = 1 for "lookup" command
• Store TR 7. If the HT bit in TR 7 indicates a hit, then the other values reveal
the TLB contents. If HT indicates a miss, then the other values in TR 7 are
indeterminate
 Systems Instructions
1. Verification of pointer parameters: 3. Multitasking:
• ARPL ── Adjust RPL • LTR ── Load Task Register
• LAR ── Load Access Rights • STR ── Store Task Register
• LSL ── Load Segment Limit
• VERR ── Verify for Reading
• VERW ── Verify for Writing 4. Coprocessing and Multiprocessing :
• CLTS ── Clear Task-Switched Flag
2. Addressing descriptor tables: • ESC ── Escape instructions
• LLDT ── Load LDT Register • WAIT ── Wait until Coprocessor not
• SLDT ── Store LDT Register Busy
• LGDT ── Load GDT Register • LOCK ── Assert Bus-Lock Signal
• SGDT ── Store GDT Register
 Systems Instructions
5. Input and Output : 7. Debugging :
• IN ── Input • MOV ── Move to and from debug
• OUT ── Output INS ── Input String registers
• OUTS ── Output String
8. TLB testing :
• MOV ── Move to and from test registers
6. Interrupt control :
• CLI ── Clear Interrupt-Enable Flag 9. System Control:
• STI ── Set Interrupt-Enable Flag • SMSW ── Set MSW
• LIDT ── Load IDT Register • LMSW ── Load MSW
• SIDT ── Store IDT Register • HLT ── Halt Processor
• MOV ── Move to and from control
registers