Innovus Hierarchical Design Flow

Hierarchical PE Team
February 2019

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 Agenda
• Introduction of Innovus Hierarchical Flow
• 18.12 Innovus Hierarchical Flow Demo
– Demo Tar Kit Contents
– Makefile
– Task List in the Makefile
– Output Data Directory Structure
o PTN Directory structure

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 Introduction of Hierarchical Flow

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 General Innovus Hierarchical Flow
• Benefit: Obtain an initial floorplan
• BlackBox/SAI/FlexModel can be
used
Top
Implementation

Hierarchical
Prototyping Design
Assembly &
Planning Block Signoff
Implementation Analysis

.
.
.
FlexModel
Need user intervention to can be used Block
get final detailed/production Implementation
floorplan

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Innovus Floorplanning Block Modeling

Performance

✓ BlackBox

✓ SoC Architecture Info (SAI)

✓ Shell Model

✓ FlexModel Boundary
flexmodel
flop
flexmodel
✓ Hierarchical FlexModel
flexmodel 1st Level
✓ Full Netlist of Logic

Accuracy

Variety of block abstractions available for design planning

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 SAI Summary
• Powerful and self-contained design planning
capability Complex functional
• Turns a high-level block diagram into a real description

netlist and SDC ready for floorplanning

• Fast runtime with crucial design information for
prototyping
SAI file
• Ideal design/floorplan-handoff mechanism set_ref_flop DFFSRX4 ;
between front-end and back-end teams set_ref_gate CLKBUFX8 ;
set_ref_memory mem1 -aspect_ratio

• Key features create_module xsw -cell XM_XBAR -

gate_count 8000 -
– Simple and easy-to-understand language syntax aspect_ratio_range {0.5 2.0}

to capture modules, ports, buses, I/O, clocks, add_macro -cell XM_PORT0

{ram_128x16A 10 rom_512x16A 20}
macros, and/or memories configuration
add_macro -cell XM_PORT1
– Adds dummy cells, boundary flops, pipeline {ram_128x16A 10 rom_512x16A 10}

registers etc, to enable timing evaluation .

.
– Supports partial netlists for mix-and-match
– Supports floorplanning constraints, reports any
constraint violation, and calculate floorplan quality
index (SAI 2.0) Innovus
• Provides a fast path from block diagram into
realistic design planning and a feasible floorplan

Allows designers to start floorplanning and timing analysis much earlier without a real netlist
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FlexModel Abstraction
^

^
Flip Flops
F
Combinatorial logic ^ ^
F F
^
Macro
F
F
^
F FlexFiller F
F
F
Interface logic F
^
F

• A FlexModel is a verilog netlist with:

– Macros
– All macros are kept (including non-interface macros)
– Interface stdcells (in Green)
– FlexFillers (in RED)
– Reserves space for removed internal R2R logic
– placement utilization will be close to interface logic
• A FlexModel netlist is usually one tenth the # instances of it’s full netlist
• Flexible shape
• Do not support nested FlexModels
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General Prototyping Flow
Prototyping
• Goal is to get an Load Initial Netlist
implementable
FlexModel/SAI
partition floorplan Generation
Initial netlist is optional
where users can use SAI
to create their initial netlist.
Preplace If initial netlist is available,
Modules/Macros it can have empty modules,
be partial, or full netlist.

Define Module and/or Macro Seeds and

their Placement Constraints

Module/Macro Placement

Manual Fine Tune floorplan

Place & Route the Design

Congestion &
Timing OK?

Optional
Cluster Modules into Groups

Define Partitions
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 Hierarchical Design Planning Flow Load in a design with
partition floorplan/macro
Original netlist placement/power
structure
FlexModel
Generation

Cell Placement

Feedthrough Insertion

Pin Assignment

Time Budgeting psPM Generation

Partition &
savePartition

replace_proto_model
Optional

Top-level
Block Implementation
Implementation

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 Top & Block Implementation Flow

Specify ILMs

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 18.12 Innovus Hierarchical Flow Demo

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 What Parts of Hierarchical Flow Demo Covers
• Can fully automate a hierarchical design closure
flow including design planning, top and block
implementation with ILMs, and assembling the
design using the Makefile.
• Support thin channel based design with
master/clones.
• What parts of the flow can be automated
– FlexModel and psPM generation.
– Feedthrough insertion.
– Pin assignment and budgets for the block designs.
– Block & Top level implementation with ILMs including
top-level CTS (bottom-up CTS).
– Assemble top and block designs.
• Do not cover the prototyping flow in this demo kit.

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 Demo Tar Kit Contents
1. Readme.txt
2. Makefile
3. DESIGN
– Initial design data base with partitioned floorplan.
4. SCRIPTS
– gen_pspm.tcl: Script for generating psPM models
– gen_flexmodel.tcl: Script for generating Flexmodels
– gen_partition.tcl: Script for running hierarchical partition flow to do feedthrough
insertion, and pin assignment.
– gen_block_db.tcl: Script for deriving time budgeting, and generating top and
partition block designs.
– pppr.tcl: Script for creating power structure.
– implement_block.tcl: Script for block implementation.
– implement_top_level.tcl: Script for top-level implementation.
– assemble_chip.tcl: Script for assembling the design
– debug_analyse.tcl: Script for debugging or analyzing the design after certain step.
– utils.tcl: Utility script.
5. DATA
– exclude_ft.txt: List of nets for excluding from feedthrough insertion.

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Required Input from Initial Design Data Base
• Locations and boundary shapes of modules that will be partitions.
• Power domain information if the design is a low power design.
• Macro placement.
• Power structure or power structure run script.
• I/O pad placement if the design is a full-chip design.
• Physical cells (well tap cells, power switches, etc…) if needed.

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 Makefile (1/5)

Section for specifying different

settings for a specific design.
User should edit this section.

Initial Floorplan Database

Partition names for a design

Section where the derived

values of the variables are
based on the variables defined
in the above section

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 Makefile (2/5) Section for defining the arguments
used to launch Innovus through
Makefile flow

Section for initializing the

Makefile flow variables

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 Makefile (3/5)
Section for defining
all tasks/targets

Running all
tasks/targets

Generating
the setup
Generating psPM models

Generating
FlexModels

Generating partitions

Generating
top & partitioned block designs

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 Makefile (4/5) Running block implementation

Running Top implementation

Running chip
assembly

Debugging the
design in Innovus

Analyzing the design in Innovus

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 Makefile (5/5) Creating demo tar file for
the current set of data

Cleaning the working

directory

Reporting the list of

tasks/targets in Makefile

Reporting the LIST variable

Dummy tasks

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 Task List in the Makefile
• Run “make task” to list all the tasks/targets that are
available
• Example: make task

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 Output Data Directory Structure
• MAKE: Directory for touch files generated at the end of each Makefile task run.
• DBS: Directory for saved design data bases created during the flow
• LOG: Directory for innovus output log files generated during Makefile run.
• proto_model: Directory for psPM models and FlexModel netlists generated by
create_pd_per_micro_model or create_proto_model
• PTN: Directory for full netlist top and partition block designs generated by
savePartition or replace_proto_model command.
• PTN_flex: Directory for top and partition blocks with FlexModel netlists.
• RPT: Directory for report files generated during Makefile run.
• timingReports: Directory for timing reports generated by timeDesign –proto.
• top.assembleDesign.rpt: Reported file generated by assembleDesign.
• Topo.txt: Output topological file generated by insertPtnFeedthrough.

NOTE:
• proto_model will not be created if Makefile is run with pspm=0 and flexmodel =0
• timingReports will not be created if Makefile is run with pspm=0
• PTN_flex dir will not be created if Makefile is run with flexmodel=0

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 PTN Directory Structure Example

PTN directory for the flow running WITHOUT PTN directory for the flow running WITH creating
creating FlexMode (make flexmode=0) FlexModel (make flexmode=1)

Note:
• *.enc.dat in both flows have full netlist. Just the name is different.
• “_proto_full” is added to design name when FlexModels is using in the flow.

22 © 2019 Cadence Design Systems, Inc. All rights reserved worldwide.

23 © 2019 Cadence Design Systems, Inc. All rights reserved worldwide.