Basic computer organization and design

By,
Er. Nabaraj Bahadur Negi

1
Contents

▪ Instruction Code, Operation Code, Stored Program Concept

▪ Registers and memory of Basic Computer, Common

Bus System for Basic Computer.

▪ Instruction Format, Instruction Set Completeness, Control Unit

of Basic Computer, Control Timing Signals

▪ Instruction Cycle of Basic computer, Determining Type of Instruction,

▪ Memory Reference Instructions, Input-Output Instructions, Program

Interrupt & Interrupt Cycle.

▪ Description and Flowchart of Basic Computer

2
 Introduction
• The organization of the computer is defined by its internal register, the timing
and control structure, and the set of instructions that it uses.

• The internal organization of a digital system is defined by the sequence of

microoperations it performs on data stored in its registers.

• Every different processor type has its own design (different registers, buses,
microoperations, machine instructions, etc.)

• Modern processor is a very complex device

• It contains

• Many registers

• Multiple arithmetic units, for both integer and floating point calculations

• The ability to pipeline several consecutive instructions to speed executi3on

• However, to understand how processors work, we will start with a
simplified processor model

• This is similar to what real processors were like ~25 years ago
• M. Morris Mano introduces a simple processor model he calls the Basic
Computer

• We will use this to introduce processor organization and the relationship

of the RTL model to the higher level computer processor

4
The basic computer

• The Basic Computer has two components, a processor and memory

• The memory has 4096 words in it

• 4096 = 212, so it takes 12 bits to select a word in memory

• Each word is 16 bits long

5
Instructions

• A computer instruction is a binary code that specifies a sequence of

microoperations for the computer.

• Instruction codes together with data are stored in memory.

• The computer reads each instruction from memory, the CPU reads the next
instruction from memory and places it in in ( Instruction Register (IR)) a
control register.

• The control then interprets the binary code of the instruction and proceeds to
execute it by issuing a sequence of microoperations.

• Every computer has its own unique instruction set.

6
Instruction Format

• A computer instruction is often divided into two parts

• An opcode ( Operation Code) is the portion of a machine language
instruction that specifies the operation for that instruction. also known as
instruction machine code, instruction code, instruction syllable.

• The operation code of an instruction is a group of bits that define such

operations as add, subtract, multiply, shift, and complement.

• An address that specifies the registers and/or locations in memory to use

for that operation

• In the Basic Computer, since the memory contains 4096 (= 212) words, we needs
12 bit to specify which memory address this instruction will use

• In the Basic Computer, bit 15 of the instruction specifies the addressing mode
(0: direct addressing, 1: indirect addressing) 7
• Since the memory words, and hence the instructions, are 16 bits long, It
consists of a 3-bit operation code, a 12-bit address, and an indirect address
mode bit designated by I. the mode bit is 0 for a direct and 1 for an indirect
address.

8
Stored Program Organization
• The simplest way to organize a computer is to have one processor register
and instruction code format with two parts.

• The first part specifies the operation to be performed and the second
specifies and address.
• The memory address tells the control where to find an operand in memory.
This operand is read from memory and used as the data to be operated on
together with the data stored in the processor register.
• Figure below depicts this type of organization. Instructions are stored in one
section of memory and a data in another.

• For a memory unit with 4096 words we need 12 bits to specify an address
since 212 = 4096.

9
• If we store each instruction code in one
16-bit memory word, we have available
four bits for the operation code
(abbreviated as opcode) to specify one
out of 16 possible operation and 12 bits
to specify the address of an operand.
• The control reads a 16-bit instruction
from the program portion of memory. It
uses the 12 bit address part of the
instruction to read and 16 bit operand
from the data portion of memory. It then Figure : Stored program organization.
executes the operation specified by the
operation code.
10
• Computer that have a single processor register usually assign to it the name
accumulator and label it AC. The operation is performed with the memory
operand and the content ofAC.
• If an operation in an instruction code does not need and operand from
memory, the rest of the bits in the instruction can be used for other purposes.

• For example, operations such as clear AC, complement AC, and increment
AC operate on data stored in the AC register.

11
Addressing Modes
• The address fieldof an Direct addressing Indirect addressing

instruction can represent 22

0 ADD 457 35 1 ADD 300

either
300 1350
• Direct address: the
457 Operand
address in memory of
1350 Operand

the data to use (the

address of the operand),
or + +
• Indirect address: the
AC AC
address in memory of
the address in memory
of the data to use Figure : Demonstration of direct and indirect address.

12
• A direct address instruction is shown in figure : b It is placed in address 22
in memory. The I bit is 0, so the instruction is recognized as a direct
address instruction. The opcode specifies an ADD instruction, and the
address part is the binary equivalent of 457. The control finds the operand
in memory at address 457 and adds it to the content ofAC.
• The instruction in address 35 shown in figure : c has a mode bit I = 1.
Therefore, it is recognized as an indirect address instruction. The address
part is the binary equivalent of 300. The control goes to address 300 to
find the address instruction needs two references to memory to fetch and
operand. The address of the operand in this case is 1350. The operand
found in address 1350 is then added to the content ofAC.
• Effective Address(EA) is the location where operand is present , or as the
target address for a branch-type instruction
13
 Basic Computer Registers and Memory
• Computer instructions are normally stored in consecutive memory locations
and are executed sequentially one at a time.
• The control reads an instruction from a specific address in memory and
executes it. It then continues by reading the next instruction in sequence and
executes it, and so on. This type of instruction sequencing needs a counter to
calculate the address of the next instruction after execution of the current

instruction is completed.
• The computer needs processor registers for manipulating data and a register
for holding a memory address.
• The memory unit has a capacity of 4096 words and each word contains 16
bits. Twelve bits of an instruction word are needed to specify the address of
an operand.
14
• A processor has many registers to hold instructions, addresses, data,etc

• The data register (DR) holds the operand read from memory. The accumulator

(AC) register is a general-purpose processing register.

• The instruction read from memory is placed in the instruction register (IR). The

temporary register (TR) is used for holding temporary data during the

processing

• The processor has a register, the Program Counter (PC) that holds the memory

address of the next instruction to be read from memory after the current

instruction is executed. Since, the memory in the Basic Computer only has

4096 locations, the PC only needs 12 bits

15
• In a direct or indirect addressing, the processor needs to keep track of what
locations in memory it is addressing: The Address Register (AR) is used for
this
• The Input Register (INPR) holds an 8 bit character gotten from an input
device

• The Output Register (OUTR) holds an 8 bit character to be send to an output

device

16
Register Number

symbol of bits Register name Function

DR 16 Data Register Holds memory operand

AR 12 Address Register Holds address for memory

AC 16 Accumulator Processor register

IR 16 Instruction Register Holds instruction code

PC 12 Program Counter Holds address of instruction

TR 16 Temporary Register Holds temporary data

INPR 8 Input Register Holds input character

OUTR 8 Output Register Holds output character

Table : List of Registers for the Basic Computer

17
 11 0
PC
Memory
11 0 4096 x 16
AR

15 0
IR
CPU
15 0 15 0
TR DR

7 0 7 0 15 0
OUTR INPR AC

Figure : Basic computer registers and memory.

18
Common Bus System
• The basic computer has eight registers, a memory unit, and a control unit.
Paths must be provided to transfer information from one register to another
and between memory and register.

• The registers in the Basic Computer are connected using a bus

• This gives a savings in circuitry over complete connections between
registers

• The outputs of seven registers and memory are connected to the common
bus.
• Three control lines, S2, S1, and S0 control which register the bus selects as its
input.

• For example, the number along the output of DR is 3. The 16-bit outputs
of DR are placed on the bus lines when S2S1S0 = 011 since this is the binary
value of decimal 3. 19
20
 S2
S1 Bus
S0
Memory unit 7
4096 x 16
Address
Write Read
AR 1

LD INR CLR
PC 2
LD INR CLR
DR 3

LD INR CLR
E
ALU AC 4

LD INR CLR

INPR
IR 5
LD
TR 6
LD INR CLR
OUTR
Clock
LD
16-bit common bus

Figure : Basic computer registers connected to a common bus.

21
Example:
One Address Instructions
Expression: X = (A+B)*(C+D)

• AC is accumulator M[] is any memory location M[T] is temporary location

LOAD A AC = M[A]

ADD B AC = AC + M[B]

STORE T M[T] = AC

LOAD C AC = M[C]

ADD D AC = AC + M[D]

MUL T AC = AC * M[T]

STORE X M[X] = AC
22
 Basic Computer Instructions

• The basic computer has three instruction code formats. Each format has 16
bits. The operation code (opcode) part of the instruction contains three bits
and the meaning of the remaining 13 bits depends on the operation code
encountered.
• A memory-reference instruction uses 12 bits to specify and address and one
bit to specify the addressing mode I. I is equal to 0 for direct address and
to 1 for indirect address.
• The register reference instructions are recognized by the operation code
111 with a 0 in the leftmost bit (bit 15) of the instruction.
• A register-reference instruction specifies an operation on or a test of the AC
register. An operand from memory is not needed; therefore, the other 12
bits are used to specify the operation or test to be executed.
23
• Similarly, an input output instruction does not need a reference to memory and
is recognized by the operation code 111 with a 1 in the leftmost bit of the
instruction. The remaining 12 bits are used to specify the type of input-output
operation or test performed.

• The type of instruction is recognized by the computer control from the

four bits in positions 12 through 15 of the instruction.
• If the three opcode bits in positions 12 through 14 are not equal to 111, the
instruction is a memory-reference type and the bit in position 15 is taken as the
addressing mode I. If the 3-bit opcode is equal to 111, control then inspects the
bit in position 15.

• If this bit is 0, the instruction is a register - reference type.

• If the bit is 1, the instruction is an input-output type.
• Note that the bit in position 15 of the instruction code is designated by the
symbol I but is not used as a mode bit when the operation code is equal to 111.
24
15 14 12 11 0

I Opcode Address

(a) Memory-Reference Instructions (Opcode = 000 ~ 110)

15 12 11 0

0 1 1 1 Register operation

(b) Register-Reference Instruction (OP-code = 111, I = 0)

15 12 11 0

1 1 1 1
I/O operation

(c) Input-Output Instructions (OP-code =111, I = 1)

Figure : Basic computer instruction formats.

25
Table : Basic Computer Instruction 26
❖ Register- reference instructions
• Register-reference instructions are recognized by the control when D7 = 1
and I = 0.

• These instructions use bits 0 through 11 of the instruction code to specify

one of 12 instructions. These 12 bits are available in IR(0-11). They
were also transferred to AR during time T2

• Execution starts with timing signal T3

r = D7 IT3 => Register Reference Instruction
Bi = IR(i) , i=0,1,2,...,11.[bit in IR(0-11) that specifies theoperation]

27
 r: SC  0 Clear SC
CLA rB11: AC  0 Clear AC
CLE rB10: E0 Clear E
CMA rB9: AC  AC’ Complement AC
CME rB8: E  E’ Complement E
CIR rB7: AC  shr AC, AC(15)  E, E AC(0) Circulate right
CIL rB6: AC  shl AC, AC(0)  E, E AC(15) Circulate left
INC rB5: AC  AC + 1 Increment AC
SPA rB4: if (AC(15) = 0) then (PC  PC+1) Skip if positive
SNA rB3: if (AC(15) = 1) then (PC  PC+1) Skip if negative
SZA rB2: if (AC = 0) then (PC  PC+1) Skip if A C zero
SZE rB1: if (E = 0) then (PC  PC+1) Skip if E zero
HLT rB0: S  0 (S is a start-stop flip-flop) Halt computer

Table: Execution of Register –Reference instructions 45

❖ Memory - Reference Instructions
• The table below lists the seven memory-reference instructions.
• The decoded output D, for i = 0,1, 2, 3, 4, 5, and 6 from the operation
decoder that belongs effective address to each instruction is included in the
table.

• The effective address of the instruction is in the address register AR and was
placed there during timing signal T2 when I = 0, or during timing signal T3
when I=1.
• The symbolic description of each instruction is specified in the table in
terms of register transfer notation. The actual execution of the instruction in
the bus system will require a sequence of microoperations.

• The execution of MR instruction starts with T4

29
 Symbol Operation Symbolic Description
Decoder

AND D0 AC  AC  M[AR]
ADD D1 AC  AC + M[AR], E  Cout
LDA D2 AC  M[AR]
STA D3 M[AR]  AC
BUN D4 PC  AR
BSA D5 M[AR]  PC, PC  AR + 1
ISZ D6 M[AR]  M[AR] + 1, if M[AR] + 1 = 0 then PC  PC+1

Table : Memory-Reference Instructions

AND to AC
• This is an instruction that performs the AND logic operation on pairs of bits in AC
and the memory word specified by the effective address. The result of the
operation is transferred to AC . The microoperations that execute this instruction
are:

D 0T4: DR  M[AR] //Read operand

D0T5: AC  AC  DR, SC  0 //AND with AC
30
ADD to AC
• This instruction adds the content of the memory word specified by the effective
address to the value of AC . The sum is transferred into AC and the output
carry Cout is transferred to the E (extended accumulator) flip-flop. The
microoperations needed to execute this instruction are

D1T4: DR  M[AR] //Read operand

D1T5: AC  AC + DR, E  Cout, SC  0 //Add to AC and store carry
in E
LDA: Load to AC
• This instruction transfers the memory word specified by the effective address to
AC . The microoperations needed to execute this instruction are
D2T4: DR  M[AR] //Read operand
D2T5: AC  DR, SC  0 //Load AC with DR
31
STA: Store AC
• This instruction stores the content of AC into the memory word specified by
the effective address. Since the output of AC is applied to the bus and the data
input of memory is connected to the bus, we can execute this instruction with
one microoperation

D3T4: M[AR]  AC, SC  0 //store data into memory location

BUN: Branch Unconditionally
• PC is incremented at time T1 to prepare it for the address of the next
instruction in the program sequence. The BUN instruction allows the
programmer to specify an instruction out of sequence and we say that the
program branches (or jumps) unconditionally. The instruction is executed with
one microoperation:

D4T4: PC  AR, SC  0 //Branch to specified address

49
BSA: Branch and Save Return Address
D5T4:M[AR]  PC,AR  AR + 1//save return address and incrementAR
D5T5: PC  AR, SC  0 //load PC with AR
• This is shown in part (a) of the figure. The BSA instruction performs the
following numerical operation:

M[135]  21, PC  135 + 1 = 136 The result of this operation is

shown in part (b) of the figure.
Memory Memory

20 0 BSA 135 20 0 BSA 135

PC = 21 Next instruction 21 Next instruction

AR = 135 135 21
136 Subroutine PC = 136 Subroutine

1 BUN 135 1 BUN 135

(a) Memory, PC, AR at time T4 (b) Memory, PC after execution

Figure : Example of BSA instruction execution.

33
ISZ: Increment and Skip-if-Zero
• This instruction increments the word specified by the effective address, and if
the incremented value is equal to 0, PC is incremented by 1.
• It is not possible to increment a word inside the memory, it is necessary to read
the word into DR, increment DR, and store the word back into memory. This
is done with the following sequence of microoperations:

D6T4: DR  M[AR] //load data into DR

D6T5: DR  DR + 1 //increment data
D6T4: M[AR]  DR, if (DR = 0) then (PC  PC + 1), SC  0

34
 Memory-reference instruction

AND ADD LDA STA

D 0T4 D 1T4 D 2T4 D 3T4

DR  M[AR] DR  M[AR] DR  M[AR] M[AR]  AC
SC  0
D0 T 5 D1 T 5 D2 T 5
AC  AC  DR AC  AC + DR AC  DR
SC  0 E  Cout SC  0
SC  0

BUN BSA ISZ

D 4T4 D 5T 4 D 6T 4
PC  AR M[AR]  PC DR  M[AR]
SC  0 AR  AR + 1

D 5T5 D 6T5

PC AR DR  DR + 1
SC  0
D 6T6
M[AR]  DR
If (DR = 0)
then (PC  PC + 1)
SC  0

Figure : Flowchart for memory-reference instructions.

35
❖ Input-output instructions
• Input and output instructions are needed for transferring information to and from
AC register, for checking the flag bits, and for controlling the interrupt facility.

• Input-output instructions have an operation code 1111 and are recognized by the
control when D7 = 1 and I = 1.The remaining bits of the instruction specify the
particular operation.
• The control functions and microoperations for the input-output instructions are
listed in Table. D7 I T3 = p (common to all input-output instructions)
IR(i) = Bi [bit in IR (6-ll) that specifies the instruction]
p: SC  0 Clear SC
INP pB11: AC(0-7)  INPR, FGI  0 Input char. to AC
OUT pB10: OUTR  AC(0-7), FGO  0 Output char. from AC
SKI pB9: if(FGI = 1) then (PC  PC + 1) Skip on input flag
SKO pB8: if(FGO = 1) then (PC  PC + 1) Skip on output flag
ION pB7: IEN  1 Interrupt enable on
IOF pB6: IEN  0 Interrupt enable off 57
 Instruction set completeness
• A computer should have a set of instructions so that the user can construct
machine language programs to evaluate any function that is known to be
computable.
• The set of instructions are said to be complete if the computer includes a
sufficient number of instructions in each of the following categories:

• Functional Instructions

• Arithmetic, logic, and shift instructions

• Example: ADD, complement AC(CMA), increment the accumulator AC

(INC), circulate the AC right (CIR), circulate the accumulator left ( CIL),
AND, clear AC(CLA)

• Transfer Instructions

• Data transfers between the main memory and the processor registers
27
• Examples: loading the AC(LDA), storing the accumulator (STA)
• Control Instructions

• Program sequencing and control

• Example: BUN, BSA, ISZ

• The branch instructions BUN, BSA, and ISZ, together with the four
skip instructions, provide capabilities for program control and
checking of status conditions.

• Input/Output Instructions

• Input and output

• Example: INP, OUT

• The input (INP) and output (OUT) instructions cause information to

be transferred between the computer and external devices.
28
 Timing and Control Unit

• The timing for all registers in the basic computer is controlled by a master
clock generator.
• The clock pulses are applied to all flip-flops and registers in the system,
including the flip-flops and registers in the control unit.
• The clock pulses do not change the state of a register unless the register is
enabled by a control signal.
• The control signals are generated in the control unit and provide control
inputs for the multiplexers in the common bus, control inputs in processor
registers, and microoperations for the accumulator.
• Control Unit: Control unit (CU) of a processor translates from machine
instructions to the control signals for the microoperations that implement
them.
• Control units are implemented in one of two ways: hardwired control and
microprogrammed control.
Hardwired control:
• The control logic is implemented with gates, flip-flops, decoders, and
other digital circuits.
• It has the advantage that it can be optimized to produce a fast mode of
operation.
• Requires changes in the wiring among the various components if the
design has to be modified or changed, i.e. modification very difficult.
• Adding new feature is difficult.
• Expensive ,high error and used in RISC processor.

29
Microprogrammed control:

• The Control information is stored in a control memory. The control memory

is programmed to initiate the required sequence of microoperations.

• In the microprogrammed control, any required changes or modifications can

be done by updating the microprogram in control memory.
• Slow ,cheap
• Used in CISC processor.
………………………………………………………………………………..
• The block Diagram of the hardware control unit is shown in figure below. It
consists of two decoders, a sequence counter, and a number of control logic
gates.
• An instruction read from memory is placed in the instruction register (IR)

30
 Instruction register (IR)
15 14 13 12 11 - 0 Other inputs

3x8
decoder
7 6 5 4 3 2 10
D0
I Combinational
D7 Control Control
logic signals

T15

T0

15 14 . . . . 2 1 0
4 x 16
decoder

4-bit Increment (INR)

sequence Clear (CLR)
counter
(SC) Clock

Figure : Hardwired Control organization. 31

• In an instruction register, instruction read from memory is sored where it is
divided into three parts the I bit, the operation code and bits 0 through 11.
The operation code in bits12 through 14 are decoded with a 3 x 8 decoder.
• The eight outputs of the decoder are designated by the binary value of the
corresponding operation code. Bit 0 through 11 are applied to the control
logic gates.
• The 4 bit sequence counter can count in binary from 0 through 15. The
outputs of the counter are decoded into 16 timing signals T0 through T15.The
sequence counter SC can be incremented or cleared synchronously.

43
Timing Signals
• Most of the time the counter is incremented to provide the sequence of timing
signals out of the 4 x 16 decoder. Once in awhile, the counter is cleared to 0,
causing the next active timing signal to be T0.
• Example, consider the case where SC is incremented to provide timing
signals T0, T1, T2, T3, and T4 in sequence. At time T4 SC is cleared to 0 if
decoder output D3 is active. This is expressed symbolically by the statement
D3T4: SC  0

44
 T0 T1 T2 T3 T4 T0
C lo c k

T0

T1

T2

T3

T4

D3

C LR
SC

Figure : Example of control timing signals

45
Figure: Functioning of Microprogrammed Control Unit
46
• The inputs (IR, ALU flags, clock) and outputs (control signals). The
control unit functions as follows:
• To execute an instruction, the sequencing logic unit issues a READ
command to the control memory.
• The word whose address is specified in the control address register is
read into the control buffer register.
• The content of the control buffer register generates control signals
and next-address information for the sequencing logic unit.
• The sequencing logic unit loads a new address into the control
address register based on the next-address information from the
control buffer register and the ALU flags.

47
 Instruction Cycle
• A program residing in the memory unit of the computer consists of a sequence of
instructions. The program is executed in the computer by going through a cycle for

each instruction.

• In Basic Computer, a machine instruction is executed in the following cycle:

1. Fetch an instruction from memory

2. Decode the instruction

3. Read the effective address from memory if the instruction has an indirect address

4. Execute the instruction

• Upon the completion of step 4, the control goes back to step 1 to fetch, decode, and

execute the next instruction. This process continues indefinitely unless a HALT

instruction is encountered.

37
Note: Every different processor has its own (different) instruction cycle
Fetch and Decode
• Initially, the program counter PC is loaded with the address of the first
instruction in the program.
• The sequence counter SC is cleared to 0, providing a decoded
timing signal T0,T1,T2, and so on.

• The microoperations for the fetch and decode phases can be specified by
the following register transfer statements.

T0: AR←PC
T1: IR←M[AR],PC←PC +1
T2: D0, ….D7←decode IR (12-14) ,AR←IR (0-11) ,I←IR(15)

49
• Since only AR is connected to the address inputs of memory, it is necessary
to transfer the address from PC to AR during the clock transition associated
with timing signal T0.
• The instruction read from memory is then placed in the instruction register
IR with the clock transition associated with timing signal T1.

• At the same time, PC is incremented by one to prepare it for the

address of the next instruction in the program.
• At time T2, the operation code in IR is decoded, the indirect bit is transferred
to flip-flop I, and the address part of the instruction is transferred to AR.
Note: The sequence counter SC incremented after each clock pulse to produce
the sequence T0, T1 andT2.

50
T1
S2

T0 S1 Bus

S0

Memory
7
unit
Address
Read

AR 1

LD

PC 2

INR

IR 5

LD
Clock

Common bus

Figure : Register transfers for the fetch phase.

51
T0 to achieve the followingconnection:
1.Place the content of PC onto the bus by making the bus selection inputs S2S1S0
equal to 010.

2. Transfer the content of the bus to AR by enabling the LD input of AR.

The next clock transition initiates the transfer from PC to AR since T0=1. In order
to implement the second statement

T1: IR <- M[AR], PC <- PC + 1

it is necessary to use timing signal T1 to provide the following connections in the
bus system.

1. Enable the read input of memory.

2. Place the content of memory onto the bus by making S2 S1S0 = 1ll.
3. Transfer the content of the bus to IR by enabling the LD input of IR
4. Increment PC by enabling the INR input of PC .
52
 Determine the type of instruction
Start
SC  

T0
AR  PC

T1
IR  M[AR], PC  PC + 1

T2
Decode Opcode in IR(12-14),
AR  IR(0-11), I  IR(15)

(Register or I/O) = 1
= 0 (Memory-reference)
D7

(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)

I I

T3 T3 T3 T3
Execute Execute AR  M[AR] Nothing
input-output register-reference
instruction instruction
SC  0 SC  0 Execute T4
memory-reference
instruction
SC  0

Figure : Flowchart for instruction cycle (initial configuration). 42

• The timing signal that is active after the decoding is T3. During time T3 the
control unit determines the type of instruction that was just read from memory.
• The flowchart of figure above presents an initial configuration for the instruction
cycle and shows how the control determines the instruction type after the
decoding.
• We determine that if D7 =1, the instruction must be a register-reference or input
output type. If D7 = 0, the operation code must be one of the other seven values
000 through 110, specifying a memory reference instruction.
• The three instruction types are subdivided into four separate paths. The selected
operation is activated with the clock transition associated with timing
signal T3. This can be symbolized as follows:
D7 I T3: AR+M[AR]

D7 I’T3: Nothing
D7 I’T3: Execute a register-reference instruction
D7 I T3 : Execute an input-output instruction
54
 Input-Output and Interrupt

• Instructions and data stored in memory must come from some input device.
Computational results must be transmitted to the user through some output
device. Commercial computers include many types of input and output
devices.

Input-Output Configuration
• The terminal sends and receives serial information. Each quantity of
information has eight bits of an alphanumeric code.
• The two registers communicate with a communication interface serially
and with the AC in parallel.
• The serial information from the keyboard is shifted into the input register
INPR . The serial information for the printer is stored in the output register

OUTR. 53
Input-output Serial Computer

communication registers and

Terminal
interface flip-flops

Receiver
Printer FGO
interface
OUTR

AC

Transmitter
Keyboard
interface INPR

FGI

Figure : Input-output configuration

56
• INPR Input register - 8 bits, OUTR Output register - 8 bits, FGI Input flag - 1 bit,
FGO Output flag - 1 bit, IENInterrupt enable - 1 bit
• Initially, the input flag FGI is cleared to 0. When a key is struck in the keyboard,
an 8-bit alphanumeric code is shifted into INPR and the input flag FGI is set to 1.
As long as the flag is set, the information in INPR cannot be changed by striking
another key. The computer checks the flag bit; if it is 1, the information from
INPR is transferred in parallel into AC and FGI is cleared to 0. Once the flag is
cleared, new information can be shifted into INPR by striking another key.
• The output register OUTR works similarly but the direction of information flow is
reversed. Initially, the output flag FGO is set to 1. The computer checks the flag
bit; if it is 1, the information from AC is transferred in parallel to OUTR and FGO
is cleared to 0. The output device accepts the coded information, prints the
corresponding character, and when the operation is completed, it sets FGO to 1.

57
Program controlled data transfer

-- CPU -- -- I/O Device --

FGI=0 FGO=1
Start Input Start Output

FGI  0
AC  Data

yes
FGI=0 yes
FGO=0
no
no
AC  INPR
OUTR  AC

FGO  0
yes
More
Character
yes More
no Character

END no

END
58
Program Interrupt
• The process of communication just described is referred to as programmed
control transfer. The computer keeps checking the flag bit, and when it finds it
set, it initiates an information transfer.
• Consider a computer that can transfer information at a maximum rate of 10
characters per second. This is equivalent to one character every 100,000µs.
Two instructions are executed when the computer checks the flag bit and
decides not to transfer the information. This means that at the maximum rate,
the computer will check the flag 50000 times between each transfer. The
computer is wasting time while checking the flag instead of doing some other
useful processing task.
• The interrupt enable flip-flop IEN can be set and cleared with two instructions.
When IEN is cleared to 0 the flags cannot interrupt the computer.
59
• When IEN is set to 1 the computer can be interrupted. These two
instructions provide the programmer with the capability of making a
decision as to whether or not to use the interrupt facility.

60
Interrupt Cycle

Instruction cycle =0 =1 Interrupt cycle

R

Fetch and decode Store return address

instructions in location 0
M[0]  PC

=0
Execute IEN
instructions
=1 Branch to location 1
PC  1
=1
FGI
=0
IEN  0
=1
FGO R 0

=0

R 1

Figure : Flowchart for interrupt cycle

61
• The interrupt cycle is a HW
implementation of a branch and
Memory Memory
save return address operation.
0 0 256
• At the beginning of the next
1 0 BUN 1120 PC = 1 0 BUN 1120
instruction cycle, the
instruction that is read from Main Main
255 Program 255 Program
memory is in address 1.
PC = 256 256
• At memory address 1, the 1120 1120

programmer must store a I/O I/O

Program Program
branch instruction that sends
the control to an interrupt
1 BUN 0 1 BUN 0
service routine

• The instruction that returns the (a) Before interrupt

(b) After interrupt cycle

control to the original program

Figure : Demonstration of the interrupt cycle
is "indirect BUN 0"
62
• Register Transfer Statements for Interrupt Cycle, The interrupt cycle is
initiated after the last execute phase if the interrupt flip-flop R is equal
to 1. This flip-flop is set to 1 if IEN = 1 and either FGI or FGO are
equal to 1. This can happen with any clock transition except when
timing signals T0, T1 or T2 are active.

T0T1T2(IEN)(FGI + FGO): R1

• The fetch and decode phases of the instruction cycle must be modified:
Replace T0, T1, T2 with R'T0, R'T1, R’T2

• The interrupt cycle :

RT0: AR  0, TR  PC

RT1: M[AR]  TR, PC  0

RT2: PC  PC + 1, IEN  0, R  0, SC  0
63
 Complete Computer Description

Design of Basic computer :

The basic computer consists of the following hardware components:
• A memory unit with 4096 words of 16 bits each
• Nine registers : AR, PC, DR, AC, IR, TR. OUTR, INPR, andSC
• Seven flip-flop: I, S, E,R, IEN. FGI, and FGO
• Two decoders: a 3 x 8 operation decoder and a 4 x 16 timing decoder
• A 16 bit common bus.
• Control logic gates.
• Adder and logic circuit connected to the input ofAC

64
Flowchart Start
SC  0, IEN  0, R  0

=0 (Instruction Cycle) =1 (Interrupt Cycle)

R
R’T0 RT0
AR  PC R’T1 AR  0, TR  PC
RT 1
IR  M[AR], PC  PC + 1 M[AR]  TR, PC  0
R’T2 RT2
AR  IR(0~11), I  IR(15) PC  PC + 1, IEN  0
D0...D7  Decode IR(12 ~ 14) R  0, SC  0

=1(Register or I/O) =0 (Memory Ref)

D7

= 1 (I/O) =0 (Register) =1(Indirect) =0 (Direct)

I I

D7IT3 D7I’T3 D7’IT3 D7’I’T3

Execute Execute AR <- M[AR] Idle
I/O RR
Instruction Instruction
Execute MR D7’T4
Instruction

Figure : Flowchart for computer operation.

65
Fetch RT0: AR  PC
RT1: IR  M[AR], PC  PC + 1
Decode RT2: D0, ..., D7  Decode IR(12 ~ 14),
AR  IR(0 ~ 11), I  IR(15)
Indirect D7IT3: AR  M[AR]
Interrupt
T0T1T2(IEN)(FGI+ FGO): R 1
RT0: AR  0, TR  PC
RT1: M[AR]  TR, PC  0
RT2: PC  PC + 1, IEN  0, R  0, SC  0
Memory-Reference
AND D0T4: DR  M[AR]
D0T5: AC  AC  DR, SC  0
ADD D1T4: DR  M[AR]
D1T5: AC  AC + DR, E  Cout, SC  0
LDA D2T4: DR  M[AR]
D2T5: AC  DR, SC  0
STA D3T4: M[AR]  AC, SC  0
BUN D4T4: PC  AR, SC  0
BSA D5T4: M[AR]  PC, AR  AR + 1
D5T5: PC  AR, SC  0
ISZ D6T4: DR  M[AR]
D6T5: DR  DR + 1
D6T6: M[AR]  DR, if(DR=0) then (PC  PC + 1),
SC  0

66
Register-Reference
D7IT3= r (Common to all register-reference instr)
IR(i) = Bi (i = 0,1,2, ..., 11)
r: SC  0
CLA rB11: AC  0
CLE rB10: E 0
CMA rB9: AC  ACE
CME rB8: E 
CIR rB7: AC  shr AC, AC(15)  E, E  AC(0)
CIL rB6: AC  shl AC, AC(0)  E, E  AC(15)
INC rB5: AC  AC + 1
SPA rB4: If(AC(15) =0) then (PC  PC + 1)
SNA rB3: If(AC(15) =1) then (PC  PC + 1)
SZA rB2: If(AC = 0) then (PC  PC + 1)
SZE rB1: If(E=0) then (PC  PC + 1)
HLT rB0: S0

Input-Output D7IT3 = p (Common to all input-output instructions)

IR(i) = Bi (i = 6,7,8,9,10,11)
p: SC  0
INP pB11: AC(0-7)  INPR, FGI  0
OUT pB10: OUTR  AC(0-7), FGO  0
SKI pB9: If(FGI=1) then (PC  PC + 1)
SKO pB8: If(FGO=1) then (PC  PC + 1)
ION pB7: IEN  1
IOF pB6: IEN  0

67
Control Logic Gates
Inputs:

• The inputs from the two decoders,

• I flip-flop
• IR-bits (0-11)
• AC bits 0 -15 to check if AC = 0 and to detect the sign bit in AC(15)
• DR bits 0 -15 to check if DR 0 and
• the values of the seven flip-flops.
Outputs:
• Signals to control the inputs of the nine registers
• Signals to control the read and write inputs of memory
• Signals to set, clear, or complement the flip-flops
• Signals for 52, 51, and 50 to select a register for the bus
• Signals to control the AC adder and logic circuit
68
Control of registers and memory
• The control inputs of the registers are LD (load), INR (increment), and CLR
(clear). Suppose that we want to derive the gate structure associated

• Address Register; AR, Scan all of the register transfer statements that change
the content of AR:
R’T0: AR  PC LD(AR)
R’T2: AR  IR(0-11) LD(AR)
D’7IT3: AR  M[AR] LD(AR)
RT0: AR  0 CLR(AR)

D5T4: AR  AR + 1 INR(AR)

LD(AR) = R'T0 + R'T2 + D'7IT3

CLR(AR) = RT0
INR(AR) = D5T4

69
• where LD(AR) is the load input of AR, CLR(AR) is the clear input of AR, and
INR(AR) is the increment input of AR . The control gate logic associated with
AR is shown in Figure.
• In a similar fashion we can derive the control gates for the other registers as well
as the logic needed to control the read and write inputs of memory. The read
operation is recognized from the symbol <-M[AR].
Read = R’T1 + D´7IT3 + (D0 + D1 + 02 + D6)T4

12 12
From bus AR To bus
D'7
I
LD Clock
T3
T2 INR
CLR
R
T0
D
T4

Figure : Control gates associated withAR. 69

Control of Flags
• The control gates for the seven flip-flops can be determined in a similar
manner
•IEN: Interrupt Enable Flag pB7:
IEN  1 (I/O Instruction)
pB6: IEN  0 (I/O Instruction)
RT2: IEN  0 (Interrupt) where, p = D7IT3 (Input/Output Instruction) and B,
and B, are bits 7 and 6 of IR.
D
7
p
I
J Q IEN
B7
T3

B6
K

R
T2

Figure : Control inputs for IEN.

70
Control of Common Bus
• The 16-bit common bus is controlled by the selection inputs S2, S1, and S0
The decimal number shown with each bus input specifies the equivalent
binary number that must be applied to the selection inputs in order.
• Each binary number is associated with a Boolean variable x1 through x7,
corresponding to the gate structure that must be active in order to select the
register or memory for the bus.

Table : Encoder for Bus Selection Circuit 71

• For example, to find the logic that makes x1 = I, we scan all register transfer
statements that have AR as a source.
D4T4: PC  AR
D5T5: PC  AR
Therefore, the Boolean function for x1 is x1 = D4T4 + D5T5
• Similarly, The data output from memory are selected for the bus when x7 = 1
and S2 S1 S0 = 1ll. The gate logic that generates x7 must also be applied to the
read input of memory. Therefore, the Boolean function for x7 is the same as the
one derived previously for the read operation.

x7 = R’T4 + D7’IT3+ (D0+ D1 + D2 + D6)T4

x1
x2 S2
x3 Multiplexer
Encoder S1 bus select
x4
x5 inputs
x6 S0
x7

Figure :Encoder for bus selectioninputs.

73
Design of Accumulator Logic

16

Adder and
16 16 16
logic AC
From DR
circuit
To bus
8
From INPR

LD INR CLR Clock

Control

gates

Figure : Circuits associated withAC.

74
D0T5: AC  AC  DR AND with DR
D1T5: AC  AC + DR Add with DR
D2T5: AC  DR Transfer from DR

pB11: AC(0-7)  INPR Transfer from INPR

rB9: AC  AC Complement
rB7 : AC  shr AC, AC(15)  E Shift right
rB6 : AC  shl AC, AC(0)  E Shift left

rB11 : AC  0 Clear

rB5 : AC  AC + 1 Increment

75
Control of AC register
• Gate structures for controlling the LD, INR, and CLR of AC show in below:

From Adder 16 16 To bus

and Logic AC
D0 AND LD Clock
T5 INR
D1 ADD CLR

D2 DR
T5
p INPR
B11
r COM
B9
SHR
B7
SHL
B6
INC
B5
CLR
B11

Figure : Gate structure for controlling the LD, INR, and CLR ofAC. 75
Adder and Logic circuit

DR(i)
AC(i)

AND

C LD
i ADD
I
FA i J Q
AC(i)
DR
C
i+1

K
INPR
From
INPR
bit(i)
COM

SHR

AC(i+1)
SHL

AC(i-1)

Figure : One stage of adder and logiccircuit.

76