International Journal of Engineering Research & Technology (IJERT)

ISSN: 2278-0181
Vol. 1 Issue 7, September - 2012

Modeling and Simulation Experiment on a Built-In Self Test for

Memory Fault Detection in SRAM
G.Narahari#1, R Venkata Sai Kiran Epi*2, Tarannum Sultana #3
#1
Assistant Professor, Department of Electronics and Communication Engineering, Sri Sai Jyothi Engineering
College, Gandipet, Hyderabad-75, (A.P.), India.

*2
P.G. Student, M.Tech. (VLSI), Department of Electronics and Communication Engineering, Sri Sai Jyothi
Engineering College, Gandipet, Hyderabad-75, (A. P.), India.
#3
Assistant Professor, Department of Electronics and Communication Engineering, Sri Sai Jyothi Engineering
College, Gandipet, Hyderabad-75, (A.P.), India.

Abstract:
The tremendous increase in memory area on 1. INTRODUCTION:
chip is in turn increasing memory density and
causing problems (i.e. faults) in Memories to detect During the fabrication of a chip, some errors
these fault‟s we require tests with high fault coverage may occur which may induce the faults in the circuit
and low cost. The faults may be of different types e.g. devices. This results in the inaccurate functioning of
static faults and dynamic faults so many has proposed the chip. Hence the chips need to be tested for the
different Algorithms to detect these kind of faults presence of any faults else it may result in the
(e.g. March algorithms) .The proposed paper deals inaccurate functioning of the chip. Since the number
with Static and Dynamic Faults, these are established of circuits on the chip is increasing exponentially,
and evaluated for static random access memories testing of such multimillion transistor chip causes a
(SRAM), by using newly developed micro-coded serious problem, and this introduces the concept of
MBIST architecture which can be used to employ Design For Testability (DFT). Design for testability
these new test algorithm which consists of 14 (DFT) refers to including test considerations into the
instructions and have much less number of operations design specifications. DFT includes using design
than the Previous Existing March algorithms (March rules that forbid the use of certain hard-to-test circuit
SS, LR e.t.c),which increases the fault coverage and forms and/or require using inherently testable forms.
reduces the time for Detecting Faults. MBISR It attempts to ensure that internal nodes are
architecture function‟s in two modes of operations. sufficiently controllable and observable. Specific
Mode 1: Normal mode and Mode 2: Test and repair DFT techniques include providing parallel test modes
mode. A Built-in-Self repair Methodology is used to to test multiple arrays simultaneously, Built-In Self-
repair the faulty locations indicated by the MBIST Test (BIST), Built-In Self-Repair (BISR).
controller. The architecture is designed by employing In recent years, embedded memories are the
Our proposed method of testing faults is simulated by fastest growing segment of SoCs. They therefore
using Xilinx 9.1ISE versions and synthesized by have major impact on the overall Defects per Million
using Xilinx 9.1 ISE version. (DPM). According to 2001 International Technology
Roadmap for Semiconductors (ITRS 2001), today‟s
Keyword - Built-In Self Test (BIST), Built-in Self SoCs are moving from logic dominant chips to
Repair (BISR), Memory Built-in Self Test (MBIST), memory dominant chips, since future application will
Reliability, Static and Dynamic faults. require lot of memory. The memory share on the chip
is expected to be about 94% in 2014.

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 International Journal of Engineering Research & Technology (IJERT)
ISSN: 2278-0181
Vol. 1 Issue 7, September - 2012

Hence cost of testing memories increases detection during test; wrapper logic to replace defect
rapidly with every new generation of memory Chips. words.
Therefore Precise fault modeling and efficient test
design is essential to reduce the cost and increase the
test time to find faults. Now-a-days embedded
memories are harder to test using ATE, and the II.MICROCODE BISR CONTROLLER
defective cells detected by the BIST circuit are
replaced by the cells of the spare SRAM. The built-in The Architecture of the Micro-code based
self diagnosis method presented for repairable built in self test and repair is shown In the Fig.1
SRAMs uses a reduced-instruction-set processor to below, It consists of the Instruction Pointer,
determine a repair solution. Instruction storage, Instruction register, AddrGen,
Reliability is one of the main considerations DataGen , R/W Control, Input multiplexer,
in any circuit design. It involves a correct and Reliability block, memory, redundant logic array,
predictable behavior of the circuit according to
output multiplexer, Fault diagnosis, SMC controller.
design specifications over a sufficiently long period
of time. To achieve this goal, the logic-circuit design
is aimed at an error-free circuit operation. Hence, Instruction Pointer:
when a fault occurs anyway, one must be able to It points to the next Micro word instruction
detect the presence of the fault and, if desired to that has to fetch from the instruction storage and
pinpoint its location. This task is accomplished by applied to memory under test. It works for every
testing the circuit. rising edge of the Clk depending on the enabling
Digital circuit manufacturers are well aware signals and Rst values. If Rst is active low InstAddr
of the need to incorporate testability features early in is reset to zero.
the design stage, or otherwise they have to incur
higher testing costs, subsequently. However, recent
studies have shown that the cost of testing and fault InstOp[5:3] R

AddrIn[3:0]
B
finding, at system and field level, is increasing

DataIn

WEna
Clk Clk Clk C

REna
Memo Output
exponentially. Thus, if a fault can be detected at chip Rst Inst MemOut Output
Rst Rst Inst ry
InstPtr Inst Mux
or board level, then significantly larger costs per fault Addr[3:0]Storage Inst[6:0] Reg WrEna
can be avoided. This is the prime reason that RdEna Ip
attention has now focused on providing testability at
Data Mux

MemEna
chip, module or even at board level.
Address[3:0]
Any test methodology usually consists of
MemIn
(i) A test strategy for generating the test-stimuli, Fault
(ii) A strategy for evaluating output responses, Clk
AddrEna
FDEna Diag
RLA
IEna

Addr
IREna

and Rst
Gen
Op
(iii) Implementation mechanisms to realize the InstOp[2]
InstEna
Over

appropriate strategies in test-generation Clk Data

and response evaluation. Rst
Data DataEna SMC
Fault modeling: This fault models should be Gen
InstOp[0] Data
established in order to deal with the new defects RLAEna RLArray
introduced by current and future technologies.
Clk
BIST: It is used at high speed testing for detect the RW
RWEna
Rst
faults in embedded memory. This is the only WrEna
InstOp[1] Control Normal
Solution that allows at-speed testing for embedded RdEna Data
memories.
BISR: Combining BIST with efficient and low cost
BISR Architecture
repair schemes in order to improve the yield.

The design proposes a word oriented Fig.1: Architecture of Micro-coded BISR.

memory Built-in Self-Repair methodology (BISR)
that targets on embedded SRAM and does not rely on Instruction Storage: It is used to store the
spare rows and columns. It uses BIST logic to instructions i.e. 14 instructions are used to find the
identify faulty words and redundancy logic to store faults in the memory. These instructions are stored in
faulty addresses and data immediately after its the instruction register. If Rst is active high, for every

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 International Journal of Engineering Research & Technology (IJERT)
ISSN: 2278-0181
Vol. 1 Issue 7, September - 2012

rising edge of the Clk if InstEna is active high one active high and WrEna is active low, the data is from
instruction will be fetched from the memory from the the memory location specified on the address signal.
location instruction address pointed by instruction
pointer. Fault Diagnosis: This module works especially
during test mode and its function is to compare the
Instruction Register: It holds the instruction pointed expected data with the original data. If any changes
at by instruction pointer. The instruction is decoded occurred it gives that location address and actual data
and given as input to the required modules. It is a 7- as input to the Redundant Logic Array.
bit register. If Rst is active low instruction register
value is reset to zero .If Rst is active high and for Redundant Logic Array: It acts as the redundant
every rising edge of the Clk, if IREna is active high memory. In this memory faulty locations address and
instruction is stored in the instruction register and data will be stored. In normal mode it compares
decoded. normal input address with the existing faulty
locations; if it matches it uses redundant logic
Address Generator: It is used to generate the memory for read and write operations. If it doesn‟t
address. If Rst is active low, address will be reset to match it will use the original memory for read and
zero, otherwise for every rising edge of the Clk, if write operations.
AddrEna is active high address will be incremented
or decremented according to the input signals. Output multiplexer: It is used to select one value
from the Redundant memory and Memory depending
Data Generator: It is used to generate the data, whether it is faulty or not.
which is given as input to the memory. If Rst is
active low, data will be reset to zero, otherwise for
III. SPECIFICATION OF MICROCODE
every rising edge of the Clk, if DataEna is active high
INSTRUCTION
data will be according to the input signals.
The proposed architecture has the ability to
RW Control: It is used to generate the RdEna and execute algorithms with unlimited number of
WrEna signals based on Micro-code bits, which are
operations per March element. Thus almost all of the
given as inputs to the memory. If Rst is active low,
then RdEna and WrEna signals will be reset to zero, recently developed March algorithms can be
otherwise for every rising edge of the Clk, if RWEna successfully implemented and applied using this
is active high then RdEna and WrEna signals will be architecture. This has been illustrated in the present
set according to the input signals. work by implementing newly developed algorithm.
The same hardware has also been used to implement
Input Multiplexer: It gives the input to memory by other new March algorithms. This requires just
considering test algorithm input and input given changing the Instruction storage unit, or the
externally during the normal mode. The control instruction codes and sequence inside the instruction
signal for this multiplexer is also given externally by storage unit. The instruction storage unit is used to
the user. If it indicates test mode then internally
store predetermined test pattern.
generated test data by BIST controller is given to the
memory as input. In case of Normal mode the The microcode is nothing but a binary code
memory responds to the external address, data and which consists of a fixed number of bits each bit
read/write signals. Multiplexer output is given as specifying a particular data or operation value. As
input to the Reliability.
there is no standard in developing a microcode
MBIST instruction, the microcode instruction fields
Reliability: It is one of the main considerations in
can be structured by the designer depending on the
any circuit design it involves the correct and
predictable behavior of the circuit according to test pattern algorithm to be used. The microcode
design specification, to achieve this goal logic circuit instruction developed in this work is coded to denote
design should be an error free circuit. Mainly it one operation in a single micro word. Thus a three
increases the life time of SRAM. operation March element is made up by five micro-
code words. The format of 7-bit microcode MBIST
Memory: It is used as a unit under test. If MemEna, instruction word is as shown in Table 1. Its fields are
WrEna both are active high and RdEna is active low, described as follows:
the data is written into the memory location specified 1) Bit #1 indicates whether it is a valid microcode
on the address signal. If MemEna, RdEna both are instruction or not, if it is equal to 1 it considers as an

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 International Journal of Engineering Research & Technology (IJERT)
ISSN: 2278-0181
Vol. 1 Issue 7, September - 2012

Developed instructions are shown in Table 3.

Fo Io Lo Description
Table 1: Format of Microcode Instruction word
1 1 1 A Single Operation Element. #1 #2 #3 #4 #5 #6 #7
Valid Fo Io Lo I/D R/W Data
0 1 1 First Operation Of a Multi-
operation Element.
Table 2: Proposed Instructions
1 0 1 In –Between Operation Of a { ↕ (W0);
Multi- Operation Element.
M0
1 1 0 Last Operation Of a Multi- ↑ (W0, R0, R0); ↑ (W1, R1, R1);
Operation Element.
M1 M2
Valid Instruction otherwise it indicates the end of test ↓ (W1, R1, R1); ↓ (W0, R0, R0);
for BIST Controller. M3 M4
2) Bits #2 is used to Specify first operation of a
multi- operation element as shown in Table 1. ↕ (R0)}
3) Bits #3 is used to Specify In-between operation of M5
a multi- operation element as shown in Table 1.
4) Bits #4 is used to Specify Last operation of a
multi- operation element as shown in Table 1. 1)The first march element M0 is a single operation
5) Bit #5 is used to Specify whether the address element, which writes zero to all memory cells in any
should be increasing or decreasing order if it is equal order, whereas the 2)second march element M1 is a
to 1 it notifies that the memory under test (MUT) is multi-operation element, which consists of Three
to be addressed in increasing order; else it is accessed operations: i) W0, ii) R0, iii) R0. MUT is addressed
in decreasing order. in increasing order as each of these three operations
6) Bit #6 is used to Specify which operation i.e. read is performed on each memory location before moving
or write operation to performed. If it is equal to 1 on to the next memory location.
indicates that the test pattern data is retrieved from
the memory under test; else, it is to be written into Table 3.Proposed Algorithm
the MUT.

#7 Data
#6 R/W
#5 I/D
#4 Lo
#2 Fo
Valid

(1/0)
#3 Io

(1/0)

(0/1)
7) Bit #7 is used to displays the data that is applied, if
#1

it is equal to 1 it signifies that a byte of 1‟s is to be

generated (written to MUT or expected to be read out
from the MUT); else byte containing all zeroes are M0: ↕ W0 1 1 1 1 1 0 0
generated. M1: ↑{ W0 1 0 1 1 1 0 0
R0 1 1 0 1 1 1 0
March Notation: R0 1 1 1 0 1 1 0
A Complete march test is delimited by the M2: ↑ {W1 1 0 1 1 1 0 1
„{..}‟ bracket pair, while a March element is R1 1 1 0 1 1 1 1
delimited by the „(..)‟ bracket pair. March elements R1 1 1 1 0 1 1 1
are separated by semicolons and the operations M3: ↓{W1 1 0 1 1 0 0 1
within a March element are separated by commas. R1 1 1 0 1 0 1 1
Note that all operations of a March element are R1 1 1 1 0 0 1 1
performed at a certain address, before proceeding to M4: ↓{ W0 1 0 1 1 0 0 0
the next address. The latter can be done in either one R0 1 1 0 1 0 1 0
of the two address orders: an increasing (↑) or a R0 1 1 1 0 0 1 0
decreasing (↓) address order. When the address order M5: ↕ R0 1 1 1 1 0 1 0
is not relevant, the symbol is used. 0 x x x x x x

The instruction word is so designed so that it can 3)Third march element M2 is a multi-operation
accommodate any existing and proposed algorithm. element, which consists of three operations: i) W1, ii)
The contents of Instruction storage unit for Newly R1, iii) R1. MUT is addressed in increasing order as

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 International Journal of Engineering Research & Technology (IJERT)
ISSN: 2278-0181
Vol. 1 Issue 7, September - 2012

each of these three operations is performed on each These are FPs that perform more than one
memory location before moving on to the next operation sequentially in order to sensitize a fault;
memory location. that is #O >1. Depending on #O, a further
4)Fourth march element M3 is a multi-operation classification can be made between 2-operation
element, which consists of Three operations: i) W1, dynamic FPs whereby #O =2, 3-operation dynamic
ii) R1, iii) R1. MUT is addressed in decreasing order FPs whereby #O =3, etc.
as each of these three operations is performed on Different types of Single cell Dynamic faults are
each memory location before moving on to the next
described below
memory location.
5) Fifth march element M4 is a multi-operation a)Dynamic Read Destructive Fault (dRDF):
element, which consists of three operations: i) W0, ii) A write followed immediately by a read
R0, iii) R0. MUT is addressed in increasing order as operation performed on a cell changes the data in the
each of these three operations is performed on each cell, and returns an incorrect value on the output.
memory location before moving on to the next <0w0r0/ 1 /1>
memory location.
6)The Sixth march element M5 is a single operation b)Dynamic Deceptive Read Destructive Fault
element, which reads zero from memory cells in any (dDRDF):
order. A write followed immediately by a read
operation performed on a cell changes the data in the
IV. FAULTS cell, and returns a correct value on the output. Here,
the write can be a transition write as well as a non-
Let #O be defined as the number of different transition write Operation.
operations performed sequentially in a S (Sentizied). <1w1r1/0/1>.

Depending on #O, FPs can be divided into static and c) Dynamic Incorrect Read Fault (dIRF):
dynamic faults: A read operation performed immediately
1)Static Faults : after a write operation on a cell returns an Incorrect
These are FPs which sensitize a fault by value on the output, while the cell remains in its
performing at the most one operation; that is #O ≤ 1.
The Static Faults described in this paper are as correct state.
follows: <0w0r0/0/1

a) Deceptive Read Destructive Fault [DRDF]: V. MBISR Operation

A Cell is said to have a DRDF if the read The address comparison is done in the
operation performed on the cell returns the expected redundancy logic, The address is compared to the
value while changing the contents of the cell to the addresses that are stored in the redundancy word
wrong value. To detect Deceptive Read Disturb Fault lines, An overflow bit identifies that there are more
each cell should be read twice successively. The first failing/fault addresses than possible repair cells, The
read sensitize the fault and the second detects it. programming of the faulty addresses is done during
R0R0 the memory BIST setup.
R1R1
The BISR mechanism employs an array of
b) Write Disturb Fault: redundant words placed in parallel with the memory.
A Cell is said to have a WDF if a non
These redundant words are used in place of faulty
transition write operation causes a transition in the
cell. To detect Write Disturb Fault each cell should words in memory. For successful interfacing with
be read after a non-transition write. already existing BIST solutions as shown in Fig. 2,
The following interface signals are taken from the
0W0R0 MBIST logic:
1W1R1.
1) A fault pulse indicating a faulty location address .
2)Dynamic Faults: 2) Fault address.
3) Expected data or correct data that is compared
with the results of Memory under test.

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 International Journal of Engineering Research & Technology (IJERT)
ISSN: 2278-0181
Vol. 1 Issue 7, September - 2012

signal. This can be easily understood by the

The repair rate and area cost of the Built In redundancy word.
Redundancy Analysis (BIRA) is mainly depends on
the redundancy organization. The redundancy
organization memory is divided into various
segments. In which spare row and columns are used
differently. Spare rows are used to replace entire row
in the memory and the columns are divided in several
spare column, groups. Here the access time and area
cost is induced due to additional multiplexers.
However different redundancy organization will lead
to different area cost and repair rate. Since most of
the memory faults are single cells, spare words are
very efficient in reducing area, more efficient and
cost saving.

The MBISR logic used here can function in two

modes.

A) Mode 1: Test & Repair Mode

In this mode the input multiplexer connects

test collar input for memory under test as generated
Fig.2 Repair module
by the BIST controller circuitry. As faulty memory
locations are detected by the fault diagnosis module
The above Fig.2 shows the repair module
of BIST Controller, the redundancy array is including the redundancy array and output
programmed. multiplexer and its interfacing with the existing BIST
module.
The fault pulse acts as an activation signal
for programming the array. The redundancy word is VI. SIMULATION RESULTS
divided into three fields. The FA (fault asserted)
indicates that a fault has been detected. The address Verilog HDL Design of Testable SRAM is done
field of a word contains the faulty address, here as the with Xilinx ISE Simulator. The design is simulated
data field is programmed to contain the correct data with same tool ISE Simulator. Simulation Results are
which is compared with the memory output. shown below. Fig.3 shows the Block diagram of Top
Module, and the Simulated Wave form of a Fault free
The IE and OE signals respectively act as SRAM is shown in Fig.4 .The top module consists of
control signals for writing into and reading from the MBIST, Memory, Fault Diagnosis module and
data field of the redundant word. An overflow signal redundancy repair array. The waveform resembles
indicates that memory can no longer be repaired if all the first operation (M0) i.e. write 0 operation which
means no data will be read out from memory and
the redundancy.
WrEna will be „1‟.Similarly for remaining operations
also we can get simulated waveform. The Faults in
B) Mode2: Normal SRAM are observed by Introducing Faults. The
Write Disturb Fault(WDF),Dynamic Incorrect Read
During the normal mode each incoming Fault(dIRF) are observed on Fig. 5 at 215ns and 270
address is compared with the address field of ns. The Dynamic Deceptive Read Destructive Fault
programmed redundant words. If there is a match, the (dDRDF) is observed in Fig.6 at 1175 ns. The
data field of the redundant word is used along with Deceptive Read Destructive Fault DRDF) and
the faulty memory location for reading and writing Dynamic Read Destructive Fault (dRDF)is shown in
data. Fig.8 at 1650ns and 1685 ns.
The output multiplexer of Redundant Array
Logic then ensures that in case of a match, the
redundant word data field is selected over the data
read out ( = 0) of the faulty location in case of a read

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 International Journal of Engineering Research & Technology (IJERT)
ISSN: 2278-0181
Vol. 1 Issue 7, September - 2012

Fig.6: Simulated waveform of Faulty SRAM

Fig.3 Block diagram of Top Module. [dDRDF].

Fig.4:Simulated waveform of Fault-free SRAM. Fig.7: Simulated waveform of Faulty SRAM [DRDF,
dRDF].

Fig.5: Simulated waveform of Faulty SRAM [WDF,

dIRF].
Fig 8 : RTL Schematic for Top Module.

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 International Journal of Engineering Research & Technology (IJERT)
ISSN: 2278-0181
Vol. 1 Issue 7, September - 2012

VII. SYNTHESIS REPORT Optimization, which in turn Reduces the time

required to detect the faults . The faults which are not
---- Source Parameters covered by previous algorithm is covered in this
Input File Name : "TopModule.prj" paper.

Input Format : mixed REFERENCES

Ignore Synthesis Constraint File : NO [1] Dr. R.K. Sharma and Aditi Sood “Modeling and
Simulation of Multi-operation Microcode-based Built-
---- Target Parameters In Self Test for Memory Fault Detection and
Output File Name : "TopModule" Repair”,2010 IEEE Annual Symposium on VlSI,DOI
10.1109/ISVLSI.2010.88.
Output Format : NGC [2] S. Hamdioui, Z. Al-Ars, A.J. van de Goor, “Testing
Static and Dynamic Faults in Random Access
Target Device : xc3s100e-5-vq100 Memories”, In Proc. of IEEE VLSI Test Symposium,
Device utilization summary: pp. 395-400, 2002.
[3] S. Hamdioui, et. al, “Importance of Dynamic
--------------------------- Faults for New SRAM Technologies”, In IEEE
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Selected Device: 3s100evq100-5
[4] S. Hamdioui, A.J. van de Goor and M. Rodgers,
Number of Slices : 212 out of 960 22% ”March SS: A Test for All Static Simple RAM
Faults”, In Proc. of IEEE International Workshop on
Number of Slice Flip Flops: 151 out of 1920 7% Memory Technology, Design, and Testing, pp. 95-100,
Bendor, France, 2002.
Number of 4 input LUTs: 397 out of 1920 20%
[5] Dongkyu Youn,Taehyung Kim, Sungju Park,”A
Number of IOs: 14 microcode-based memory BIST Implementing
modified march algorithm “,Asain Test
Number of bonded IOBs: 13 out of 66 19% Symposium,2001. Proceedings. 10th, 2001,pp.391-
395.
Number of GCLKs: 1 out of 24 4% [6] Schober,V.;paul,s.;picot,o.;”Memory built-in-self-
Timing Summary: repair using redundant Words,” International
TestConference,2001.(ITC
Speed Grade: -5 2001).proceedings,2001.pp.995-1001.
[7] R. Dekker, et al., \A Realistic Fault Model and Test
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IEEE Trans on Computers, C9(6), pp. 567-572, 1990.
138.328MHz) [8] R.D. Adams and E.S. Cooley, \Analysis of a
Minimum input arrival time before clock: 10.663ns Deceptive Read Destructive Memory Fault Model and
Recommended Test ing", In Proc. IEEE North
Maximum output required time after clock: 5.333ns Atlantic Test Workshop, 1996.
[9] M.S Abadir and J.K. Reghbati, “Functional Testing of
Semiconductor Random Access Memories ,”ACM
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VIII. CONCLUSION [10] Ch. E. Stroud, “A Designer‟s Guide to Built-In Self
Test”, Kluwer Academic Pubs., ISBN 1-4020-7050-0,
The Proposed algorithm has been generated 2002.
to detect and diagnose the Static as well as Dynamic [11] A.J van de Goor and Z. Al-Ars,”Functional Fault
faults in SRAM have been successfully implemented, Models: A Formal Notation and Taxonomy”,In Proc.
of IEEE VLSI Test Symposium,pp 281-289,2000.
Xilinx ISE 9.1i is used to verify the functionality and
[12] J-F.Li,J.C Yeh,R-F.Huang, and C.-W.Wu, “A built-in
timing Constraints of Verilog Coded BIST Module, Self Repair design for RAMs with 2-D redundancies,”
Repair redundancy and their interface, and all IEEE Trans on VLSI Systems,vol. 13, no. 6,pp 742-
modules are synthesized using Xilinx ISE 9.1i and 745, June 2005.
synthesis report is generated. The proposed algorithm
has less no of instructions then the previous one i.e.
March SS this leads to Micro Instructions

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