PREFACE

Laboratory works are worked out for provision of more deep understanding of basic
digital circuits’ operation. They cover such circuits as logic gates, code converters, decoders,
encoders, multiplexers, demultiplexres, adders, flip-flops. They are used to improve students’
investigation skills.
In process of lab works’ performance students must improve their skills of analysis and
synthesis of digital circuits, investigate modes of their operation. The important part of the
student’s work is Scheme Design System application for the schemes’ preparation. Doing the
lab works students must understand the functionality of the circuits deeply and to be sure that it
operates in full correspondence with its theoretical description. Lab works can be very helpful
to provide hands-on reinforcement of the theoretical knowledge.
Performance of lab works provides presence and development the students’ skills to
mount electronic schemes, to treat with measuring instruments and evaluate their readings
correctly. The students must obtain skills to define the function of chips and how to treat with
them. Throughout the labs, the standard integrated circuits are used to provide students’
proficiency at using the terminology and data sheets of the ICs.
To perform lab works the following power supply scheme is used:

VOLTREG Vout +5V

1 Vin Vout 3

FUSE 1A
12.6Vac F

GND
220Vac + + + +

2
25V F
25V 25V
4-IN4001diodes F  F
50 Hz 220V:12.6V 
transformer Or 1-1A bridge 25V
rectifier

It provides presence of 5V dc as output voltage at each working place. Such value of

voltage is not dangerous for the human life, so laboratory installation has full correspondence
to safety rules.

1
 PRELIMINARIES 1.

RESISTORS’ COLORED CODES.

Codes may have a view of colored strips or dots. Each color has got its own definite
meaning (see table). Strips put to one of the resistor’s terminal and are situated from left to
right. If the size of the resistor doesn’t allow us to place strips in such a way the first strip of
each resistor is made wider than others. Resistors of low accuracy (0.1%-10%) are marked
with 5 colored strips. The first three are resistance in Ohms, the forth – multiplier, the fifth –
accuracy. If resistors are marked with 4 colored strips the first two are resistance in Ohms, the
third – multiplier, the forth -accuracy. If a resistor has got 3 colored strips it means that the
first two strips are shown value of resistance in Ohms, the third one is multiplier.

Strip’s color Nominal resistance, Ohm Multiplier Tolerance, %

First strip Second strip Third strip Forth strip Fifth strip
Silver - - - 0.01 ±10
Golden - - - 0.1 ±5
Black - 0 - 1 -
Brown 1 1 1 10 ±1
Red 2 2 2 102 ±2
Orange 3 3 3 103 -
Yellow 4 4 4 104 -
Green 5 5 5 105 ±0.5
Blue 6 6 6 106 ±0.25
Violet 7 7 7 107 ±0.1
Gray 8 8 8 108 -
White 9 9 9 109 -

2
 PRELIMINARIES 2.

MEASUREMENTS with DIGITAL MULTIMETER.

Digital multimeter is a multifunctional instrument. It can measure resistance,

capacitance, DC and AC voltage, DC and AC current, short-circuit. It can help us to define
transistor’s base, emitter and collector, anode and cathode for diode.

Process of measurement.
Before the work it needs to check if the instrument ready to work. For this purpose in the mode
“measurement of resistance” it needs to connect test leads (range of measurement is 200 Ω).
The sound signal will appear to inform us about short-circuit. It means that the instrument is
suitable for measurement. This mode is used for searching short-circuit somewhere in the
electric circuit. In other positions of the pointer (not “measurement of resistance”) we can see 0
on the display without contact between the leads.

1. Measurement of resistance.

Set the FUNCTION switch to the position “measurement of resistance” and connect the test
leads across the resistor under measurement. Connect the BLACK test lead to the COM jack
and the RED test lead to the V/Ω jack. After checking define range of measurement. For
example, 200 Ω. If resistance of resistor under measurement is higher, the readings will be 1.
Change the range. If resistance under measurement is over this range, we have got its value on
the display.

2. Measurement of DC voltage.

Set the FUNCTION switch to the position “measurement of DC voltage” and connect the test
leads across the source or load under measurement. Connect the BLACK test lead to the COM
jack and the RED test lead to the V/Ω jack. After checking define range of measurement.
Range for DCV-200mV-1000V. For DCV: if polarity is wrong, indications will be with sigh “-
“. About correctness of measurement range we can judge comparing measuring parameter and
chosen range. If measuring parameter is over the lower measuring range, you should switch the
FUNCTION switch to it to increase measurement accuracy. If measuring parameter is out of
the range there is 1 on the display. In case of measurement of the same value in different
ranges the accuracy of measurement will be different. For example, if V=1.5V: range 2V- the
result is 1.505 V( three digits after decimal point); range 20V-the result is 1.51V( two digits
after decimal point); range 200V-01.5V (one digit after decimal point). To increase accuracy it
needs to choose the range, which corresponds to measuring parameter.

3. Definition of p-n-junction resistance.

In spite of the fact that it is resistance, we can’t use position of the FUNCTION switch
“measurement of resistance”. We will see 1 on the display in this case. We must use for the
switch a special position, where convention of the diode is situated. Test leads are in the
position for voltage measurement. We touch pins of the diode by test leads. If we have reverse
bias, we can see 1 on the display. If it is forward bias, we can see some definite value on the
display. It is the diode’s resistance and it is definition of the diode’s anode and cathode. RED
test lead in this case is connected with anode. If the diode is LED one, it can light.

3
 LABORATORY WORK # 1.

DIODE APPLICATIONS

Aims: investigate properties of diodes and LEDs, get skills of the scheme mounting. Compare
experimental results with theoretical foundations about diodes.

PREPARATION TO LAB WORK.

1 Learn the information about diodes and LEDs.
2 Show semiconductor diode i-v-characteristic.
3 Consider experiments’ schemes and draw them with application of Scheme Design
System. Fill in the tables theoretically.
4 Answer the questions below in written form.
4.1 What is a semiconductor diode?
4.2 What is diode’s forward/reverse bias?
4.3 What is diode’s cathode/anode?
4.4 How can you define cathode and anode for real diode?
4.5 Explain a semiconductor diode’s behavior according to its i-v-characteristic.
4.6 What is LED?
4.7 Explain how to define the value of resistance for any resistor.
4.8 Explain how to measure voltage with multimeter.

LAB WORK PERFORMANCE.

1. Demonstrate presence of your home preparation for lab work to your instructor.
2. Pass test of 10 questions.
3. Get a permission to begin the work.
4. Mount the schemes of experiment 1A on the breadboard and perform them.
5. Make a conclusion about functionality of the schemes. Compare your results with
theoretical ones.
6. Demonstrate your results to your instructor. If your results are correct you may dismount
your scheme, if no – find the mistake.
7. Repeat steps 4 to 6 for experiment 1B.
8. Be ready to answer your instructor’s questions in process of work.
9. Complete your work, dismount your schemes, clean your working place.
10. Answer your instructor’s final questions, obtain your mark.
11. Ask your instructor’s permission to leave.

4
 Experiment 1A. Realize the following circuit on a breadboard. Connecting A, and B inputs to
either GND or VCC based on the following table, fill in the blanks. Write ON or OFF for
LEDs.

Vout

Vout
Vout
LED0
R1 A A R1 A R1
Vcc
220 220 220
LED0 LED0

INPUT OUTPUT INPUT OUTPUT INPUT OUTPUT

A LED 0 Vout A LED 0 Vout A LED 0 Vout
ON/OFF (V) ON/OFF (V) ON/OFF (V)
1 5V 1 5V 1 5V
2 0V 2 0V 2 0V

Experiment 1B. Do the similar things for the following circuits.

A D0 A D0
R1
VCC
100
1N4001 Vo ut R0 1N4001
220
B D1 LED 0 B D1 Vo ut R0
220
1N4001 1N4001 LED 0

INPUTS OUTPUTS INPUTS OUTPUTS

A B LED0 Vout (V) A B LED0 Vout (V)
1 0V 0V 1 0V 0V
2 0V 5V 2 0V 5V
3 5V 0V 3 5V 0V
4 5V 5V 4 5V 5V

5
 TEST QUESTIONS

1. Voltages V1, V3, V4 in the scheme below equal to ________ respectively.

+5V
+5V
+5V
V 2 D 3
D D 2 kW
1 V 3 V 4
V 1

D 4

5kW kW kW D 5

kW

A. 4.3 V, 0, 0 B. 0, 4.3V, 0 C. 4.3 V, 4.3 V, 0 D. 0, 0, 0 E. 4.3 V, 0, 4.3 V

2. How many states has the switch got?

A. 1 B. 2 C. 3 D. 4 E. 5

3. What can you say about state of diodes 1, 2, 3 in the picture?

+5V
+5V
+5V
V 2 D 3
D D 2 kW
1 V 3 V 4
V 1

D 4

5kW kW kW D 5

kW

A. reverse, forward, reverse B. reverse, forward, forward

C. forward, reverse, forward D. Reverse, reverse, forward
E. forward, forward, reverse

4. The second strip to obtain resistance 560 Ω must be

A. blue B. Green C. Brown D. Yellow E. red

5. Value of resistance is 9.6 kΩ. It means that the first three strips on the resistance case (in
whole the case has got 4 strips) are:
A. white, blue, red B. gray, brown, black C. Black, brown, green
D. brown, black, brown E. brown, black, red

6. Analyze the information. Fill in the gaps.

Anode voltage is +5V, cathode V is +3V. The diode is ______. Anode voltage is -5V, cathode
V is -3V. The diode is ______.
A. ON, ON B. OFF,OFF C. ON, OFF D. OFF, ON E. all answers are wrong

7. Forward bias means that for diode

A. anode voltage is more positive than its cathode one
B. anode voltage is equal to or is more negative than its cathode one
C. anode voltage is positive D. anode voltage is negative E. all answers are wrong

6
8. For the circuit below if V A=5V VB=0V D0 is _______, D1 is ______, and LED0
is________.
A. open, closed, ON B. open, open, ON C. closed, closed, OFF
D. closed, open, ON E. open, open, OFF

A D0

1N4001 Vo ut R0
220
B D1 LED 0

1N4001

9. Calculate current through typical red LED if resistor for its limitation is equal to 330 Ω.
Anode voltage of LED is 5V.
A. 10 mA B. 15 mA C. 20 mA D. 25 mA E. 30 mA

10. For the circuit below define current through diode if R=2kΩ

A. 5 mA
V out
B. 4.5 mA
C. 4.3 mA
5V R D. 2.15 mA
E. 0.86 mA

7
 LABORATORY WORK # 2.

REALIZATION OF LOGIC GATES WITH TRANSISTORS.

Aims: define what logic gates are realized schematically, learn the gates’ properties. Compare
experimental results with theoretical foundations about logic gates.
Improve skills of the schemes’ preparation.

PREPARATION TO LAB WORK.

1 Learn the information about transistors.
2 Show bipolar transistor’s characteristics.
3 Consider experiments’ schemes and draw them with application of Scheme Design
System. Analyze what gates are realized on the schemes’ basis. Fill in the tables
theoretically.
4 Answer the questions below in written form.
4.1 What is a bipolar transistor?
4.2 What are names of a bipolar transistor’s electrodes?
4.3 How to define situation of a bipolar transistor’s electrodes?
4.4 What are conditions to have a bipolar transistor ON(OFF)?
4.5 What types of bipolar transistors do you know?
4.6 What are typical silicon transistor’s parameters?
4.7 What modes of a bipolar transistor’s operation do you know?

LAB WORK PERFORMANCE.

1. Demonstrate presence of your home preparation for lab work to your instructor.
2. Pass test of 10 questions.
3. Get a permission to begin the work.
4. Mount the first scheme of experiment 2 on the breadboard and perform it.
5. Make a conclusion about functionality of the scheme. Compare your results with
theoretical ones.
6. Demonstrate your results to your instructor. If your results are correct you may
dismount your scheme, if no – find the mistake.
7. Repeat steps 4 to 6 for the second and third schemes of experiment 2.
8. Be ready to answer your instructor’s questions in process of work.
9. Complete your work, dismount your schemes, clean your working place.
10. Answer your instructor’s final questions, obtain your mark.
11. Ask your instructor’s permission to leave.

8
Experiment 2. Realize the following circuit on a breadboard. Connecting A, and B inputs to
either GND or VCC based on the following table, fill in the blanks. Write ON or OFF for
LEDs.

VCC VCC
VCC

A R0 1K T0 BC239 A R0 1K T0 BC239
R5
R3 1K R3 1K 100

B T1 BC239 B T1 BC239 Vo ut
R1 10K V ou t R1 10K R4 T2 BC239
1K
R2 R6
220 220

R2
1K

LED0
LED0

INPUTS OUTPUTS INPUTS OUTPUTS

A B LED Vout A B LED Vout
1 0V 0V 1 0V 0V
2 0V 5V 2 0V 5V
3 5V 0V 3 5V 0V
4 5V 5V 4 5V 5V

This is …………… Gate This is a ……………. Gate

VCC

A R0 T0 BC239
1K

B R1 T1 BC239
1K
Vou t
R2
220

LED0

INPUTS OUTPUTS INPUTS OUTPUTS

A B LED Vout A B LED Vout
1 0V 0V 1 0V 0V
2 0V 5V 2 0V 5V
3 5V 0V 3 5V 0V
4 5V 5V 4 5V 5V

This is …………… Gate This is a ……………. Gate

9
 TEST QUESTIONS

1.For the circuit below if V A=0 VB=0 transistor T0 is____, transistor T1 is_____, LED0 is____.
A. ON, ON, ON B. ON, ON, OFF C. OFF,ON, OFF
D. OFF, OFF, ON E. OFF, OFF, OFF

VCC

A R0 T0 BC239
1K

B R1 T1 BC239
1K
Vou t
R2
220

LED0

2.Fill in the gaps in the text: to turn on an NPN transistor, a ______ voltage is applied to the
______. When transistor is turned on, its collector-to-emitter becomes a _____.
A. negative, base, short B. positive, base, short C. negative, emitter, open
D. positive, emitter, short E. positive, emitter, open

3. How many states has the switch got?

A. 1 B. 2 C. 3 D. 4 E. 5

4. Bipolar transistor has:

A. 1 p-n-junction B. 2 p-n-junctions C. 3 p-n-junctions
D.1, or 2, or 3 p-n-junctions E. any number of p-n-junctions

5. The second strip to obtain resistance 120 Ω must be

A. white B. Green C. Brown D. Yellow E. red

6. What statement is wrong?

A. (X+Y)(X+Z)=X+YZ B. X(Y+Z)=XY+XZ C. X+XY=X
D. (XY)´=(X+Y)´ E. X(X+Y)=X

7. The truth table for XOR gate is:

A B C D E
X y F x y F x y F X y F x y F
0 0 0 0 0 0 0 0 1 0 0 1 0 0 0
0 1 0 0 1 1 0 1 1 0 1 0 0 1 1
1 0 0 1 0 1 1 0 1 1 0 0 1 0 1
1 1 1 1 1 1 1 1 0 1 1 0 1 1 0

10
8. For the circuit below if V A=0 VB=5V transistor T0 is____, transistor T1 is_____, LED0
is____.
A. ON, ON, ON B. ON, ON, OFF C. OFF,ON, OFF
D. OFF, OFF, ON E. OFF, OFF, OFF
VCC

A R0 1K T0 BC239

R3 1K

B T1 BC239

R1 10K V ou t

R2
220

LED0

9. The truth table for NAND gate is:

A B C D E
X y F x y F X y F X y F x y F
0 0 0 0 0 0 0 0 1 0 0 1 0 0 0
0 1 0 0 1 1 0 1 1 0 1 0 0 1 1
1 0 0 1 0 1 1 0 1 1 0 0 1 0 1
1 1 1 1 1 1 1 1 0 1 1 0 1 1 0

10. For the circuit below if VA=5V VB=0 transistor T0 is____, transistor T1 is_____,
transistorT2 is____.
A. ON, ON, ON B. ON, OFF, OFF C. OFF,ON, OFF
D. OFF, OFF, ON E. OFF, OFF, OFF
VCC
VCC

A R0 1K T0 BC239
R5
R3 1K 100

B T1 BC239 Vo ut
R1 10K R4 T2 BC239
1K
R6
220

R2
1K
LED0

11
 LABORATORY WORK # 3.

LOGIC GATES.

Aims: define what logic gates are realized schematically, learn the gates’ properties. Compare
experimental results with theoretical foundations about logic gates.

PREPARATION TO LAB WORK.

1 Learn the information about logic gates and integrated circuits (IC).
2 Show truth table of AND, OR, NOT, NAND, NOR, XOR, XNOR, buffer gates.
3 Consider experiments’ schemes and draw them with application of Scheme Design
System. Analyze what gates are realized on the schemes’ basis.
4 Design XNOR gate for the experiment 3D on the basis of schemes in experiment 3A, 3B,
3C. Draw the XNOR scheme with application of Scheme Design System.
5 Answer the questions below in written form.
5.1 What logical operations do you know?
5.2 Show the algebraic expression of logical operation NOT (AND, OR and so on).
5.3 How many magnitudes has the logic value got?
5.4 What is integrated circuit (IC)?
5.5 What types of IC’s do you know?
5.6 What scales of IC’s integration do you know?
5.7 How many functions of 2 variables do you know?
5.8 Show the difference between complement and dual functions.
5.9 What function is called odd (even)?
5.10 What IC digital logic families do you know?
5.11 What is positive (negative) logic?
5.12 What are typical voltage levels for TTL, ECL, CMOS families?
5.13 What is fan-out, power dissipation, propagation delay, noise margin
5.14 Compare different IC digital logic families from point of view their typical
special characteristics.

LAB WORK PERFORMANCE.

1. Demonstrate presence of your home preparation for lab work to your instructor.
2. Pass test of 10 questions.
3. Get a permission to begin the work.
4. Mount the scheme of experiment 3A on the breadboard and perform it.
5. Make a conclusion about functionality of the scheme. Compare your results with
theoretical ones.
6. Demonstrate your results to your instructor. If your results are correct you may dismount
your scheme, if no – find the mistake.
7. Repeat steps 4 to 6 for experiment 3B, 3C, 3D.
8. Be ready to answer your instructor’s questions in process of work.
9. Complete your work, dismount your schemes, clean your working place.
10. Answer your instructor’s final questions, obtain your mark.
11. Ask your instructor’s permission to leave.

12
Experiment 3A. Realize the following circuit on a breadboard. Do not forget to connect 7 th pin
of 7404 chip to GND (0V) and 14th pin to VCC (+5V). Connecting X-input to either GND or
VCC based on the following table, fill in the blanks. Write ON or OFF for LEDs.
U?A
7404
1 2 F

X R1 R3
330 330

LED1 LED2

INPUT OUTPUT
X LED1 LED2
1 0V
2 5V
As a result, this truth table belongs to a …………………………….

Experiment 3B. Realize the following circuit on a breadboard. Connecting X, and Y inputs to
either GND or VCC based on the following table, fill in the blanks. Write ON or OFF for
LEDs, and a voltage value for F.

X R1
330

U1A
1
LED 3 F
L1 2

Y 7400

R2 R3
330 330

LED LED
L2 L3

INPUTS OUTPUTS
X Y LED1 LED2 LED3 F (V)
1 0V 0V
2 0V 5V
3 5V 0V
4 5V 5V

As a result this truth table belongs to a ……………………………………………….

13
Experiment 3C. Realize the following circuit on a breadboard. Do not forget to connect 7 th
pin of 7400 chip to GND (0V) and 14th pin to VCC (+5V). Connecting X-input to either GND
or VCC based on the following table, fill in the blanks. Write ON or OFF for LEDs.

U1B
X 4
6
R1 5
330
U1A 7400 U1D
1 12
3 11 F
2 13
LED R3
7400 U1C 7400
L1 9 330
8
Y 10

7400 L3
R2
330 LED

LED
L2

INPUTS OUTPUTS
X Y LED1 LED2 LED3 F (V)
1 0V 0V
2 0V 5V
3 5V 0V
4 5V 5V

As a result this truth table belongs to a ………………………………….

Experiment 3D. Design XNOR gate on the same scheme basis. Draw the XNOR scheme
with application of Scheme Design System.

INPUTS OUTPUTS
X Y LED1 LED2 LED3 F (V)
1 0V 0V
2 0V 5V
3 5V 0V
4 5V 5V

As a result this truth table belongs to a ………………………………….

14
 TEST QUESTIONS

1. Function # _____ corresponds to function AND of 3 variables.

X Y Z F1 F2 F3 F4 F5
0 0 0 0 0 0 0 0
0 0 1 0 0 1 1 0
0 1 0 0 0 1 1 0
0 1 1 1 1 1 1 0
1 0 0 0 1 1 1 0
1 0 1 1 1 1 0 0
1 1 0 1 1 1 0 0
1 1 1 1 1 1 1 1
A. 1 B. 2 C. 3 D. 4 E. 5

2. The truth table for XOR gate is:

A B C D E
X Y F X Y F X Y F X Y F X Y F
0 0 0 0 0 0 0 0 1 0 0 1 0 0 0
0 1 0 0 1 1 0 1 1 0 1 0 0 1 1
1 0 0 1 0 1 1 0 1 1 0 0 1 0 1
1 1 1 1 1 1 1 1 0 1 1 0 1 1 0

3.A small-scale integration (SSI) device contains __________ gates in a single chip.
A. thousands of B. From10 to 1000 C. More than 100
D. From 10 to 100 E. less than 10

4. (XY)´ is algebraic expression of ________ function.

A. XOR B. XNOR C. NOR D. NAND E. AND

5. NOR is dual to A. XOR B. XNOR C. NOR D. NAND E. AND

6. OR is complement to A. XOR B. XNOR C. NOR D. NAND E. AND

7. A buffer produces the _____ function.

A. complement B.dual C. transfer D. inhibition E. implication

8. Inverter can have _____ input (s). A. 1 B.2 C. 3 D.4 E. A lot of

9. For the gate below function F is correspondent to column ____.

A.1 B.2 C.3 D.4 E5
X Y 1 2 3 4 5
1 1 0 0 1 1 1 F
1 0 1 0 1 0 0
0 1 1 0 1 0 0
0 0 1 1 0 0 1

10. Duality principle states that every algebraic expression

A. remains valid if the operators and identity elements are changed.
B. remains valid if the operators and identity elements are interchanged.
C. deducible from the postulates of Boolean algebra remains valid if the operators and identity elements are
changed.
D. deducible from the postulates of Boolean algebra remains valid if the operators and identity elements are
interchanged.
E. deducible from the postulates of Boolean algebra remains valid if the operators are changed.

15
 LABORATORY WORK # 4.

SEVEN-SEGMENT DISPLAYS

Aims: investigate 1-digit and 2-digit seven-segment displays operation, understand the process
of code conversion for the device, and make a comparison between 1 and 2 digit seven-
segment displays.

PREPARATION TO LAB WORK.

1 Learn the information about seven-segment displays
2 Consider scheme of experiment 4A and draw it using Scheme Design System.
3 Answer the questions below in written form.
3.1 What is an order to count pins of a chip?
3.2 What is a code conversion?
3.3 What is a BCD-to-seven-segment decoder?
3.4 What is the way to obtain #6 (or 2, or3 and so on) on the display?
3.5 Show the situation of segments from a to g on the display.
3.6 If we apply +5V to segments b and c we can see #____ on the display.
3.7 How many pins has the chip of seven-segment display got?
3.8 What shall we do with pins #3, 5, 8?
3.9 Show seven-segment display internal structure with LEDs.
3.10 What is another name of a seven-segment display?
3.11 What is the difference between conversion and coding of a decimal number?
3.12 Show the differences between 1- and 2-digit seven-segment display.

LAB WORK PERFORMANCE.

1. Demonstrate presence of your home preparation for lab work to your instructor.
2. Pass test of 10 questions.
3. Get a permission to begin the work.
4. Mount the scheme of experiment 4A on the breadboard and perform it.
5. Make a conclusion about functionality of the scheme. Compare your results with
theoretical ones.
6. Demonstrate your results to your instructor. If your results are correct you may
dismount your scheme, if no – find the mistake.
7. Mount the scheme of experiment 4B on the bread board. Use 2-digit seven-segment
display of common cathode type.
8. Find which pin corresponds to appropriate segment, and fill in the table.
9. Repeat steps 7 and 8 for experiment 4C. Use another type of seven-segment display.
10. Be ready to answer your instructor’s questions in process of work.
11. Complete your work, dismount your scheme, and clean your working place.
12. Answer your instructor’s final questions, obtain your mark.
13. Ask your instructor’s permission to leave.

16
 Experiment 4A. Realize the following circuit on a breadboard. Connecting Va, Vb, Vc, Vd,
Ve, Vf and Vg inputs to either GND or VCC based on the following table, fill in the blanks.

Va Vb Vc Vd Ve Vf Vg Display
1 5V 5V 5V 5V 5V 5V 0V
2 0V 5V 5V 0V 0V 0V 0V
3 5V 5V 0V 5V 5V 0V 5V
4 5V 5V 5V 5V 0V 0V 5V
5 0V 5V 5V 0V 0V 5V 5V
6 5V 0V 5V 5V 0V 5V 5V
7 0V 0V 5V 5V 5V 5V 5V
8 5V 5V 5V 0V 0V 0V 0V
9 5V 5V 5V 5V 5V 5V 5V
10 5V 5V 5V 0V 0V 5V 5V
11 5V 0V 5V 5V 0V 5V 5V
12 0V 5V 5V 5V 5V 0V 5V
13 0V 5V 5V 5V 5V 0V 5V

Experiment 4B. Use 2-digit seven- segment display. Situate it on the breadboard. Pins 13 and
14 are connected to GND. Define which pin corresponds to which segment, show them in the
picture. Fill in the table, showing the voltage for the numbers obtained. For example, V 1 is a
voltage, applied to pin 1 and so on. Use resistors of 330(220)Ω to avoid the LED’s burning.

# V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V15 V16 V17 V18 #

1 15
2 24
3 37
4 60
5 89
6 41
7 52
8 73
9 96
10 08

17
 Experiment 4C. Use another type of 2-digit seven segment display (common anode). Make
appropriate connections and fill in the table.

# V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V15 V16 V17 V18 #

1 15
2 24
3 37
4 60
5 89
6 41
7 52
8 73
9 96
10 08

18
 TEST QUESTIONS

1. What fragment corresponds to definition of the Gray code?

A B C D E
x y F x y F x Y F x y F x y F
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 1 1 0 0 0 0 1 1 0 0 1 0 0
0 1 0 1 1 0 0 1 1 1 0 1 1 1 1
0 1 1 1 1 1 0 1 0 1 1 0 1 1 0
1 0 0 0 1 1 1 0 0 1 1 1 1 0 1

2. A code converter is a circuit that

A. makes the several systems compatible
B. makes the two systems compatible
C. makes the two systems compatible even though each uses a different binary code
D. makes the two systems compatible even though each uses a different codes
E. makes the several systems compatible even though each uses a different binary codes

3. Decimal 3 will be represented in 8,4,-2,-1 code as

A. 0111 B. 0101 C. 0110 D. 0100 E. 1000

4. What factor is, as a rule, more important for the circuit?

A. number of gates B. Types of gates C. Propagation delay
D. number of levels of implementation D. None of above mentioned

5. In biquinary code decimal 2 is

A. 0100100 B. 0010010 C. 0100101 D. 1000010 E. 1000001

6. Binary conversion of decimal 12 is _______, the coding it in BCD is _____.

A. 1101, 00010011 B. 1101, 1100 C. 1101, 1111 D. 1100, 01101100
E. 1100, 00010010

7. In the table below you can see a message. Show the parity bit for rows 1 to 3 if odd parity
system is adopted.
A. 0,0,1 B.1,0,1 C.1,1,0 D.0,1,0 E. 0,1,1

Message Parity bit

0001
1110
0110

8. Decimal 1 will be represented in Excess-3 code as

A. 0111 B. 0101 C. 0110 D. 0100 E. 1110

9. Binary combination of decimal 5 in Excess –3 code means decimal ______ for 8,4,-2,-1
code.
A. 2 B. 3 C. 4 D. 6 E. 8

10. Decimal 9 will be represented in 2,4,2,1 code as

A. 0111 B. 0101 C. 0110 D. 1100 E. 1111

19
 LABORATORY WORK # 5.

FOUR-BIT BINARY PARALLEL ADDER.

Aims: investigate 4-bit binary parallel adder operation; make an addition according to the task.
Compare the results of the addition with ones, made by theoretical way.

PREPARATION TO LAB WORK.

1 Learn the information about adders.
2 Draw look-ahead carry generator scheme with application of Scheme Design System.
3 Consider experiment’s scheme and analyze its operation. Draw it using Scheme Design
System.
4 Draw the scheme of 8-bit binary parallel adder on the basis of 7483 chip with application
of Scheme Design System. It will be the scheme for experiment 5B.
5 Answer the questions below in written form.
5.1 What is a half-(full-) adder?
5.2 Show the truth table for half-(full-) adder.
5.3 Show the algebraic expressions for sum and carry for half-(full-) adder.
5.4 What is a binary parallel adder?
5.5 What is a serial adder?
5.6 How many adders are needed to construct 7-bit parallel adder?
5.7 How many bits have typical full-adders ICs got?
5.8 How to connect IC’s full-adders if one package is not enough?
5.9 What is a look-ahead carry generator?
5.10 What functions can look-ahead carry generator produce?

LAB WORK PERFORMANCE.

1. Demonstrate presence of your home preparation for lab work to your instructor.
2. Pass test of 10 questions.
3. Get a permission to begin the work.
4. Mount the scheme of experiment 5A on the breadboard and perform it.
5. Make a conclusion about functionality of the scheme. Compare your results with
theoretical ones.
6. Demonstrate your results to your instructor. If your results are correct you may dismount
your scheme, if no – find the mistake.
7. Repeat steps 4 to 6 for experiment 5B.
8. Be ready to answer your instructor’s questions in process of work.
9. Complete your work, dismount your schemes, clean your working place.
10. Answer your instructor’s final questions, obtain your mark.
11. Ask your instructor’s permission to leave.

20
Experiment 5A. Realize the following circuit on a breadboard. Connecting A and B inputs to
either GND (for 0) or VCC (for 1) based on the following table, fill in the blanks. Connect pin
5 of 7483 to VCC and pin 12 to GND. Write ON or OFF for LEDs.

L10

L L 330
4 3 L2 L1
L11
330
330
330 330
A 10 9 L12
1
A3 A2 8
A1 S1
6 330
A2 S2
3 2
A 1
A3 S3
15
4 A4 S4 330
L13
11
B1
B 7 330
1 B2 4
B2
330 B3 16
B3 L14
330
B 4
B4

330 13 14
C0 C4
330 330
7483
330

L5 L6 L7 L8 L9

Numbers for addition inputs outputs

A1 A2 A3 A4 B1 B2 B3 B4 L1 L2 L3 L4 L5 L6 L7 L8 L9 L 10 L 11 L 12 L 13 L 14
1 1 0 0 1 1 0 1
0 0 0 1 1 1 1 1
1 0 0 1 0 1 1 0

Experiment 5B. Do the same things for your own circuit for 8-bit addition. Add numbers
00101100 and 11000100, 11101100 and 11001100.

21
 TEST QUESTIONS

1. Name the inputs_____ and outputs________ of a half-adder.

A. A0,B0, Cin, ∑0 B. A0,B0, Cout, ∑0 C. Cin, ∑0 A0,B0 D. Cout, ∑0 A0,B0,
E. ∑0 A0,B0

2. The first strip to obtain resistance 220 Ω must be

A. white B. Green C. Brown D. Yellow E. red

3. What statement is wrong?

A. (X+Y)(X+Z)=X+YZ B. X(Y+Z)=XY+XZ C. X+XY=X
D. (X+Y)´=X´Y´ E. X(X+Y)=X+Y

4. A Boolean function is an expression, formed with

A. binary numbers
B. binary variables
C. binary variables and operators
D. binary variables, the two binary operators OR and AND, the unary operator NOT,
parentheses, and equal sign.
E. binary variables, the binary operators OR, AND, and NOT, parentheses, and equal sign.

5. 7483 is
A. 3*8 decoder B. 4-bit magnitude comparator C. Code converter
D. 4-bit full adder E. priority encoder

6. What factor is, as a rule, more important for the circuit?

A. number of gates B. Types of gates C. Propagation delay
D. number of levels of implementation D. None of above mentioned

7. Serial binary adder consists of

A. n full adders, connected in cascade, where n-number of digits for addition
B. n half adders, connected in cascade, where n-number of digits for addition
C. n full adders and a storage device, where n-number of digits for addition
D. n half adders and a storage device, where n-number of digits for addition
E. one full adder and a storage device

8. A half-subtractor is a ________ circuit, that subtracts ________ bits and produces their
difference.
A.sequential; three
B. sequential; two
C. combinational; two
D. combinational; three
E. sequential or combinational; three

9. Make addition of binary numbers: 1001 and 1010. Result is

A. 10011 B.1001 C. 1100 D. 11001 E. 10101

10. To construct 6-bit parallel adder we must use cascade of such full-adders IC s as
A. two 2-bit and one 1-bit B. one 2-bit and one 3-bit C.one 4-bit and one 1-bit
D. five 1-bit E. none of above mentioned, because 5-bit parallel adder IC exists itself

22
 LABORATORY WORK # 6.
BCD ADDER.
Aims: investigate BCD adder operation, make an addition according to the task. Compare the
results of the addition with ones, made by theoretical way.

PREPARATION TO LAB WORK.

1. Learn the information about BCD adder and combinational logic.
2. Draw block diagram of a BCD adder with application of Scheme Design System and
compare this scheme with a scheme of experiment #6.
3. Answer the questions below in written form.
3.1. What is a decimal adder?
3.2. What is a BCD adder?
3.3. For what purpose do 3 external gates exist in the scheme of BCD adder?

LAB WORK PERFORMANCE.

1. Demonstrate presence of your home preparation for lab work to your instructor.
2. Pass test of 10 questions.
3. Get a permission to begin the work.
4. Mount the scheme of experiment 6 on the breadboard and perform it.
5. Make a conclusion about functionality of the scheme. Compare your results with
theoretical ones.
6. Demonstrate your results to your instructor. If your results are correct you may
dismount your scheme, if no – find the mistake.
7. Be ready to answer your instructor’s questions in process of work.
8. Complete your work, dismount your schemes, clean your working place.
9. Answer your instructor’s final questions, obtain your mark.
10. Ask your instructor’s permission to leave.

23
Experiment 6. Realize the circuit on a breadboard. For 2-input AND take 7408, pins 1,2-
inputs, pin 3 output. For 2-input OR take 7432, pins 1,2,4,5-inputs, pins 3,6-outputs. Fill in the
tables. Connect pin 5 of 7483 to VCC and pin 12 – to GND. Show ONs or OFFs for LEDs.
Tasks for addition:

options Inputs of basic adder Outputs of basic adder

L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14
5+9
7+8
4+3

options Inputs of correction adder Outputs of the circuit

L15 L16 L17 L18 L19 L20 L21 L22 L23
5+9
7+8
4+3

Conclusion:

24
 TEST QUESTIONS

1. The content of register when we enter 249 in BCD is:

0A 0 1 0 0 1 0 0 1 0 0 1
B 0 0 1 0 0 1 0 0 1 0 0 0
C 0 1 0 0 0 0 1 0 1 0 0 1
D 0 0 1 1 0 1 0 0 1 0 0 0
E 0 0 1 0 0 0 1 1 1 0 0 1

2. A small-scale integration (SSI) device contains __________ gates in a single chip.

A. thousands of B. From10 to 1000 C. More than 100 D. From 10 to 100 E. less than 10

3. Number of functions of n variables can be determined according to the formula

n n
A. 2 2 B. 22n C.2n D. 2 3 E. 23n

4. A half-subtractor is a ________ circuit, that subtracts ________ bits and produces their
difference.
A.sequential; three B. sequential; two C. combinational; two
D. combinational; three E. sequential or combinational; three

5. What is the result of the following BCD addition?

0011 0010 1001 0101
+ 0111 0000 0110

A. 0011 1001 1001 1011 B. 0100 0000 0000 0001 C. 0011 1001 1001 0001
D. 0100 0000 0000 1011 E. 0011 0000 0000 1011

6. Add in octal: 541+326

A. 967 B. 867 C. 1067 D. 947 E. 948

7. Full adder forms ____________, but half-adder forms _________________________.

A. the sum of two bits, …. the sum of two bits and a previous carry.
B. the sum of two bits, …. the sum of two bits and a carry
C. the sum of two bits, …. the sum of two bits and a present carry
D. the sum of two bits and a carry,… the sum of two bits
E. the sum of two bits and a previous carry, … the sum of two bits

8. Add in hex: A8D5+3CA9

A. D56D B. D56E C. D46D D. E56E E. E57E

9. A Boolean function is an expression, formed with

A. binary numbers
B. binary variables
C. binary variables and operators
D. binary variables, the two binary operators OR and AND, the unary operator NOT,
parentheses, and equal sign.
E. binary variables, the binary operators OR, AND, and NOT, parentheses, and equal sign

10. Equation for carry output of the second stage of look-ahead carry generator is
A. C2=G1+P1C1 B. C2=G1+P1 C. C2=G1+C1 D. C2=G1+P2C1 E. C2=G1+P1C2

25
 LABORATORY WORK # 7.

MAGNITUDE COMPARATOR.

Aims: investigate operation of the magnitude comparator as a MSI circuit.

PREPARATION TO LAB WORK.

1. Learn the information about magnitude comparator.

2. Fill in the table for experiment theoretically.
3.
4. Answer the questions below in written form.
4.1. What is magnitude comparator?
4.2. How many output signals may exist for magnitude comparator simultaneously and
why?
4.3. Why A<B, A>B inputs of the first 7485 must be grounded?
4.4. Why A=B input of the first 7485 must be HIGH?
4.5. What are outputs of the first 7485 if numbers for comparison are 00110111 and
00100101?
4.6. Show the scheme which is suitable to define if 4-bit binary number A is equal to the 4-
bit binary number B (use Scheme Design System).

LAB WORK PERFORMANCE.

1. Demonstrate presence of your home preparation for lab work to your instructor.
2. Pass test of 10 questions.
3. Get a permission to begin the work.
4. Mount the scheme of experiment 7 on the breadboard and perform it.
5. Make a conclusion about functionality of the scheme. Compare your results with
theoretical ones.
6. Demonstrate your results to your instructor. If your results are correct you may dismount
your scheme, if no – find the mistake.
7. Be ready to answer your instructor’s questions in process of work.
8. Complete your work, dismount your schemes, clean your working place.
9. Answer your instructor’s final questions, obtain your mark.
10. Ask your instructor’s permission to leave.

26
Experiment 7. Prepare the circuit on the breadboard. Apply the signals according to the table
below. Fill in the gaps. Write down ON or OFF for LEDs.

U1 U2
A 0 10 A 4 10
A0 A0
A 1 12 A 5 12
A1 A1
A 2 13 A 6 13
A2 A2
A 3 15 A 7 15 L 1
A3 A3
B 0 9 B 4 9
B0 B0
B 1 11 B 5 11
B1 B1
B 2 14 B 6 14 330
B2 B2
B 3 1 B 7 1 L 2
B3 B3
2 7 2 7
A<B A<B A<B A<B
4 5 4 5
A>B A>B A>B A>B
5V 3 6 3 6 330
A=B A=B A=B A=B
L 3

7485 7485

330

# Inputs outputs
A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 L1 L2 L3
1 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V
2 0V 0V 0V 0V 0V 0V 0V 5V 0V 0V 0V 0V 0V 0V 0V 0V
3 0V 0V 0V 0V 0V 0V 0V 5V 0V 0V 0V 0V 0V 0V 0V 5V

4 0V 5V 5V 0V 5V 5V 0V 0V 0V 5V 5V 0V 0V 2V 0V 0V

5 0V 5V 5V 0V 5V 5V 0V 0V 5V 5V 5V 0V 0V 2V 0V 0V

6 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V
7 5V 5V 5V 5V 5V 5V 5V 0V 5V 5V 5V 5V 5V 5V 5V 5V

7485 is a ____________________________________.

Conclusion.

27
 TEST QUESTIONS

1. The truth table for AND gate is:

A B C D E
X y F x y F x y F x y F x y F
0 0 0 0 0 0 0 0 1 0 0 1 0 0 0
0 1 0 0 1 1 0 1 1 0 1 0 0 1 1
1 0 0 1 0 1 1 0 1 1 0 0 1 0 1
1 1 1 1 1 1 1 1 0 1 1 0 1 1 0

2. Typical voltage for IC TTL logic family for negative logic is for HIGH -_____V, for LOW-
_____V. A. 0.2, 3.5 B. 3.5, 0.2 C. 5, 0 D. 0, 5 E. 0, 3.5

3. Power dissipation is
A. the power consumed by the gate
B. the power consumed by the gate, which must be available from the power supply
C. the power consumed by the gate, which may be available from the power supply
D. the power emitted by the gate
E. the power emitted by the gate, which may be available for the gates of the next level

4. 7485 is
A. 3*8 decoder B. 4-bit magnitude comparator C. Code converter
D. D flip-flop E. priority encoder

5. The circuit below is

X

F
Y

A. combinational B. sequential C. combinational, because it hasn’t any flip-flops

D. sequential, because it has a feedback path
E. sequential, because it has a feedback path between output and input

6. Function # _____ corresponds to function NOR of 3 variables.

X Y Z F1 F2 F3 F4 F5
0 0 0 0 0 0 0 1
0 0 1 0 0 1 1 0
0 1 0 0 0 1 1 0
0 1 1 1 1 1 1 0
1 0 0 0 1 1 1 0
1 0 1 1 1 1 0 0
1 1 0 1 1 1 0 0
1 1 1 1 1 1 1 0
A. 1 B. 2 C. 3 D. 4 E. 5

28
7. XY´+X´Y is algebraic expression of ________ function.
A. XOR B. XNOR C. NOR D. NAND E. AND

8. For 4-bit magnitude comparator if A>B function _________ must be realized

(xi=AiBi+A`iB`i).
A. A2B`2+ x2 A1B`1+ x2x1A0B`0
B. A`2B2+ x2 A`1B1+ x2x1 A`0B0
C. A3B`3+ x3 A2B`2+ x3x2 A1B`1+ x3x2 x1 A0B`0
D. A`3B3+ x3 A`2B2+ x3x2A`1B1+ x3x2 x1 A`0B0
E. all answers are wrong

9. What statement is correct?

A. Tabulation method is not applicable for functions of 4 variables
B. Number of different functions of two variables is equal to 8.
C. NOT is a binary operator
D. 4-bit magnitude comparator can be used for comparison of two BCD numbers.
E. Decoder with enable can be used as multiplexer

10. To answer the question if two 4-bit binary numbers are equal each other for the circuit it is
enough to use __________
A. 4XOR gates B. 4XNOR gates
C. 4XOR gates and one AND gate D. 4XNOR gates and one 4-input AND gate
E. 4XNOR gates and one 4-input OR gate

29
 LABORATORY WORK # 8.

DECODER AND DEMULTIPLEXER.

Aims: investigate operation of the 2*4 decoder with enable as a decoder and as a
demultiplexer.

PREPARATION TO LAB WORK.

1. Learn the information about decoder and demultiplexer.

2. Consider the scheme of experiment 8A and define the results theoretically. Draw the
scheme using Scheme Design System.
3. Construct 3*8 decoder using 2 decoder/demultiplexer ICs (74139) and an inverter for
experiment 8B. Draw it using Scheme Design System.
4. Answer the question below in written form.
4.1. What is a decoder?
4.2. What is a DUX?
4.3. Show the principal scheme of 2*4 decoder with application of Scheme Design System.
4.4. What is enable input for a decoder?
4.5. Decoder with an enable input can work as ________.
4.6. Compare decoder and encoder.
4.7. Compare DUX and MUX.
4.8. Show the scheme of 2*4 decoder on the basis of NOR gates (use Scheme Design
System).

LAB WORK PERFORMANCE.

1. Demonstrate presence of your home preparation for lab work to your instructor.
2. Pass test of 10 questions.
3. Get a permission to begin the work.
4. Mount the scheme of experiment 8A on the breadboard and perform it. Fill in table #1.
5. Make a conclusion about functionality of the scheme. Compare your results with
theoretical ones.
6. Demonstrate your results to your instructor. If your results are correct you may dismount
your scheme, if no – find the mistake.
7. Repeat steps 4-6 for the experiment 8B.
8. Demonstrate your results to your instructor. If your results are correct you may dismount
your scheme, if no – find the mistake.
9. Be ready to answer your instructor’s questions in process of work.
10. Complete your work, dismount your schemes, clean your working place.
11. Answer your instructor’s final questions, obtain your mark.
12. Ask your instructor’s permission to leave.

30
Experiment 8A. Realize the circuit below on the breadboard.

U1A
X 1 2 1
2 12 R4
R1 U3A 13 330
330 LED L4
74LS04 74LS10

U1B
LED L1 3
4 6 R5
5 330
LED L5
74LS10

U3B U1C
9
Y 3 4 10 8 R6
11 330
R2 LED L6
74LS04 74LS10
330

U2A
1
LED L2 2 12 R7

U3C 13 330
LED L7
E 5 6 74LS10

R3
74LS04
330

LED L3

Table #1
INPUTS OUTPUTS
E X Y LED1 LED2 LED3 LED4 LED5 LED6 LED7
1 0V 0V 0V
2 0V 0V 5V
3 0V 5V 0V
4 0V 5V 5V
5 5V X X
As a result, this truth table belongs to a …………………………….

Experiment 8B. Construct 3*8 decoder using 2 decoder/demultiplexer ICs (74139) and an
inverter. Mount the scheme on a breadboard and fill the table below.

Table #2
INPUTS OUTPUTS
X Y Z L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11
1 0V 0V 0V
2 0V 0V 5V
3 0V 5V 0V
4 0V 5V 5V
5 5V 0V 0V
6 5V 0V 5V
7 5V 5V 0V
8 5V 5V 5V

31
 TEST QUESTIONS

1. A decoder is a combinatioal circuit that

A. converts binary information from n input lines to a maximum of 2n unique output lines
B. has 2n (or less) unique input lines and n output lines
C. selects binary information from one of many input lines and direct it to a single output line
D. receives information on a single line and transmits this information on one of 2n possible
output lines
E. converts binary information from n input lines to m output lines

2. Output of 1*4 demultiplexer is D1. What are selection lines?

D 0

1*4
D 1
E
DUX D 2

D 3

A B

A. 00 B. 01 C. 10 D. 11 E. any of them

3. What signals for XYZ inputs are applied if active output is D 0 ?

D0 A.0, 0, 0
B. 0, 1, 1
Z
C. 1, 0, 0
D1 D. 0, 1, 0
E. 0, 0, 1
Y D 2

X
D
3

D4

D
5

D
6

D7

4. Decoder is __________ component.

A. SSI B. MSI C. LSI D. VLSI E. SSI or MSI

32
5. What function F1 is implemented with a decoder and external gate?

3*8 0 A. 0
decode
r
1 F1 B. 1
2 C. XY
X 2
2 3 D. X`Y`
Y 1 4 E. XYZ`
2 F2
5
Z 0
2 6
7

6. What statement is correct?

A. A decoder can be realized on the basis of OR gates.
B. A decoder can be used as a MUX.
C. A decoder can be used as a data selector.
D. A 3-to-8 line decoder can be used for a binary-to-BCD conversion.
E. A 3-to-8 line decoder can be used for a binary-to-octal conversion.

7. What input signals must be applied to WXYZ for the circuit below if D 8 is generated as
output?
A. 0110
X D to D
0 7 B. 0111
Y 3*8 C. 1000
decoder
Z D. 1001
E
W
E. 1010

D 8 to D 15

3*8
decoder

8. Fill in the gaps.

If we use NAND gates for decoder the outputs will be active-____. It means that only one
output will be _______ at the moment, others will be _____.
A. HIGH, HIGH, LOW B. HIGH, LOW, HIGH C. LOW, HIGH, HIGH
D. LOW, LOW, HIGH E. all answers are wrong

9. DUX sometimes is called

A. code converter B. data selector C. data distributor
D. decoder E. all answers are correct

10. The scheme in question 3 is________.

A. 1-of-8 decoder B. 3-to-8 line decoder C. binary-to-octal decoder
D. A,B,C are correct E. A,B,C are wrong

33
 LABORATORY WORK # 9.

ENCODER.

Aims: investigate operation of the octal-to-binary encoder.

PREPARATION TO LAB WORK.

1. Learn the information about encoder

2. Consider the scheme of experiment 9A and define the results theoretically. Draw the
scheme using Scheme Design System.
3. Implement the scheme of octal-to-binary encoder using OR gates and draw the scheme
with application of Scheme Design System. This will be the scheme for the experiment 9B.
4. Answer the question below in written form.
4.1. What is an encoder?
4.2. What is a priority encoder?
4.3. Show the principal scheme of octal-to-binary and explain why D0 is not connected
with any of OR gates.
4.4. What discrepancy may be for this scheme?

LAB WORK PERFORMANCE.

1. Demonstrate presence of your home preparation for lab work to your instructor.
2. Pass test of 10 questions.
3. Get a permission to begin the work.
4. Mount the scheme of experiment 9A on the breadboard and perform it. Fill in the table.
5. Make a conclusion about functionality of the scheme. Compare your results with
theoretical ones.
6. Demonstrate your results to your instructor. If your results are correct you may dismount
your scheme, if no – find the mistake.
7. Repeat steps 4-6 for experiment 9B.
8. Be ready to answer your instructor’s questions in process of work.
9. Complete your work, dismount your schemes, clean your working place.
10. Answer your instructor’s final questions, obtain your mark.
11. Ask your instructor’s permission to leave.

34
Experiment 9A. Realize the following circuit on a breadboard. Connecting D 0-D7 to GND or
VCC based on the following table, fill in the blanks. Write ON or OFF for LEDs. Remember
that EI is active LOW enable input: a HIGH on this input forces all outputs to their inactive
(HIGH) state; EO is active-LOW enable output: this output pin goes LOW when all inputs are
inactive (HIGH) and EI is LOW; GS is active-LOW group signal output: this output pin goes
LOW whenever any of the inputs are active (LOW) and EI is LOW.

LED1

330

LED2

330
U? LED3
D0 10 9
D1 0 A
11 7 330
D2 1 B
12 6
2 C
D3 13 LED4
3
D4 1 14
D5 4 GS
2 330
D6 5
3
6
D7 4
7
LED5
E 5 15
EI EO
330
74LS148

INPUTS OUTPUTS
(EI)’ D0 ’ D1 ’ D2 ’ D3 ’ D4 ’ D5 ’ D6 ’ D7 ’ GS’ A B C EO’

1 5 x x x x x x x x
2 0 5 5 5 5 5 5 5 5
3 0 x x x x x x x 0
4 0 x x x x x x 0 5
5 0 x x x x x 0 5 5
6 0 x x x x 0 5 5 5
7 0 x x x 0 5 5 5 5
8 0 x x 0 5 5 5 5 5
9 0 x 0 5 5 5 5 5 5
10 0 0 5 5 5 5 5 5 5

Experiment 9B. Implement the scheme of octal-to-binary encoder using OR gates and mount
it on the breadboard. Fill in the table below. Compare your results with the table above.
INPUTS OUTPUTS
D0 D1 D2 D3 D4 D5 D6 D7 A B C

1 5 0 0 0 0 0 0 0
2 0 5 0 0 0 0 0 0
3 5 5 0 0 0 0 0 0
4 0 0 5 0 0 0 0 0
5 0 5 5 0 0 0 0 0
6 0 0 5 0 0 5 0 0
7 0 0 0 5 0 0 0 0
8 0 0 0 0 5 0 0 0
9 0 0 5 5 5 5 5 5
10 0 5 5 5 5 5 5 5

Conclusion.

35
 TEST QUESTIONS

1. An encoder is a combinational circuit that

A. converts binary information from n input lines to a maximum of 2 n unique output lines
B. has 2n (or less) unique input lines and n output lines
C. selects binary information from one of many input lines and direct it to a single output line
D. receives information on a single line and transmits this information on one of 2 n possible
output lines
E. converts binary information from n input lines to m output lines

2. If D1 is active input outputs XYZ will be _______

D0 A.111
X
D1 B. 100
D2 C.101
D3 D.011
Y
E. 001
D4
D5
D6 Z
D7

3. 74139 is
A. decoder
B. DUX
C. MUX
D. dual 2-to-4 line decoder
E. triple 3-input NAND gate

4. DUX sometimes is called

A. code converter B. data selector C. data distributor
D. decoder E. all answers are correct

5. What output of 1*4 demultiplexer will be chosen if selection lines AB=00?

D 0

1*4
D 1
E
DUX D 2

D 3

A B

A. D1 B. D0 C. D2 D. D3 E. any of them

36
6. For the circuit below if EI=5V, D1=0, D5=0 the state of L1 to L5 will be:
LED1

330

LED2

330
U? LED3
D0 10 9
D1 0 A
11 7 330
D2 1 B
12 6
2 C
D3 13 LED4
3
D4 1 14
D5 4 GS
2 330
D6 5
3
6
D7 4
7
LED5
E 5 15
EI EO
330
74LS148

A. ON,ON,ON,ON,ON B. OFF,OFF,OFF,ON,ON
C. ON,ON,ON,OFF,OFF D. OFF,OFF, ON,ON,ON,
E. OFF, ON,ON,ON, OFF

7. For the circuit in question 6 if EI=0, D0 to D7=5V the state of L1 to L5 will be:
A. ON,ON,ON,ON,OFF B. OFF,OFF,OFF,ON,ON
C. ON,ON,ON,OFF,OFF D. OFF,OFF, ON,ON,ON,
E. OFF, ON,ON,ON, OFF

8. For the circuit in question 6 enable input is active-______. A ____ on this input forces all
outputs to their inactive _____ state.
A. LOW, HIGH, LOW B.LOW, LOW, HIGH,
C. HIGH, LOW, HIGH D. HIGH, HIGH, LOW E. LOW, HIGH, HIGH

9. For priority encoder we have got input lines D1, D3, and D6 active simultaneously. In such
case output signal will be corresponded to …
A. D1 B. D3 C. D6 D. D1or D3 E. D3 or D6

10. For the circuit in question 6 output signals are: L1 is ON, L2 is ON, L3 is ON, GS is OFF,
EO is ON. It means that
A. the chip is disabled B. any input signal is absent
C. number 7 is encodered D. number 0 is encodered
E. all answers are wrong

37
 LABORATORY WORK # 10.

MULTIPLEXER.

Aims: investigate operation of the 8*l multiplexer.

PREPARATION TO LAB WORK.

1. Learn the information multiplexer

2. Consider the scheme of experiment 10A and define the results theoretically. Draw the
scheme using Scheme Design System (SDS).
3. Construct and draw (using SDS) 16*1 multiplexer with 2 8*1 multiplexers and an OR gate.
This will be the scheme for experiment 10B
4. Answer the question below in written form.
4.1. What is a MUX?
4.2. A MUX’s another name is __________
4.3. Enable input of a MUX is called________.
4.4. How many functions can a MUX realize?
4.5. A MUX can be used as a DUX. True or false? Why?
4.6. What is a role of a MUX’s selection lines?

LAB WORK PERFORMANCE.

1. Demonstrate presence of your home preparation for lab work to your instructor.
2. Pass test of 10 questions.
3. Get a permission to begin the work.
4. Mount the scheme of experiment 10A on the breadboard and perform it. Fill in the table.
5. Make a conclusion about functionality of the scheme. Compare your results with
theoretical ones.
6. Demonstrate your results to your instructor. If your results are correct you may dismount
your scheme, if no – find the mistake.
7. Repeat steps 4-6 for experiment 10B.
8. Be ready to answer your instructor’s questions in process of work.
9. Complete your work, dismount your schemes, clean your working place.
10. Answer your instructor’s final questions, obtain your mark.
11. Ask your instructor’s permission to leave.

38
Experiment 10A. Realize the following circuit on a breadboard. Connecting I 0-I7 to GND or
VCC based on the following table, fill in the blanks (X-don’t –care conditions). Write ON or
OFF for LEDs.
U? L5
4 5 330
I0 Z
3
I1
2 6
I2 Z
1 330
I3
S0 S 1 S2 15
I4
14 L 6
I5
13
I6
L4 12
I7
330 11
A
10
B
9
C
7
330 E
E
330 74151
330
L
3 L 2

L 1

N Inputs outputs
I0 I1 I2 I3 I4 I5 I6 I7 E S2 S1 S0 Z Z’
L1 L2 L3 L4 L5 L6
1 0 5V 5V 0 5V 5V 0 5V 0 0 0 0
2 0 5V 5V 0 5V 5V 0 5V 0 0 0 5V
3 0 5V 5V 0 5V 5V 0 5V 0 0 5V 0
4 0 5V 5V 0 5V 5V 0 5V 0 0 5V 5V
5 0 5V 5V 0 5V 5V 0 5V 0 5V 0 0
6 0 5V 5V 0 5V 5V 0 5V 0 5V 0 5V
7 0 5V 5V 0 5V 5V 0 5V 0 5V 5V 0
8 0 5V 5V 0 5V 5V 0 5V 0 5V 5V 5V
9 5V 0 0 0 0 0 5V 5V 0 0 0 0
10 5V 0 0 0 0 0 5V 5V 0 0 0 5V
11 5V 0 0 0 0 0 5V 5V 0 0 5V 0
12 5V 0 0 0 0 0 5V 5V 0 0 5V 5V
13 5V 0 0 0 0 0 5V 5V 0 5V 0 0
14 5V 0 0 0 0 0 5V 5V 0 5V 0 5V
15 5V 0 0 0 0 0 5V 5V 0 5V 5V 0
16 5V 0 0 0 0 0 5V 5V 0 5V 5V 5V
17 5V 0 0 0 0 0 5V 5V 5V X X X
18 5V 0 0 0 0 0 5V 5V 5V X X X
19 5V 0 0 0 0 0 5V 5V 5V X X X

Experiment 10B. Construct and mount 16*1 multiplexer with 2 8*1 multiplexers and an OR
gate. Define how should inputs I0-I15 be connected so that the output of the circuit (Z) would
match the table below, which shows the relation between configuration of selection lines (S)
and output of the circuit (Z).
S 5 1 12 7 6 8 15 9 0 3 11 2 4 10 13 14
Z 1 1 0 0 0 1 0 1 1 1 0 1 1 1 0 1

Conclusion.

39
 TEST QUESTIONS

1. A multiplexer is a combinational circuit that

A.converts binary information from n input lines to a maximum of 2n unique output lines
B. has 2n (or less) unique input lines and n output lines
C. selects binary information from one of many input lines and direct it to a single output line
D. receives information on a single line and transmits this information on one of 2n possible
output lines
E. converts binary information from n input lines to m output lines

2. Strobe is
A. enable input of decoder B. disable input of decoder
C. enable input of multiplexer D. disable input of demultiplexer
E. disable input of multiplexer

3. What will the output signal of 4*1 multiplexer be if selection lines S 1S0=11?

I 0

4*1 A. I0
I 1

Y B. I1
I 2 MUX C. I2
I3 S1 S 0 D. I3
E. any of them

4. What are selection lines of 4*1 multiplexer if output signal Y=I1 ?

I 0
A. 00
4*1 B. 01
I 1
C. 10
Y D. 11
I 2 MUX
E. any of them
I3 S1 S 0

5. What function is implemented with multiplexer?

A I 0 4*1 A. F(A,B,C)=Σ(2,3,5,6)
0 I 1 MUX B. F(A,B,C)=Σ(1,3,5,6)
F
1 I 2 Y C. F(A,B,C)=Σ(2,3,5,7)
A' I 3 D.F(A,B,C)=Σ(2,3,4,6)
S1 S0 E. F(A,B,C)=Σ(1,3,5,7)
B 0 I 0
8*1
C I 1 MUX
I 2
1
I 3

6. What function is implemented with multiplexer? F

I 4 Y
I 5

A. F(A,B,C,D)= Σ(2,5,6,7,10,11,12,13,14) I 6

A' I
B. F(A,B,C,D)= Σ(0,1,3,4,7,14) 7

C. F(A,B,C,D)= Σ(0,1,3,4,8,15) S2 S1 S0

D. F(A,B,C,D)= Σ(0,1,3,4,8,9,15) B

E. F(A,B,C,D)= Σ(0,1,3,5,7,14,15) C
D

40
7. Decoder is __________ component.
A. SSI B. MSI C. LSI D. VLSI E. SSI or MSI
8. For the circuit below if selection lines S 2S1S0=011 the output Z will be ____, if S2S1S0=100,
Z will be ____, if S2S1S0=001, Z will be ____.
U?
1 4 5 330
I0 Z
1 3
I1
0 2 6
I2 Z
1 1 330
I3
S0 S 1 S2 0 15
I4
1 14
I5
0 13
I6
1 12
I7
330 11
A
10
B
9
C
7
330 0 E
330 74151
330

A. 1,1,0 B. 0,1,1 C. 1,1,1 D. 0,1,0 E.1,0,1

9. For the circuit in question 8 the output Z is equal to _____ for periods of time between t 3 and
t4, t4 and t5, t5 and t6.

t0 t1 t2 t 3 t 4 t 5 t6 t7 t8 t 9 t 10 t 11

E'

S 0

S 1

S 2

A. 0,1,1 B. 0,1,0 C. 1,1,1 D. 0,0,1 E. 1,0,1

10. What function is implemented with multiplexer?

1 I 0
A. F(A,B,C,D)= Σ(0,1,3,4,5,8,15)
8*1
I 1 MUX
0 I 2
B. F(A,B,C,D)= Σ(0,1,3,4,7,14)
I 3
F
I 4 Y C. F(A,B,C,D)= Σ(0,1,3,4,8,15)
I 5

I 6 D. F(A,B,C,D)= Σ(0,1,3,4,8,9,15)
B I 7

E. F(A,B,C,D)= Σ(0,1,3,5,7,14,15)
S2 S1 S0

A
C
D

41
 LABORATORY WORK # 11.

D- FLIP-FLOP.

Aims: investigate operation of the D-flip-flop.

PREPARATION TO LAB WORK.

1. Learn the information about flip-flops.

2. Consider the scheme of experiment 11A and define the results theoretically. Draw the
circuit with application of Scheme Design System.
3. Draw the D-flip-flop implemented with NAND gates (using Scheme Design System) for
the experiment 11B.
4. Answer the question below in written form.
4.1. What circuit is called sequential?
4.2. What sequential circuit is called synchronous?
4.3. What sequential circuit is called asynchronous?
4.4. What is a master-clock generator?
4.5. What circuits are called clocked sequential circuits?
4.6. What is a flip-flop?
4.7. What types of flip-flops do you know?
4.8. Show truth tables for all types of flip-flops.
4.9. Show the typical schemes of RS, D, T, JK-flip-flops and describe their operation.
(Use Scheme Design System).
4.10. What is a master-slave flip-flop?
4.11. What is setup time and hold time for flip-flop?
4.12. Show excitation tables for all types of flip-flops.
4.13. What types of flip-flops’ triggering do you know?

LAB WORK PERFORMANCE.

1. Demonstrate presence of your home preparation for lab work to your instructor.
2. Pass test of 10 questions.
3. Get a permission to begin the work.
4. Mount the scheme of experiment 11A on the breadboard and perform it. Fill in the table.
5. Make a conclusion about functionality of the scheme. Compare your results with
theoretical ones.
6. Demonstrate your results to your instructor. If your results are correct you may dismount
your scheme, if no – find the mistake.
7. Repeat steps 4-6 for experiment 11B.
8. Be ready to answer your instructor’s questions in process of work.
9. Complete your work, dismount your schemes, clean your working place.
10. Answer your instructor’s final questions, obtain your mark.
11. Ask your instructor’s permission to leave.

42
Experiment 11A. Realize the following circuit on a breadboard. Connecting D, CLK, CD,
and SD inputs to either GND or VCC based on the following table, fill in the blanks. Write ON
or OFF for LEDs.
R1 SD R4

330 330

4
D LED 1 LED 4
74LS74 U?A
2 5 R5

SD
R2 D Q
330
3 LED 5
330 CLK
C LK LED 2
R6

CD
6
Q
330
R3 LED 6

1
330
CD LED 3

INPUTS OUTPUTS
D CLK CD SD LED1 LED2 LED3 LED4 LED5 LED6
1 0V 0V 5V 5V
2 0V 5V 5V 5V
3 0V 0V 5V 5V
4 5V 0V 5V 5V
5 5V 5V 5V 5V
6 5V 0V 5V 5V
7 5V 0V 0V 5V
8 5V 0V 5V 5V
9 5V 0V 5V 0V
10 5V 0V 5V 5V
11 5V 0V 0V 5V
12 5V 0V 5V 5V
13 5V 0V 5V 0V
14 5V 0V 5V 5V
15 0V 0V 5V 5V
16 0V 0V 0V 5V
17 0V 0V 5V 5V
18 0V 0V 5V 0V
19 0V 0V 5V 5V
20 0V 5V 5V 5V
21 0V 0V 5V 5V
22 0V 0V 0V 5V
23 * 0V 0V 0V 0V
24 0V 0V 5V 0V
25 0V 0V 5V 5V
* be careful at that stage!
Based on the above truth table, it is a ………. type flip flop, with ……… is the input, …….. is
the clock input, ……….. is the output, and ……… is the inverting output. SD is
………………………… and CD is …………………………

Experiment 11B. Mount the D-Flip-Flop circuit implemented with NAND gates on the
breadboard. Compare results with the results obtained in experiment 11A.

Conclusion.

43
 TEST QUESTIONS

1. ________ flip-flop gives us uncertainty if set and reset inputs have value 1 at the same time.
A. RS and clocked RS B.RS or clocked RS C. D D. JK E. T

2. This is characteristic table of _____ flip-flop.

Q (t+1)
0 0
1 1
A. RS B. Clocked RS C. D D. JK E. T

3. This is excitation table of _______ flip-flop.

Q(t) Q (t+1)
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
A. RS B. Clocked RS C. D D. JK E. T

4. What state sequence for Q(t+1) is correct?

J K Q (t+1)
0 0
0 1
1 0
1 1
A. 1, 0, Q(t), ? B. 1, 0,?, Q(t) C. Q(t), 0,1,Q´(t) D. Q(t), 0,1, 1 E. Q(t), 0,1, 0

5. Set-dominate flip-flop has got ______ input(s).

A. 1 B. 2 C. 1 or 2 D. 3 E. 2 or 3

6. D flip-flop characteristic equation is _____

A. Q(t+1)=DQ B. Q(t+1)=D+Q C. Q(t+1)=D
D. Q(t+1)=D´Q E. Q(t+1)=D´

7. A state equation of the sequential circuit is

A. an expression to describe next state of the circuit
B. an expression to describe present state of the circuit
C. a Boolean function that specifies the present state conditions
D. a Boolean function that specifies the present state conditions that make the next state equal to 1
E. a Boolean function that specifies the next state conditions that make the present state equal to 1

8. How many options to gain state 10 will the circuit with the state table below have?
Present state Next state
X=0 X=1
A B A B A B
0 0 0 1 1 1
0 1 1 0 0 0
1 0 0 0 0 0
1 1 0 1 1 0
A. 1 B. 2 C. 3 D. 4 E. 5

44
9. What is the input equation for D flip-flop for the circuit below?

A. A+X
X A
B. AX
D Q
Z C. AXY
D. XY
Y CP E. XYA

10. For the circuit below X=1,B=1,Y=1,C=1. What will be the next state for the flip-flop?
A. set B. reset C. complement D. No change E. none

X
B
A
J Q
Y K
Z C
P CL
R
FJK
C

45
 LABORATORY WORK # 12.

COUNTERS.

Aims: investigate the operations of switch tail ring counter and ripple counter.

PREPARATION TO LAB WORK.

1. Learn the information about flip-flops, registers and counters.

2. Prepare logic diagram of 4-stage switch-tail ring counter using 4 D-flip-flops, and draw it
with application of Scheme Design System. This circuit will be used in experiment 12A.
3. Construct a 4-bit asynchronous ripple counter with 4 JK-flip-flops for the experiment 12B,
and draw it with application of Scheme Design System.
4. Answer the question below in written form.
4.1. What is a word-time signal?
4.2. What is a ring counter?
4.3. What is switch tail ring counter?
4.4. What is ripple counter?
4.5. What is BCD counter?
4.6. What is the difference between synchronous and asynchronous counters?

LAB WORK PERFORMANCE.

1. Demonstrate presence of your home preparation for lab work to your instructor.
2. Pass test of 10 questions.
3. Get a permission to begin the work.
4. Mount the scheme of experiment 12A on the breadboard and perform it. Fill in the table.
5. Make a conclusion about functionality of the scheme. Compare your results with
theoretical ones.
6. Demonstrate your results to your instructor. If your results are correct you may dismount
your scheme, if no – find the mistake.
7. Repeat steps 4-6 for experiment 12B.
8. Be ready to answer your instructor’s questions in process of work.
9. Complete your work, dismount your schemes, clean your working place.
10. Answer your instructor’s final questions, obtain your mark.
11. Ask your instructor’s permission to leave.

46
Experiment 12A. Construct the logic diagram of 4-stage switch-tail ring counter using 4
D-flip-flops, and mount it on the breadboard. Apply direct clear CD signal for all flip-flops.
Apply active CP (clock pulse) 8 times, observing all D-flip-flops outputs (A, B, C, and E)
behavior. Fill in the table.
# CD CP A B C E
1 0
2 5V ↑
3 5V ↑
4 5V ↑
5 5V ↑
6 5V ↑
7 5V ↑
8 5V ↑
9 5V ↑

Experiment 12B. Construct a 4-bit asynchronous ripple counter with 4 JK-flip-flops, and
mount it on the breadboard. Apply direct clear CD signal for all flip-flops. Apply active CP
(clock pulse) 8 times, observing all JK-flip-flops outputs (A, B, C, and D) behavior. Fill in the
table.

# CD CP A B C D
1 0
2 5V ↑
3 5V ↑
4 5V ↑
5 5V ↑
6 5V ↑
7 5V ↑
8 5V ↑
9 5V ↑

Conclusion.

47
 TEST QUESTIONS

1. Sequential MSI circuits may be

A. decoder, register, counter B. multiplexer, register, counter
C. demultiplexer , register, counter D. ROM, register, counter
E. register, counter, random-access memory

2. The content of a 4-bit shift register is initially 1101. The register is shifted 6 times to the
right, with the serial input being 101101. What is the content of the register after the second
shift?
A. 0101 B. 1100 C. 1110 D. 1101 E. 0111

3. What statement is correct?

A. Number of different functions of two variables is equal to 8.
B. In a ripple counter, the flip-flop output transition serves as a source for triggering other flip-
flops.
C. NOT is a binary operator
D. Computers may operate in a serial mode and in a parallel mode
E. Decoder with enable can be used as multiplexer

4. The circuit below is

B
F
A

F2

A. combinational B. sequential C. combinational, because it hasn’t any flip-flops

D. sequential, because it has a feedback path
E. sequential, because it has a feedback path between output and input

5. Sequence of 12 timing signals can be produced by Johnson counter if it has got ____ flip-
flops.
A. 7 B. 6 C. 5 D. 4 E. 3

6. For the scheme of Johnson shift counter the correct sequence of states are:
A. 0000, 0001, 0010, 0011 B. 0000, 1000, 1100, 1110
C. 0000, 1000, 1001, 1010 D. 0000, 1000, 0001, 1001
E. 0000, 0001, 1000, 1001

48
7. For the table below the sequence for KC is
A. X,X, X, 0,0,1 B. 0,0,1,X,X,X C. 0,1,X,0,1,X D. X,1,X,X,1,X E. 1,1,0,1,0,0
Count sequence Flip-flop inputs
A B C JA KA JB KB JC KC
0 0 0 0 X 0 X 1
0 0 1 0 X 1 X X
0 1 0 1 X X 1 0
1 0 0 X 0 0 X 1
1 0 1 X 0 1 X X
1 1 0 X 1 X 1 0

8. This is characteristic table of _____ flip-flop.

Q (t+1)
0 0 Q(t)
0 1 0
1 0 1
1 1 Q´(t)
A. RS B. Clocked RS C. D D. JK E. T

9. For the circuit below (positive-edge-triggered D flip-flop) if CP=0 and D=0 level of signals
for NAND gate #1 is ______, NAND #2 is ____, NAND #4 is ______.

1 A. 1, 0, 1
B. 0, 1, 1
S
2 Q C. 0, 1, 0
5 D. 1, 0, 0
CP E. 1, 1, 0

3 6
Q`
R

D 4

10. What statement defines count down operation?

A. A←A+1 B. A←A-1 C. F←A+1 D. F←A-1 E. A←A`+1

49
 LABORATORY WORK # 13.

UP/DOWN COUNTER, DRIVER, and SEVEN SEGMENT DISPLAY.

Aims: investigate operation of the device, improving students’ design and analytical skills.

PREPARATION TO LAB WORK.

1. Learn the information about counter and seven-segment drive.

2. Consider scheme of experiment 13 and prepare functionally equal scheme with application
of common anode display (use Scheme Design System).
3. Fill in table #1 theoretically.
4. Configure the circuit so that it would count down. Fill in table #2.
4. Answer the questions in writing form:
A. Explain 7447 principle of operation.
B. Explain 74192 principle of operation.

LAB WORK PERFORMANCE.

1. Demonstrate presence of your home preparation for lab work to your instructor.
2. Pass test of 10 questions.
3. Get a permission to begin the work.
4. Mount your schemes of the experiments on the breadboard and fill in tables#1 and #2.
5. Make a conclusion about functionality of the scheme.
6. Demonstrate your results to your instructor. If your results are correct you may dismount
your scheme, if no – find the mistake.
7. Be ready to answer your instructor’s questions in process of work.
8. Complete your work, dismount your schemes, clean your working place.
9. Answer your instructor’s final questions, obtain your mark.
10. Ask your instructor’s permission to leave.

50
EXPERIMENT 13. Realize the following circuit on a breadboard. By pressing and releasing the
switch (SW), fill in the blanks on the following table.

Table #1
SW LED3 LED2 LED1 LED0 DISPLAY
1 Press, Release
2 Press, Release
3 Press, Release
4 Press, Release
5 Press, Release
6 Press, Release
7 Press, Release
8 Press, Release
9 Press, Release
10 Press, Release
11 Press, Release

Table #2
SW LED3 LED2 LED1 LED0 DISPLAY
1 Press, Release
2 Press, Release
3 Press, Release
4 Press, Release
5 Press, Release
6 Press, Release
7 Press, Release
8 Press, Release
9 Press, Release
10 Press, Release
11 Press, Release

51
 TEST QUESTIONS

1. If anode of each LED of the seven-segment display is connected to the 5-V supply the chip
is a _____ display. It is an active-____, because it takes a _____ to illuminate a segment.
A.common-anode, LOW, LOW B. common-cathode, LOW, LOW
C. common-anode, HIGH, HIGH D. common-cathode, HIGH, HIGH
E. common-anode, HIGH, LOW

2. To have #9 on one-digit seven segment display it needs to illuminate ________ segments.

A. a, c, d, e, f, g B. a, c, d, e, f C. a, b, c, f, g D. c, d, e, f, g E. a, b, c, d, e, f

3. The circuit below can’t count _______.

A. up B. down C. up and down D. None E. It is not a counter

A1 A2 A3 A4

1 1 1 1
J Q J Q J Q J Q
1 K 1 K 1 K 1 K
count pulses
CLR CLR CLR CLR

FJKC FJKC FJKC FJKC

4. 7447 is
A. 3*8 decoder B. 4-bit magnitude comparator C. priority encoder
D. D flip-flop E. BCD-to-seven-segment decoder/driver

5. Master-reset input is the input

A. to initialize the states of all flip-flops in the system
B. to initialize the states of all flip-flops in the system, when clock pulse will appear C. to
change the states of all flip-flops in the system
D. To clear all flip-flops asynchronously E. to set all flip-flops asynchronously

6. Enable input is the input

A. to make a device active B. to provide the normal device’s operation
C. to control the circuit operation D. to make the circuit sensitive
E. to have part of the circuit active

7. 74192 is
A. up/down counter B. a BCD counter C. a BCD decade counter
D. a BCD decade up/down counter E. a register

8. The terminal count up (TCu) and terminal count down (TCd) of 74193 are normally ____.
The TCu is used to indicate that ____ count is reached.
A. HIGH, 9th B.LOW, 9th C. HIGH, 15th D. LOW, 15 E. LOW, maximum

52
9. What can you say about state of diodes 1, 2, 3 in the picture?

+5V
+5V
+5V
V 2 D 3
D D 2 kW
1 V 3 V 4
V 1

D 4

5kW kW kW D 5

kW

A. reverse, forward, reverse B. reverse, forward, forward

C. forward, reverse, forward D. Reverse, reverse, forward
E. forward, forward, reverse

10. Parallel load input is used to change the counter _____ regardless of the conditions of the
clock _______.
A. inputs, output B. inputs, outputs C. outputs, input D. outputs, inputs
E. output, input

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 LABORATORY WORK # 14.

BIDIRECTIONAL SHIFT REGISTER.

Aims: investigate operation of the registers, improving students’ design and analytical skills.

PREPARATION TO LAB WORK.

1. Learn the information about registers.

2. Draw the circuit (using Scheme Design System) for 4-bit bidirectional shift register,
connecting outputs of the register to LEDs as shown in experiment 14A.
3. Fill in table theoretically.
4. Construct the circuit (using Scheme Design System) for 8-bit bidirectional shift regidter on
the basis of experiment 14A. Use the resulting scheme in experiment 14B.
5. Answer the questions in writing form:
5.1. What is register?
5.2. What types of registers do you know?
5.3. Explain parallel-in serial-out register.
5.4. Explain 7447 principle of operation.
5.5. Explain 74192 principle of operation.

LAB WORK PERFORMANCE.

1. Demonstrate presence of your home preparation for lab work to your instructor.
2. Pass test of 10 questions.
3. Get a permission to begin the work.
4. Mount your schemes of the experiment 14A on the breadboard and fill in table.
5. Make a conclusion about functionality of the scheme.
6. Demonstrate your results to your instructor. If your results are correct you may dismount
your scheme, if no – find the mistake.
7. Repeat steps 4-6 for experiment 14B.
8. Be ready to answer your instructor’s questions in process of work.
9. Complete your work, dismount your schemes, clean your working place.
10. Answer your instructor’s final questions, obtain your mark.
11. Ask your instructor’s permission to leave.

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EXPERIMENT 14A. Implement the following circuit on a breadboard and fill in the blanks on the
following table.

Table #1
SR SL S0 S1 CLK LED4 LED3 LED2 LED1
1 0 0 0 0 ↑
2 1 0 1 0 ↑
3 1 0 1 0 ↑
4 1 0 1 0 ↑
5 1 0 0 1 ↑
6 1 0 0 1 ↑
7 0 1 0 1 ↑
8 0 1 0 1 ↑
9 0 0 0 1 ↑
10 1 1 0 0 ↑
11 1 1 1 1 ↑

EXPERIMENT 14B. Implement the circuit of 8-bit bidirectional shift regidter using 2 4-bit
bidirectional shift registers. Make appropriate connections. Configure your circuit so that it
would shift the information 8 times to the left and then 8 times to th right. Compare it with the
circuit in experiment 14A. Make conclusion.

Conclusion.

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 TEST QUESTIONS

1. The transfer a new information into register is called _____ of register.

A. triggering B. Loading C. Set D. Reset E. none of above mentioned

2. Loading of register is done in parallel if

A. the bits of the register are loaded simultaneously
B. all the bits of the register are loaded simultaneously
C. all the bits of the register are loaded simultaneously with a clock pulse
D. all the bits of the register are loaded simultaneously with a single clock pulse
E. the bits of the register are loaded simultaneously with a single clock pulse

3. How many control signals has bidirectional shift register with parallel load got?
A. 2 B. 3 C.4 D.5 E.6

4. The content of a 4-bit shift register is initially 1101. The register is shifted 6 times to the
right, with the serial input being 101101. What is the content of the register after the first shift?
A. 0101 B. 1100 C. 1110 D. 1101 E. 1010

5. What types of operation bidirectional shift register with parallel load has?
A. shift right, parallel load B. shift left, parallel load
C. shift right, shift left, parallel load D. Complement, no change
E. shift right, shift left, parallel load, no change

6. Feedback shift register is such type of register, when

A. each flip-flop transfers its content to the next flip-flop
B. each flip-flop transfers its content to the next flip-flop, when a clock pulse occurs
C. each flip-flop transfers its content to the next flip-flop, when a clock pulse occurs, but the
next state of the first flip-flop(for MSD) is some function of the present state of other flip-flops
D. each flip-flop transfers its content to the next flip-flop, when a clock pulse occurs, but the
next state of the first flip-flop(for LSD) is some function of the present state of other flip-flops
E. each flip-flop transfers its content to the next flip-flop, when a clock pulse occurs, but the
next state of the last flip-flop(for LSD) is some function of the present state of other flip-flops

7. If Johnson counter has got 3 flip-flops, we can have sequence of _____ timing signals.
A. 3 B. 4 C. 5 D. 6 E.9

8. For what purpose is buffer used?

A. to reduce loading of the device to which the buffer is connected
B. to improve characteristics of the circuit C. to decrease propagation delay
D. to increase propagation delay E. all aforementioned answers are wrong

9. A flip-flop has a 10-ns delay from the time its CP input goes from 1 to 0 to the time the
output is complemented. What is the maximum frequency the counter can operate at reliably?
A. 5 MHz B. 6.25 MHz C. 8.33 MHz D. 10 MHz E. 12.5 MHz
A 4 A3 A2 A 1
10. The circuit below is a mod-_____ counter.
A. 1 B. 2 C. 3 D. 4 E. 5
count=1
load clear=1
CP

0 0 1 0

56
 LITERATURE

1. M. Morris Mano, Digital Logic and Computer Design, Prentice-Hall of India 2005
2. William Kleitz, Digital Electronics. A Practical Approach. Ninth Edition., Pearson
Education, Inc. 2012
3. Larissa A. Kiziyeva. Digital Design. Test Questions. SDU Almaty, 2002
4. Dr. Melik Şah Ertugrul, Larissa A. Kiziyeva. Digital Design.Lab works’ description.
SDU. Almaty, 2005
5. Dr. Melik Şah Ertugrul, Larissa A. Kiziyeva, Suliyev R., Circuit Technologies
Laboratory works description and test examples, SDU Almaty 2011
6. M.Morris Mano, Michael D. Ciletti, Digital Design (4th eddition), Prentice- Hall of
India 2008
7. Robert Boylestad, Louis Nashelsky, Electronic Devices and Circuit Theory, Prentice
Hall 2008
8. Zafer Karacan, Basic Electricity – experiment book, Yildirim Elektronic 2012
9. Zafer Karacan, Basic Electronics – experiment book, Yildirim Elektronic 2012
10. Zafer Karacan, Digital Electronics – experiment book, Yildirim Elektronic 2012

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