2024 IEEE International Students' Conference on Electrical, Electronics and Computer Science

Design of Full Adder Circuits with Optimized

Power and Speed Using CMOS Technique
2024 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS) | 979-8-3503-4846-0/24/$31.00 ©2024 IEEE | DOI: 10.1109/SCEECS61402.2024.10482060

Vishal Rajput Abhay Pratap Singh Sukeshni Tirkey

Department of electronics and Department of electronics and Department of electronics and
communication engineering communication engineering communication engineering
Maulana Azad National Institute of Maulana Azad National Institute of Maulana Azad National Institute of
Techonology Techonology Techonology
Bhopal,india Bhopal,india Bhopal,india
[email protected] [email protected] [email protected]

Dr. Sangeeta Nakhate

Department of electronics and
communication engineering
Maulana Azad National Institute of
Techonology
Bhopal,india
[email protected]

Abstract— Circuits for a 1-bit complete adder are Power reduction is very essential in VLSI circuit designing
proposed in this paper. The suggested circuits have very process, specially the reduction in power delay product (PDP)
low power consumption and minimal delay [1]. CMOS is very important for a good digital circuit and this can be
technology is used to develop various complete adder achieved by improving various parameters like width-to-
circuits with low power consumption and minimal delay. length (W/L) ratio. We always look for new designs while
Cadence Virtuoso at 90nm technology is used to designing VLSI (very larger scale technology) circuits
implement these, with a 1.8V supply voltage. The power because our main focus is to reduce area, power consumption
consumption [2], delay, and area parametric restrictions and delay, so that the performance of design will improve.
are compared with various complete adder circuit Although it is not possible to search any ideal design to
designs, and comments are made on which design achieve our targets and it is like never ending task. Our main
provides the best performance parameter. The Power focus is to maximize the performance while minimizing the
Delay Product indicates the circuit's efficiency. Since the resource consumption.
primary focus of VLSI research is low power design, One problem that we face is while designing VLSI circuits
create circuits with low power, little area, and little is that temperature of chips will increase as they work and
latency. The whole adder circuit design performance is hence cause more power consumption [1] this we can
related to the complete design performance. overcome with additional transistors. There are mainly two
types of power dissipation that is there in any circuit one is
Keywords— Full adder (FA), Cadence Virtuoso, Static power, static and another is dynamic. Static power dissipation [4], is
CMOS, Delay, Low Power, PDP, Dynamic power, PVT. there when transistor is off, the reverse current and
subthreshold current are the main causes of static power
Ⅰ. INTRODUCTION
dissipation. The source of power dissipation in the equation
Technology advancements have made circuit design more is as follows:
sophisticated, which means that designers are faced with
increasingly difficult VLSI difficulties, such as low power Pavg = Pleakage + PShort-circuit + Pswitching (1)
consumption [1], increased operating speed, and small space.
According to Moore's Law, the speed at which technology is Pswitching happens as a result of component switching. Short
developing has resulted in an exponential rise in the number circuit current is the cause of a short circuit. It results from
of transistors in VLSI circuits. VLSI engineers face difficult the simultaneous activation of NMOS and PMOS. This study
problems as a result of this expansion, including minimizing uses the Cadence Virtuoso tool to create two complete adder
chip space [2], increasing operating speed, and addressing circuits. The CMOS method at 90nm technology was used in
complicated issues like low power consumption. Designers the design of these adders. The traditional method of building
want to create more transistors per unit space while lowering a 1-bit complete adder circuit used 28 transistors, which
power consumption [3], since the number of transistors resulted in higher power dissipation, slower performance, and
doubles roughly every two years. a larger circuit footprint. Therefore, based on various

979-8-3503-4846-0/24/$31.00 ©2024 IEEE

performance parameters, the number of transistors is circuits have been proposed [3-6]. The circuit designs for
decreased to 22T and 14T [1]. XOR and XNOR gates using CMOS technology are shown
The creation of a one-bit full adder utilizing the CMOS in fig.2 and fig.3
technology is explained in Section IV. Schematic, output
waveform, and layout designs are the three components of a XOR GATE:
different complete adder design. The comparison between the
carry of complete adder circuits and the delay of the total is
presented in Section V. This section also includes a tabulation
of the PDP and power usage results. Section V concludes
which complete adder circuit type is appropriate for each
performance criterion based on the results.

IⅠ. REVIEW OF FULL ADDER CIRCUIT

Fig.2 Diagram for a XOR gate.
The purpose of a complete adder, a crucial digital circuit for
binary addition, is to calculate the total of three binary bits: XNOR GATE:
the carry bit from the previous stage (CIN), the addend (B),
and the augend (A). Full adders can calculate more complete
sums because they can handle the complexity of a third input,
whereas half adders can only handle two [5]. The carry from
the previous stage is represented by the third input, CIN. The
full adder produces a carry bit for the next step as well as the
sum of the three bits, or Carry-OUT. Because full adders can
handle many inputs, they are necessary for precise and
efficient binary addition circuits.
Fig.3 Diagram for XNOR gate.
A complete adder with the inputs A, B, and CIN and the
outputs S and Carry OUT is shown in the block diagram Fig.1.
ⅠV. CMOS TECHNOLOGY
The XOR and XNOR gates that we are going to use in our
design will be implemented by using CMOS. A CMOS is
circuit that is built by using NMOS and PMOS transistors in
series with each other [8]. It is possible to operate transistors
in the saturation or sub-threshold regions. The transistor will
be in the sub-threshold zone and the drain current (Id) will
drop when Vgs<Vt. This sub- threshold region is also called
Fig.1 Diagram for a full adder
weak inversion region, here in this region the input signal will
IIⅠ. REVIEW OF XOR AND XNOR CIRCUIT be greater than 0 but it will be less than the threshold voltage
(Vt) and when Vds > Vgs – Vt, the transistor will be the drain
Three XOR gate, one OR gate and two AND gates are current (Id) will increase when it is within the saturation zone
required to complete adder circuit, although we generally use [9]. Full adder circuits have been developed using the sub-
OR gate and AND gate in the circuit to implement adder not threshold area proposed in [2] with lengths of 22 and 14 times.
XOR/XNOR because XOR/XNOR gates take more power in Transistors are being operated in the Cadence Virtuoso's
the circuit. To implement XOR/XNOR gate we need four region 3, or sub-threshold area, in this instance. An NMOS
CMOS that means power requirement is more than in transistor functioning in the subthreshold region has the
AND/OR gate. As two XOR/XNOR gates used in adder so following equation [10] as mentioned:
power consumption is more therefore the main challenge is
to decrease the power consumption of the circuit, in order to
Ids = exp exp 1 1 exp
achieve good power efficiency in full adder we need to
optimize XOR/XNOR gates. we can decrease the power . (2)
consumption of full adder by optimization of XOR/XNOR
using smart design decision. The overall energy efficiency And for the NMOS transistor operating in saturation
can be raised of adder circuit, several times to implement a region, its current equation will be:
digital circuit. To create an XOR/XNOR gate, numerous Id = . (3)

SCEECS 2024
 A. 22T FULL ADDER: D. OUTPUT WAVEFORMS OF 22T:
In this design, a complete adder circuit is created at 90nm
technology using the CMOS process. 22 transistors total—11
NMOS and 11 PMOS—were utilized in this design. Two
additional NOT gates were needed during circuit design in
order to generate Abar, or the complement of A, and Cbar, or
the complement of C, which will be used as inputs in addition
to inputs A, B, and C. The XOR, XNOR, C, and Cbar signals
are utilized to form the output SUM signal. By using the Cbar
signal, we can minimize the capacitance at the nodes of XOR
and XNOR, which improves the driving capability of the
design and reduces power consumption [11, 12] and delay of
the circuit. We utilized XOR, XNOR, and C instead of Cbar
for the computation of CARRY [14]. A continuous supply of
1.8V was applied to the design during analysis. Fig. 6. 22T full adder output result and its waveforms

B. SCHEMATIC DESIGN OF 22T: E. FULL ADDER USING 14T:

The proposed full adder circuit is implemented on cadence

virtuoso tool on 90nm technology, which is having seven
NMOS and seven PMOS transistors [15, 16]. In 14T full
adder circuit, some of the transistor has full swing problem
[17]. To solve this problem, we added inverter after an XNOR
gate to make it an XOR gate. Using this modification, more
precise and reliable operation can be expected in the 90 nm
technology, while more improvement in the performance of
the circuit by reducing full swing issue. A 1-bit full adder
circuit is design by forming XOR and XNOR gates by using
the approach of Low Power Full Adder (LPFA). Steady
voltage of 1.8v is supplied at the time of analysis.

F. SCHEMATIC DESIGN OF 14T:

Fig. 4. 22T full adder schematic

C. TESTBENCH FOR 22T DESIGN:

Three Vpulse sources are used to create voltage waveforms that
are input to the A, B, and C terminals while constructing a
testbench for a circuit. These sources mimic dynamic input
conditions, making it possible to thoroughly test and confirm
the circuit's operation at different voltage levels.

Fig. 7 14T full adder schematic

G. TESTBENCH FOR 14T DESIGN:

The testbench design of the 14-transistor circuit uses three
Vpulse generators to generate dynamic voltage waveforms that
are inputs to the A, B, and C terminals. Through extensive
testing of the 14-transistor design under various input
conditions made possible by this simulation setup, reliable
performance verification and assessment in the Cadence
Virtuoso tool environment are ensured.
Fig. 5. 22T full adder circuit testbench

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 TABLE I. SUM DELAYS FOR INPUT A, B AND, C.

Sum Conventional Proposed

delays
22T 14T 22T 14T
A to Sum 55.4 153.2 48.21 142.2
B to Sum 54.4 156.2 46.44 143.12
C to Sum 84.83 12.5 75.82 7.4

TABLE II. CARRY DELAYS FOR INPUT A, B, AND C

Fig. 8 14T full adder circuit testbench
Carry Conventional Proposed
delays

H. OUTPUT WAVEFORMS OF 14T: 22T 14T 22T 14T

A to carry 16.13 184.1 10.12 165.22
B to carry 16.24 147.6 10.11 132.8
C to carry 61.48 13.42 50.32 7.4

C. Power consumption:

TABLE III. POWER CONSUMPTION

Average power

Full adder Conventional Proposed

22T 2.82mW 2.32mW
Fig. 9 14T full adder output results and its waveforms
14T 65.28μW 51.25μW

V. RESULTS D. POWER ANALYSIS:

The primary focal parameters in our digital circuit analysis The product of maximum delay and power dissipation is
are area minimization, power consumption, and either PDP. Optimal circuits are those with low power consumption
optimizing speed or decreasing delay. Based on this points (PDPs). Power dissipation and speed are
evaluation, our design has produced optimum results. fundamentally traded off, as described by the PDP. Another
Minimizing the area improves manufacturing efficiency; name for it is switching energy, and it is calculated by
minimizing the power consumption saves energy; and multiplying the input-output delay, or duration, D, by the
maximizing the speed ensures less delays. These findings power consumption P, averaged throughout the course of a
indicate a balanced and effective digital circuit design that switching event. What our proposed circuit yielded is what
satisfies the requirements of small footprint, low power follows:
consumption, and increased speed [5].
TABLE IV. POWER DELAY PRODUCT
A. Area:
Power delay product (pJ)
The number of transistors employed in the design determines Full adder type Conventional Proposed
the circuit's area. An increased number of transistors also 22T 0.240 0.175
means an increased need for room. The number of transistors
14T 0.012 0.084
for complete adder circuits are 14 and 22.

B. Delay:
VⅠ. CONCLUSION
The delay defines the speed of operation of circuits, if more
delay is there then speed will be less and if delay is less then A novel full adder has been designed for optimized power
speed will be more, the delay is mainly caused by the and high switching speed. The proposed full adder circuits
connecting wires and is known as transportation delay and the usage 22T and 14T, which shows better performance and
delay that is caused the change in output is known as inertial consumes very less power than conventional full adder
delay. Based on the latency of the total and carry from each circuits. The proposed circuits in this work has its own
input, Tables Nos. 2 and 3 compare several CMOS full adder advantage in terms of power consumption and delay. A 22T
circuits [18, 19]. full adder circuit have power reduction on 17.7% and in case

SCEECS 2024
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