SN65HVDA1040A-Q1

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EMC-OPTIMIZED HIGH SPEED CAN TRANSCEIVER

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1FEATURES APPLICATIONS
• Qualified for Automotive Applications • GMW3122 Dual-Wire CAN Physical Layer
• Meets or Exceeds the Requirements of • SAE J2284 High-Speed CAN for Automotive
ISO 11898-2 and -5 Applications
• GIFT/ICT Compliant • SAE J1939 Standard Data Bus Interface
• ISO 11783 Standard Data Bus Interface
• ESD Protection up to ±12 kV (Human-Body
Model) on Bus Pins • NMEA 2000 Standard Data Bus Interface
• Low-Current Standby Mode With Bus
DESCRIPTION
Wake-Up, <12 µA Max
• High Electromagnetic Compliance (EMC) The SN65HVDA1040A meets or exceeds the
specifications of the ISO 11898 standard for use in
• SPLIT Voltage Source for Common-Mode applications employing a Controller Area Network
Stabilization of Bus Via Split Termination (CAN). The device is qualified for use in automotive
• Digital Inputs Compatible with 3.3V and 5V applications. As a CAN transceiver, this device
Microprocessors provides differential transmit capability to the bus and
• Package Options: SOIC and VSON differential receive capability to a CAN controller at
signaling rates up to 1 megabit per second (Mbps) (1) .
• Protection Features
– Bus-Fault Protection of –27 V to 40 V
– TXD Dominant Time-Out
– Thermal Shutdown Protection
– Power-Up/Down Glitch-Free Bus Inputs and
Outputs
– High Bus Input Impedance With Low VCC
(1) The signaling rate of a line is the number of voltage
(Ideal Passive Behavior on Bus When transitions that are made per second, expressed in the units
Unpowered) bps (bits per second).

FUNCTIONAL BLOCK DIAGRAM

VCC
VCC
3 5 SPLIT
Dominant Temperature VCC/2
Time-Out Protection

1 Input
TXD Logic Driver
VCC
7 CANH

6
8 Standby Mode CANL
STB

4 Output
RXD MUX
Logic
Wake-Up
Filter

Standby Bus Monitor 2

and
Low-Power Receiver

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. © 2010–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

DESCRIPTION (CONTINUED)
The device is designed for operation in especially harsh environments and includes many device protection
features such as undervoltage lock out, over temperature thermal shutdown, wide common-mode range and loss
of ground protection. The bus pins are also protected against external cross-wiring, shorts to -27 V to 40 V and
voltage transients according to ISO 7637.

D PACKAGE DSJ PACKAGE

(TOP VIEW) (TOP VIEW)

TXD 1 8 STB
TXD STB
GND CANH
GND 2 7 CANH
VCC CANL
RXD SPLIT
VCC 3 6 CANL
NC NC
NC NC
RXD 4 5 SPLIT

TERMINAL FUNCTIONS
TERMINAL
SOIC VSON TYPE DESCRIPTION
NAME
NO. NO.
TXD 1 1 I CAN transmit data input (low for dominant bus state, high for recessive bus state)
GND 2 2 GND Ground connection
VCC 3 3 Supply Transceiver 5V supply voltage input
RXD 4 4 O CAN receive data output (low in dominant bus state, high in recessive bus state)
SPLIT 5 9 O Common mode stabilization output
CANL 6 10 I/O LOW-level CAN bus line
CANH 7 11 I/O HIGH-level CAN bus line
STB 8 12 I Standby mode select pin (active high)
NC NA 5, 6, 7, 8 NC No connect

ORDERING INFORMATION (1)

TA PACKAGE (2) ORDERABLE PART NUMBER TOP-SIDE MARKING
–40°C to 125°C SOIC – D Reel of 2500 SN65HVDA1040AQDRQ1 A1040A
–40°C to 125°C VSON – DSJ Reel of 3000 HVDA1040AQDSJRQ1 A1040A

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

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FUNCTIONAL DESCRIPTION

Operating Modes
The device has two main operating modes: normal mode and standby mode. Operating mode selection is made
via the STB input pin.

Table 1. Operating Modes

STB PIN MODE DRIVER RECEIVER RXD PIN
LOW NORMAL Enabled (On) Enabled (On) Mirrors CAN bus
Low-power wake-up receiver and bus Low = wake-up request received
HIGH STANDBY Disabled (Off)
monitor enabled (On) High = no wake-up request received

Bus States by Mode

The CAN bus has three valid states during powered operation depending on the mode of the device. In normal
mode the bus may be dominant (logic LOW) where the bus lines are driven differentially apart or recessive (logic
HIGH) where the bus lines are biased to VCC/2 via the high-ohmic internal input resistors RIN of the receiver. The
third state is low power standby mode where the bus lines will be biased to GND via the high-ohmic internal input
resistors RIN of the receiver.

CANH
Normal & Silent Mode Low Power
Standby Mode VCC/2 A
Typical Bus Voltage

RXD
CANH B

CANL
Vdiff

Vdiff
CANL A: Normal Mode
B: Low Power Standby Mode

Recessive Dominant Recessive Time, t

Figure 1. Bus States (Physical Bit Representation) Figure 2. Simplified Common Mode Bias and
Receiver Implementation

Normal Mode
This is the normal operating mode of the device. It is selected by setting STB low. The CAN driver and receiver
are fully operational and CAN communication is bi-directional. The driver is translating a digital input on TXD to a
differential output on CANH and CANL. The receiver is translating the differential signal from CANH and CANL to
a digital output on RXD. In recessive state the bus pins are biased to 0.5 × VCC. In dominant state the bus pins
(CANH and CANL) are driven differentially apart. Logic high is equivalent to recessive on the bus and logic low is
equivalent to a dominant (differential) signal on the bus.
The SPLIT pin is biased to 0.5 × VCC for bus common mode bus voltage bias stabilization in split termination
network applications (see application information).

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Standby Mode and RXD Wake-Up Request

This is the low power mode of the device. It is selected by setting STB high. The CAN driver and main receiver
are turned off and bi-directional CAN communication is not possible. The low power receiver and bus monitor are
enabled to allow for wake up requests via the bus. A wake up request will be output to RXD (driven low) for any
dominant bus transmissions longer than the filter time tBUS. The local protocol controller (MCU) should monitor
RXD for transitions and then reactivate the device to normal mode based on the wake up request. The CAN bus
pins are weakly pulled to GND and the SPLIT pin is off (floating).

STB Low Power Standby Mode, STB = high

Bus VDiff

<tBUS <tBUS tBUS tBUS <tBUS tBUS

RXD

Figure 3. Standby Mode Low Power Receiver and Bus Monitor Behavior

Driver and Receiver Function Tables

Table 2. Driver Function Table (1)

INPUTS OUTPUTS
BUS STATE
TXD STB CANH CANL
L L H L Dominant
H L Z Z Recessive
Open L Z Z Recessive
X H or Open Y Y Recessive

(1) H = high level, L = low level, X = irrelevant, Y = weak pull down to GND, ? = indeterminate, Z = high
impedance

Table 3. Receiver Function Table

DIFFERENTIAL INPUTS OUTPUT
STB BUS STATE
VID = V(CANH) – V(CANL) RXD
VID ≥ 0.9 V L L Dominant
VID ≥ 1.15 V H or Open L Dominant
0.5 V < VID < 0.9 V X ? ?
VID ≤ 0.5 V X H Recessive
Open X H Recessive

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Protection Features

TXD Dominant State Timeout

During normal mode (only mode where CAN driver is active) the TXD dominant time-out circuit prevents the
transceiver from blocking network communication in event of a hardware or software failure where TXD is held
dominant longer than the time out period tDST. The dominant time out circuit is triggered by a falling edge on
TXD. If no rising edge is seen before the time-out constant of the circuit expires (tDST) the CAN bus driver is
disabled freeing the bus for communication between other network nodes. The CAN driver is re-activated when a
recessive signal is seen on TXD pin, thus clearing the dominant state time out. The CAN bus pins will be biased
to recessive level during a TXD dominant state time-out and SPLIT will remain on.
APPLICATION NOTE: The maximum dominant TXD time allowed by the TXD Dominant state time out limits the
minimum possible data rate of the device. The CAN protocol allows a maximum of eleven successive dominant
bits (on TXD) for the worst case, where five successive dominant bits are followed immediately by an error
frame. This, along with the t(dom) minimum, limits the minimum bit rate. The minimum bit rate may be calculated
by:
Minimum Bit Rate = 11/t(dom)

Thermal Shutdown
If the junction temperature of the device exceeds the thermal shut down threshold the device will turn off the
CAN driver circuits, including SPLIT pin. This condition is cleared once the temperature drops below the thermal
shut down temperature of the device.

Undervoltage Lockout / Unpowered Device

The device has undervoltage detection and lockout on the VCC supply. If an undervoltage condition is detected
on VCC, the device protects the bus.
The TXD pin is pulled up to VCC to force a recessive input level if the pin floats. The STB is pulled up to VCC to
force the device in standby mode (low power) if the pin floats.
The bus pins (CANH, CANL, and SPLIT) all have extremely low leakage currents when the device is un-powered
so it will not load down the bus but be an “ideal passive” load to the bus. This is critical, especially if some nodes
of the network will be unpowered while the rest of the network remains in operation.

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Application Hints

Using With 3.3-V Microcontrollers

The input level threshold for the digital input pins of this device are 3.3V compatible, however a few application
considerations must be taken if using this device with 3.3-V microcontrollers. Both TXD and STB input pins have
internal pull up sources to VCC. Some microcontroller vendors recommend using an open drain configuration on
their I/O pins in this case even though the pullup limits the current. As such care must be taken at the application
level that TXD and STB have sufficient pull up to meet system timing requirements for CAN. The internal pullup
on TXD especially may not be sufficient to overcome the parasitic capacitances and allow for adequate CAN
timing; thus, an additional external pullup may be required. Care should also be taken with the RXD pin of the
microcontroller as this device's RXD output drives the full VCC range (5 V). If the microcontroller RXD input pin is
not 5-V tolerant, this must be addressed at the application level. Other options include using a CAN transceiver
from Texas Instruments with I/O level adapting or a 3.3-V CAN transceiver.

Using SPLIT With Split Termination

The SPLIT pin voltage output provides 0.5 × VCC in normal mode. The circuit may be used by the application to
stabilized the common-mode voltage of the bus by connecting it to the center tap of split termination for the CAN
network (see Figure 17 and Figure 4). This pin provides a stabilizing recessive voltage drive to offset leakage
currents of un-powered transceivers or other bias imbalances that might bring the network common mode
voltage away from 0.5 × VCC. Utilizing this feature in a CAN network improves electromagnetic emissions
behavior of the network by eliminating fluctuations in the bus common mode voltage levels at the start of
message transmissions.
VCC

SN65HVDA1040A 3
CANH
7

VSPLIT = ½VCC in normal mode, 5 SPLIT

floating in other modes

CANL
6
2
GND

Figure 4. Split Pin Stabilization Circuitry and Application

PCB and Thermal Considerations for VSON Package

The VSON package verson of this device has an exposed thermal pad which should be connected with vias to a
thermal plane. Even though this pad is not electrically connected internally it is recommended that the exposed
pad be connected to the GND plane. Please refer to the mechanical information on the package at the end of
this datasheet and application report SLUA271 "QFN/SON PCB Attachement" for more information on proper
use of this package.

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ABSOLUTE MAXIMUM RATINGS (1) (2)

1.1 VCC Supply voltage range –0.3 V to 6 V
1.2 Voltage range at bus terminals (CANH, CANL, SPLIT) –27 V to 40 V
1.3 IO Receiver output current 20 mA
1.4 VI Voltage input range, ISO 7637 transient pulse (3) (CANH, CANL) –150 V to 100 V
1.5 VI Voltage input range (TXD, STB) –0.3 V to 6 V
1.6 TJ Junction temperature range –40°C to 150°C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with ISO 7637 test pulses 1, 2, 3a, 3b per IBEE system level test (Pulse 1 = –100 V, Pulse 2 = 100 V, Pulse
3a = –150 V, Pulse 3b = 100 V). If dc may be coupled with ac transients, externally protect the bus pins within the absolute maximum
voltage range at any bus terminal. This device has been tested with dc bus shorts to +40 V with leading common-mode chokes. If
common-mode chokes are used in the system and the bus lines may be shorted to dc, ensure that the choke type and value in
combination with the node termination and shorting voltage either will not create inductive flyback outside of voltage maximum
specification or use an external transient-suppression circuit to protect the transceiver from the inductive transients.

ELECTROSTATIC DISCHARGE PROTECTION

PARAMETER TEST CONDITIONS VALUE
2.1 CANH and CANL (3) ±12 kV
(2) (4)
2.2 Human-Body Model SPLIT ±10 kV
2.3 All pins ±4 kV
2.4 Electrostatic discharge (1) Charged-Device Model (5) All pins ±1.5 kV
2.5 Machine Model (6) ±200 V
IEC 61000-4-2 according to IBEE
2.6 CANH and CANL pins to GND ±7 kV
CAN EMC test specification

(1) All typical values at 25°C.

(2) Tested in accordance JEDEC Standard 22 Test Method A114F and AEC-Q100-002.
(3) Test method based upon JEDEC Standard 22 Test Method A114F and AEC-Q100-002, CANH and CANL bus pins stressed with
respect to each other and GND.
(4) Test method based upon JEDEC Standard 22 Test Method A114F and AEC-Q100-002, SPLIT pin stressed with respect to GND.
(5) Tested in accordance JEDEC Standard 22 Test Method C101D and AEC-Q100-011.
(6) Tested in accordance JEDEC Standard 22 Test Method A115A and AEC-Q100-003.

RECOMMENDED OPERATING CONDITIONS

MIN MAX UNIT
3.1 VCC Supply voltage 4.75 5.25 V
3.2 VI or VIC Voltage at any bus terminal (separately or common mode) –12 12 V
3.3 VIH High-level input voltage TXD, STB 2 5.25 V
3.4 VIL Low-level input voltage TXD, STB 0 0.8 V
3.5 VID Differential input voltage –6 6 V
3.6 Driver –70
IOH High-level output current mA
3.7 Receiver (RXD) –2
3.8 Driver 70
IOL Low-level output current mA
3.9 Receiver (RXD) 2
3.10 TA Operating free-air temperature range See Thermal Characteristics table –40 125 °C

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ELECTRICAL CHARACTERISTICS
over recommended operating conditions including operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT
Supply
4.1 Standby mode STB at VCC, VI = VCC 6 12 µA
4.2 ICC 5-V supply current Dominant VI = 0 V, 60-Ω load, STB at 0 V 50 70
mA
4.3 Recessive VI = VCC, No load, STB at 0 V 6 10
4.4 UVVCC Undervoltage reset threshold 2.8 4.0 V
Device Switching Characteristics
Total loop delay, driver input to receiver output,
5.1 td(LOOP1) STB at 0 V, See Figure 12 90 230 ns
recessive to dominant
Total loop delay, driver input to receiver output,
5.2 td(LOOP2) STB at 0 V, See Figure 12 90 230 ns
dominant to recessive
Driver
6.1 Bus output voltage CANH VI = 0 V, STB at 0 V, RL = 60 Ω, 2.9 3.4 4.5
VO(D) V
6.2 (dominant) CANL See Figure 5 and Figure 1 0.8 1.75
VI = 3 V, STB at 0 V, RL = 60 Ω,
6.3 VO(R) Bus output voltage (recessive) 2 2.5 3 V
See Figure 5 and Figure 1
STB at Vcc, RL = 60 Ω,
6.4 VO Bus output voltage (standby mode) –0.1 0.1 V
See Figure 5 and Figure 1
VI = 0 V, RL = 60 Ω, STB at 0 V,
6.5 1.5 3 V
See Figure 5, Figure 1, and Figure 6
VOD(D) Differential output voltage (dominant)
VI = 0 V, RL = 45 Ω, STB at 0 V,
6.6 1.4 3
See Figure 5, Figure 1, and Figure 6
VI = 3 V, STB at 0 V, RL = 60 Ω,
6.7 –0.012 0.012 V
VOD(R) Differential output voltage (recessive) See Figure 5 and Figure 1
6.8 VI = 3 V, STB at 0 V, No load –0.5 0.05
Output symmetry (dominant or recessive)
6.9 VSYM STB at 0 V, RL = 60 Ω, See Figure 16 0.9 VCC VCC 1.1 VCC V
(VO(CANH) + VO(CANL))
6.10 VOC(ss) Steady-state common-mode output voltage STB at 0 V, RL = 60 Ω, See Figure 11 2 2.5 3 V
Change in steady-state common-mode output
6.11 ΔVOC(ss) STB at 0 V, RL = 60 Ω, See Figure 11 30 mV
voltage
6.12 VIH High-level input voltage, TXD input 2 V
6.13 VIL Low-level input voltage, TXD input 0.8 V
6.14 IIH High-level input current, TXD input VI at VCC –2 2 µA
6.15 IIL Low-level input current, TXD input VI at 0 V –50 –10 µA
6.16 IO(off) Power-off TXD output current VCC at 0 V, TXD at 5 V 1 µA
VCANH = –12 V, CANL open, TXD = low,
6.17 –120 –85
See Figure 14
VCANH = 12 V, CANL open, TXD = low,
6.18 0.4 1
See Figure 14
VCANL = –12 V, CANH open, TXD = low,
6.19 –1 –0.6
Short-circuit steady-state output current, See Figure 14
IOS(ss) mA
Dominant VCANL = 12 V, CANH open, TXD = low,
6.20 75 120
See Figure 14
VCANH = 0 V, CANL open, TXD = low,
6.21 -100 -75
See Figure 14
VCANL = 32 V, CANH open, , TXD = low,
6.22 75 125
See Figure 14
-20 V ≤ VCANH ≤ 32 V, CANL open,
6.23 -10 10
Short-circuit steady-state output current, TXD = high, See Figure 14
IOS(ss) mA
Recessive -20 V ≤ VCANL ≤ 32 V, CANH open,
6.24 -10 10
TXD = high, See Figure 14
6.25 CO Output capacitance See receiver input capacitance

(1) All typical values are at 25°C with a 5-V supply.

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ELECTRICAL CHARACTERISTICS (continued)

over recommended operating conditions including operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT
Driver Switching Characteristics
7.1 tPLH Propagation delay time, low-to-high level output STB at 0 V, See Figure 7 25 65 120 ns
7.2 tPHL Propagation delay time, high-to-low level output STB at 0 V, See Figure 7 25 45 120 ns
7.3 tr Differential output signal rise time STB at 0 V, See Figure 7 25 ns
7.4 tf Differential output signal fall time STB at 0 V, See Figure 7 45 ns
Enable time from standby mode to normal mode
7.5 ten See Figure 10 10 µs
and transmission of dominant
7.6 t(dom) Dominant time out (2) ↓VI, See Figure 13 300 450 700 µs
Receiver
Positive-going input threshold voltage, high-speed
8.1 VIT+ STB at 0 V, See Table 4 800 900 mV
mode
Negative-going input threshold voltage,
8.2 VIT– STB at 0 V, See Table 4 500 650 mV
high-speed mode
8.3 Vhys Hysteresis voltage (VIT+ – VIT–) 100 125 mV
8.4 VIT Input threshold voltage, standby mode STB at VCC 500 1150 mV
8.5 VOH High-level output voltage IO = –2 mA, See Figure 9 4 4.6 V
8.6 VOL Low-level output voltage IO = 2 mA, See Figure 9 0.2 0.4 V
Power-off bus input current (unpowered bus CANH = CANL = 5 V,
8.7 II(off) 3 µA
leakage current) VCC at 0 V, TXD at 0 V
8.8 IO(off) Power-off RXD leakage current VCC at 0 V, RXD at 5 V 20 µA
TXD at 3 V,
8.9 CI Input capacitance to ground (CANH or CANL) 13 pF
VI = 0.4 sin (4E6πt) + 2.5 V
8.10 CID Differential input capacitance TXD at 3 V, VI = 0.4 sin (4E6πt) 6 pF
8.11 RID Differential input resistance TXD at 3 V, STB at 0 V 30 80 kΩ
8.12 RIN Input resistance (CANH or CANL) TXD at 3 V, STB at 0 V 15 30 40 kΩ
Input resistance matching
8.13 RI(m) V(CANH) = V(CANL) –3 0 3 %
[1 – (RIN (CANH) / RIN (CANL))] × 100%
Receiver Switching Characteristics
9.1 tPLH Propagation delay time, low-to-high-level output STB at 0 V , See Figure 9 60 90 130 ns
9.2 tPHL Propagation delay time, high-to-low-level output STB at 0 V , See Figure 9 45 70 130 ns
9.3 tr Output signal rise time STB at 0 V , See Figure 9 8 ns
9.4 tf Output signal fall time STB at 0 V , See Figure 9 8 ns
Dominant time required on bus for wake-up from
9.5 tBUS STB at VCC, See Figure 15 1.5 5 µs
standby
STB Pin
10.1 VIH High-level input voltage, STB input 2 V
10.2 VIL Low-level input voltage, STB input 0.8 V
10.3 IIH High-level input current STB at 2 V –10 0 µA
10.4 IIL Low-level input current STB at 0.8 V –10 0 µA
SPLIT Pin
11.1 VO Output voltage –500 µA < IO < 500 µA 0.3 VCC 0.5 VCC 0.7 VCC V
11.2 IO(stb) Leakage current, standby mode STB at 2 V, –12 V ≤ VO ≤ 12 V –5 5 µA

(2) The TXD dominant time out (t(dom)) disables the driver of the transceiver once the TXD has been dominant longer than t(dom), which
releases the bus lines to recessive, preventing a local failure from locking the bus dominant. The driver may only transmit dominant
again after TXD has been returned HIGH (recessive). While this protects the bus from local faults, locking the bus dominant, it limits the
minimum data rate possible. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the worst case,
where five successive dominant bits are followed immediately by an error frame. This, along with the t(dom) minimum, limits the minimum
bit rate. The minimum bit rate may be calculated by:
Minimum Bit Rate = 11/ t(dom) = 11 bits / 300 µs = 37 kbps

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THERMAL CHARACTERISTICS
over recommended operating conditions, TA = –40°C to 125°C (unless otherwise noted)
THERMAL METRIC (1) TEST CONDITIONS MIN TYP MAX UNIT
THERMAL METRIC - SOIC 'D' PACKAGE
12.1-D Junction-to-air thermal Low-K thermal resistance (3) 140
θJA
12.2-D resistance (2) High-K thermal resistance (4) 112
Junction-to-board thermal
12.3-D θJB 50
resistance (5)
Junction-to-case (top) thermal
12.4-D θJC(TOP) 56
resistance (6)
°C/W
Junction-to-case (bottom)
12.5-D θJC(BOTTOM) NA
thermal resistance (7)
Junction-to-top
12.6-D ΨJT 13
characterization parameter (8)
Junction-to-board
12.7-D ΨJB 55
characterization parameter (9)
THERMAL METRIC - VSON 'DSJ' PACKAGE
12.1-DSJ Junction-to-air thermal Low-K thermal resistance (3) 290
θJA
12.2-DSJ resistance (2) High-K thermal resistance (4)
52
Junction-to-board thermal
12.3-DSJ θJB 14
resistance (5)
Junction-to-case (top) thermal
12.4-DSJ θJC(TOP) 56
resistance (6)
°C/W
Junction-to-case (bottom)
12.5-DSJ θJC(BOTTOM) 4.5
thermal resistance (7)
Junction-to-top
12.6-DSJ ΨJT 6
characterization parameter (8)
Junction-to-board
12.7-DSJ ΨJB 19
characterization parameter (9)
AVERAGE POWER DISSIPATION AND THERMAL SHUTDOWN
VCC = 5 V, TJ = 27°C, RL = 60 Ω, STB at 0 V,
12.5 Input to TXD at 500 kHz, 50% duty cycle 112
square wave, CL at RXD = 15 pF
PD Average power dissipation VCC = 5.5 V, TJ = 130°C, RL = 45 Ω, STB at mW
0 V,
12.6 170
Input to TXD at 500 kHz, 50% duty cycle
square wave, CL at RXD = 15 pF
Thermal shutdown
12.7 185 °C
temperature

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction temperature (TJ) is calculated using the following TJ = TA + (PD × θJA). θJAis PCB dependent, both JEDEC-standard Low-K
and High-K values are given as reference points to standardized reference boards.
(3) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, Low-K board, as
specified in JESD51-3, in an environment described in JESD51-2a.
(4) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(5) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(6) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(8) The junction-to-top characterization parameter, ΨJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(9) The junction-to-board characterization parameter, ΨJB estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).

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 SN65HVDA1040A-Q1
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PARAMETER MEASUREMENT INFORMATION

IO(CANH)

TXD VO (CANH)
II RL
VOD
VO(CANH) + VO(CANL)
2
STB I I(S)
VI VOC
+ I O(CANL)
VI(S) V O(CANL)
_

Figure 5. Driver Voltage, Current, and Test Definition

330 W ±1%
CANH

TXD
0V VOD RL
+
_ –2 V £ VTEST £ 7 V
STB
CANL
330 W ±1%

Figure 6. Driver VOD Test Circuit

CANH
VCC
VI
VCC/2 VCC/2

TXD 0V
RL = 60 W VO
±1% tPLH tPHL
CL = 100 pF VO(D)
VI 90%
0.9 V
VO 0.5 V
STB 10%
VO(R)
CANL tr tf

Figure 7. Driver Test Circuit and Voltage Waveforms

CANH
VI (CANH) RXD
IO
VID
V + VI (CANL)
VIC = I (CANH)
2
VO
VI (CANL) CANL

Figure 8. Receiver Voltage and Current Definitions

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PARAMETER MEASUREMENT INFORMATION (continued)

CANH 3.5 V
VI 2V 2.4 V
RXD IO
VI 1.5 V
tPLH tPHL
CANL VOH
(See Note A) 1.5 V CL = 15 pF ±20% 90% 0.75 VCC
VO
STB (See Note B) VO 0.25 VCC
10% VOL
tr tf

A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle,
tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
B. CL includes instrumentation and fixture capacitance within ±20%.

Figure 9. Receiver Test Circuit and Voltage Waveforms

Table 4. Differential Input Voltage Threshold Test

INPUT OUTPUT
VCANH VCANL |VID| R
–11.1 V –12 V 900 mV L
12 V 11.1 V 900 mV L
VOL
–6 V –12 V 6V L
12 V 6V 6V L
–11.5 V –12 V 500 mV H
12 V 11.5 V 500 mV H
–12 V –6 V 6V H VOH
6V 12 V 6V H
Open Open X H

DUT

CANH VCC
(B)
TXD (A) 60 W VI 0.5 VCC
0V CL
±1% 0V

STB CANL
VI VOH

VO 0.5 VCC
RXD VOL
ten
+
VO
_ 15 pF ± 20%

A. CL = 100 pF and includes instrumentation and fixture capacitance within ±20%.

B. All VI input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 6 ns,
pulse repetition rate (PRR) = 125 kHz, 50% duty cycle.

Figure 10. ten Test Circuit and Waveforms

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CANH

TXD
VI RL VO(CANH) + VO(CANL) VOC(SS)
VOC =
2
VOC
STB CANL VO(CANH)
VO(CANL)

NOTE: All VI input pulses are from 0 V to VCC and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns,
pulse repetition rate (PRR) = 125 kHz, 50% duty cycle.

Figure 11. Common-Mode Output Voltage Test and Waveforms

DUT

CANH VCC
TXD Input 0.5 VCC
(B) TXD 60 W
VI CL
(A)
0V
±1%
tloop2 tloop1

STB CANL VOH

0.5 VCC 0.5 VCC
RXD Output
RXD VOL

VO
_ 15 pF ±20%

A. CL = 100 pF and includes instrumentation and fixture capacitance within ±20%.

B. All VI input pulses are from 0 V to VCC and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns,
pulse repetition rate (PRR) = 125 kHz, 50% duty cycle.

Figure 12. t(LOOP) Test Circuit and Waveforms

CANH
VCC
VI
TXD
RL = 60 W CL
(B)
VOD 0V
±1%
VOD(D)
VI (A)
VOD
900 mV
STB 500 mV
CANL 0V
tdom

A. All VI input pulses are from 0 V to VCC and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns,
pulse repetition rate (PRR) = 500 Hz, 50% duty cycle.
B. CL = 100 pF includes instrumentation and fixture capacitance within ±20%.

Figure 13. Dominant Time-Out Test Circuit and Waveforms

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SN65HVDA1040A-Q1
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Figure 14. Driver Short-Circuit Current Test and Waveforms

VCC 3.5 V
CANH
STB VI 2.65 V
IO
VI RXD
1.5 V
(see Note A) 0.7 µs tBUS
CANL CL
1.5 V VO VOH
(see Note B)
VO 400 mV
VOL
A. For VI bit width ≤ 0.7 µs, VO = VOH. For VI bit width ≥ 5 µs, VO = VOL. VI input pulses are supplied from a generator
with the following characteristics: tr/tf < 6 ns.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.

Figure 15. tBUS Test Circuit and Waveforms

CANH

TXD
VI RL
VSYM = VO(CANH) + VO(CANL)

STB CANL VO(CANH)

VO(CANL)

A. All VI input pulses are from 0 V to VCC and supplied by a generator having the following characteristics: tr/tf ≤ 6 ns,
pulse repetition rate (PRR) = 250 kHz, 50% duty cycle.

Figure 16. Driver Output Symmetry Test Circuit

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Equivalent Input and Output Schematic Diagrams

TXD Input RXD Output

VCC
VCC

4.3 kW 15 W
Input Output

6V 6V

CANH Input CANL Input

VCC VCC

10 kW 10 kW
20 kW 20 kW
Input Input

10 kW 10 kW
40 V
40 V

STB Input CANH and CANL Outputs

VCC
VCC

CANH
4.3 kW
Input CANL

6V 40 V 40 V

SPLIT Output
VCC

2 kW

Output
2 kW
40 V

© 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 15

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SN65HVDA1040A-Q1
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APPLICATION INFORMATION
VBATTERY

VSUP VCC
VCC
Vreg
VCC 3 CANH
(e.g., TPSxxxx) 7
STB
Port x 8
SN65HVDA1040A
CAN Transceiver
MCU SPLIT
(e.g., TMS470) 5

RXD
RXD 4
TXD CANL
TXD 1 6
2
GND

Figure 17. Typical Application Using Split Termination for Stabilization

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 PACKAGE OPTION ADDENDUM

www.ti.com 9-Feb-2011

PACKAGING INFORMATION

Orderable Device Status

(1) Package Type Package Pins Package Qty Eco Plan
(2) Lead/ MSL Peak Temp
(3) Samples
Drawing Ball Finish (Requires Login)
HVDA1040AQDSJRQ1 ACTIVE VSON DSJ 12 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR
& no Sb/Br)
SN65HVDA1040AQDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
HVDA1040AQDSJRQ1 VSON DSJ 12 3000 330.0 12.4 3.3 4.3 1.1 8.0 12.0 Q1
SN65HVDA1040AQDRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
HVDA1040AQDSJRQ1 VSON DSJ 12 3000 367.0 367.0 35.0
SN65HVDA1040AQDRQ1 SOIC D 8 2500 367.0 367.0 35.0

Pack Materials-Page 2
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