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Exp 2

The document is a lab report detailing the design and implementation of various arithmetic circuits on FPGA, including full adders, a 4-bit full adder, and circuits for addition and subtraction using mode control. It provides code examples using different programming constructs such as if-else statements, case statements, and structural modeling. Additionally, it includes designs for multiplexers and decoders with corresponding code implementations.

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Khelan Mehta
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9 views12 pages

Exp 2

The document is a lab report detailing the design and implementation of various arithmetic circuits on FPGA, including full adders, a 4-bit full adder, and circuits for addition and subtraction using mode control. It provides code examples using different programming constructs such as if-else statements, case statements, and structural modeling. Additionally, it includes designs for multiplexers and decoders with corresponding code implementations.

Uploaded by

Khelan Mehta
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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EXPERIMENT-2 LAB REPORT

KHUSHI OJHA 23BEC089


To design and implement arithmetic circuits on FPGA.

1) Full adder by If-Else :-


Code :-
module exp2 (a,b,cin,sum,cout);
input a,b,cin; output reg cout,sum;
always @(*) begin
if (a==0 && b==0 && cin==0)
begin sum=0;
cout=0;
end
else if (a==0 && b==0 && cin==1)
begin sum=1;
cout=0;
end
else if (a==0 && b==1 && cin==0)
begin
sum=1; cout=0;
end
else if (a==0 && b==1 && cin==1)
begin
sum=0; cout=1;
end
else if (a==1 && b==0 && cin==0)
begin
sum=1; cout=0;
end
else if (a==1 && b==0 && cin==1)
begin sum=0;
cout=1;
end
else if (a==1 && b==1 && cin==0)
begin sum=0; cout=1;
end
else
begin
sum=1; cout=1;
end
end
endmodule
RTL:

TTL:

2) Full adder by case statement :-


module exp2(input a,b,cin, output reg cout,sum);
always @(*) begin
case ({a,b,cin}) 3'b000 :
begin sum = 1'b0; cout = 1'b0;
end
3'b001 , 3'b010 , 3'b100 :
begin sum = 1'b1; cout = 1'b0;
end 3'b011 , 3'b101 , 3'b110 :
begin sum = 1'b0; cout = 1'b1;
end 3'b111 :
begin sum = 1'b1; cout = 1'b1;
end
endcase
end
endmodule

RTL:

TTL:

3) 4 bit full adder using structural modelling :-

CODE:
module exp2( A,B,Cin,sum,Cout);
input [3:0]A,B; input Cin; output [3:0]sum; output Cout;
wire x0,x1,x2;
fulladder abc0 (A[0],B[0],Cin,sum[0],x0);
fulladder abc1 (A[1],B[1],x0,sum[1],x1);
fulladder abc2 (A[2],B[2],x1,sum[2],x2);
fulladder (A[3],B[3],x2,sum[3],Cout);
endmodule
module fulladder(input a,b,c,output s,co);
assign s = a^b^c;
assign co = (c&(a^b)) | (a&b);
endmodule

RTL:

TTL:

4) Modify the code that can perform Addition and Subtraction operation using a ‘Mode
Control Switch’:
CODE:
module exp2(input a,b,cin,mode,output reg sum,cout,sub,bout);
always @ (*) begin
sum=0;
sub=0;
cout=0;
bout=0;
case (mode) 0:
begin
sum = a ^b ^cin; cout = (a&b) | (cin&(a^b));
end
1: begin
sub = a ^b ^cin; bout = ((~a)&b) | (cin&(~(a^b)));
end
endcase
end
endmodule
RTL:

TTL:

5) Full adder - Subtractor Mode control by structural modelling.

CODE:
module exp2( A,B,Cin,m,sum,Cout);
input [3:0]A,B; input Cin,m; output [3:0]sum; output Cout;
wire x0,x1,x2;
fulladder abc0 (A[0],B[0]^m,Cin,sum[0],x0);
fulladder abc1 (A[1],B[1]^m,x0,sum[1],x1);
fulladder abc2 (A[2],B[2]^m,x1,sum[2],x2);
fulladder abc3(A[3],B[3]^m,x2,sum[3],Cout);
endmodule
module fulladder (input a,b,c,output s,co);
assign s = a^b^c;
assign co = (c&(a^b)) | (a&b);
endmodule

RTL:
TTL:

6) Multiplexer using if-else :-


CODE:
module exp2(in,sel,out); input [3:0] in; input [1:0] sel; output reg out;
always @(*) begin
if (sel == 2'b00) out = in[0];
else if (sel == 2'b01) out = in[1];
else if (sel == 2'b10) out = in[2];
else if (sel == 2'b11) out = in[3];
else out = 1'b0;
end
endmodule

RTL:

TTL:
7) Multiplexer using Case statement :-
module exp2(input [3:0]in , input [1:0]sel , output reg out);
always @(*) begin
case(sel)
2'b00 : out = in[0];
2'b01 : out = in[1];
2'b10 : out = in[2];
2'b11 : out = in[3];
default : out = 1'b0;
endcase
end
endmodule

RTL:

TTL:

8) Multiplexer using nested if statement :-


CODE:
module exp2(input s0,s1,s2,s3,a,b,output reg m);
always@(*)begin
if (a==0)
begin
if (b==a) m=s0;
else m=s1;
end
else
begin
if (b==a) m=s3;
else m=s2;
end
end
endmodule

RTL:

TTL:

9) Decoder using if-else statement :-


module exp2(input [1:0]in , output reg [3:0]out);
always @(*) begin
if (in==2'b00)
endmodule
out = 4'b0001;
else if (in==2'b01)
out = 4'b0010;
else if (in==2'b10) out = 4'b0100;
else if (in==2'b11) out = 4'b1000;
else out = 1'bxxxx;
end

RTL:

TTL:

10) Decoder using Case statement :-

CODE:
module exp2 (input [1:0]in , output reg [3:0]out );
always @(*) begin
case (in)
endmodule

2'b00 : out = 4'b0001;


2'b01 : out = 4'b0010;
2'b10 : out = 4'b0100;
2'b11 : out = 4'b1000;

default : out = 4'bxxxx;


endcase
end
RTL:

TTL:

11) Decoder using nested if :-


CODE:
module exp2 (input i0,i1,output reg a,b,c,d);
always@(*)begin
if(i0==0)
begin
if(i0==i1)
begin
a=1; b=0; c=0; d=0;
end
else
begin
a=0; b=1; c=0; d=0;
end
end
else
begin
if(i0==i1)
begin
a=0; b=0; c=0; d=1;
end
else
begin a=0; b=0; c=1; d=0;
end
end
end
endmodule

RTL:

TTL:

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