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Exp1 23bec089

The document presents an FPGA report by Khushi Ojha, detailing the implementation of various logic gates including XOR, XNOR, and data-flow modeling using Verilog code. It includes code snippets for each gate, along with sections for RTL and TTL views, although the output sections are not filled in. Additionally, it discusses behavioral modeling with examples of code for different logic operations.

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Khelan Mehta
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5 views9 pages

Exp1 23bec089

The document presents an FPGA report by Khushi Ojha, detailing the implementation of various logic gates including XOR, XNOR, and data-flow modeling using Verilog code. It includes code snippets for each gate, along with sections for RTL and TTL views, although the output sections are not filled in. Additionally, it discusses behavioral modeling with examples of code for different logic operations.

Uploaded by

Khelan Mehta
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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EXPERIMENT- 1 FPGA REPORT

KHUSHI OJHA
23BEC089

1. XOR gate:
Code:
module lab1 (a,b,y);
input a,b;
output y;
//xor gate
wire w1,w2;
and_gate ag1(~a,~b,w1);
and_gate ag2(a,b,w2);
or_gate og1(w1,w2,y);
endmodule
module or_gate(a,b,y);
input a,b;
output y;
//or gate
or(y,a,b);
endmodule
module and_gate(a,b,y);
input a,b;
output y;
//and gate
and(y,a,b);
endmodule
OBSERVATION OF DATA AFTER CODE EXECUTION:

RTL VIEW:

TTL VIEW:
2. XNOR gate:
Code:
module lab1 (a,b,y);
input a,b;
output y;
wire w1,w2;
and_gate ag1(~a,~b,w1);
and_gate ag2(a,b,w2);
or_gate og1(w1,w2,y);
endmodule
module or_gate(a,b,y);
input a,b;
output y;
//or gate
or(y,a,b);
endmodule
module and_gate(a,b,y);
input a,b;
output y;
//and gate
and(y,a,b);
endmodule

OUTPUT:
RTL VIEW:

TTL VIEW:
3)DATA-FLOW MODELING:
Code:

module lab1 (a,b,c,d,e,f,g,h1);

input a,b;

output c,e,f,g,h1,d;

assign c = (a | b);

assign h = (a & b);

assign e = ~(a | b);

assign f = ~(a & b);

assign g = (a & b) | (~a & ~b);

assign h1 = (~a & b) | (a & ~b);

endmodule

OUTPUT
RTL VIEW:
TTL VIEW:

4) BEHAVIOUR MODELING
Code:

module lab1a,b,y);

input a,b;

output reg y;

always@({a,b})

begin
if (a == b)

else

y = 1'b0;

y = p1'b1;

end

endmodule

OUTPUT:
RTL VIEW:

TTL:
XNOR:

Code:

module lab1 (a,b,y);

input a,b;

output reg y;

always@({a,b})

begin

if (a != b)

else

y = 1'b0;

y = 1'b1;

end

endmodule

OUPUT:
RTL :
TTL:

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