MAHAKAVI BHARATHIYAR COLLEGE OF

ENGINEERING AND TECHNOLOGY

VASUDEVANALLUR- 627 758.

LABORATORY RECORD NOTE

STUDENT NAME :
…………………………………………………………………
REGISTER NO :
…………………………………………………………………
YEAR :
…………………………………………………………………
SEMESTER :
…………………………………………………………………
BRANCH :
…………………………………………………………………
LABORATORY CODE/ NAME :
…………………………………………………………………
 MAHAKAVI BHARATHIYAR COLLEGE OF
ENGINEERING AND TECHNOLOGY
VASUDEVANALLUR- 627 758.

Name :

Year/Semester :

Department :

Register No :

BONAFIDE CERTIFICATE

Certified that this record is the bonafide record work of the above Student in the

EC3352 DIGITAL SYSTEM DESIGN Laboratory during the academic year 2024-2025.

Staff in-charge Head of the Department

Submitted for the University Practical Examination held on ………………

Internal Examiner External Examiner

 CONTENT

STAFF
EX.NO. DATE TITLE Page No MARKS
SIGN.

1 STUDY OF LOGIC GATES

2 ADDER AND SUBTRACTOR

3 4-BITADDER AND SUBTRACTOR

4 CODE CONVERTOR

REALIZATION OF ENCODER AND

5 DECODER

6 MAGNITUDE COMPARATOR

7 MULTIPLEXER AND DEMULTIPLEXER

8 SHIFT REGISTER

SYNCHRONOUS AND
9
ASYNCHRONOUS COUNTER
Ex.No.-1 STUDY OF LOGIC GATES
Date:

AIM:

To study about logic gates and verify their truth tables

APPARATUS REQUIRED:

SL.NO. COMPONENT SPECIFICATION QTY

1. AND GATE IC7408 1
2. OR GATE IC7432 1
3. NOT GATE IC7404 1
4. NAND GATE 2I/P IC7400 1
5. NOR GATE IC7402 1
6. X-OR GATE IC7486 1
7. NAND GATE 3I/P IC7410 1
8. IC TRAINERKIT - 1
9. PATCH CORD - 14

THEORY:
Circuit that takes the logical decision and the process are called logic gates. Each
gate has one or more input and only one output. OR, AND and NOT are basic gates. NAND,
NOR and X-OR are known as universal gates. Basic gates form these gates.

AND GATE:
The AND gate performs a logical multiplication commonly known as AND
function. The output is high when both the inputs are high. The output is low level when any
one of the inputs is low.

OR GATE:
The OR gate performs a logical addition commonly known as OR function. The
output is high when any one of the inputs is high. The output is low level when both the
inputs are low.

NOT GATE:
The NOT gate is called an inverter. The output is high when the input is low. The
output is low when the input is high.

AND GATE:
The NAND gate is a contraction of AND-NOT. The output is high when both
inputs are low and any one of the input is low. The output is low level when both inputs are
high.
NOR GATE:
The NOR gate is a contraction of OR-NOT. The output is high when both inputs
are low. The output is low when one or both inputs are high.

OR GATE:
The output is high when any one of the inputs is high. The output is low when both
the inputs are low and both the inputs are high.

PROCEDURE:
 Connections are given as per circuit diagram.
 Logical inputs are given as per circuit diagram.
 Observe the output and verify the truth table.

AND GATE

SYMBOL PIN DIAGRAM

OR GATE
 NOT GATE

SYMBOL PIN DIAGRAM

EX-OR GATE

SYMBOL PIN DIAGRAM

 2-INPUTN AND GATE

SYMBOL PIN DIAGRAM

3-INPUTN AND GATE

 NOR GATE

RESULT:

The logic gates are studied and its truth tables are verified.
Ex.No.-2 ADDER AND SUBTRACTOR
Date:

AIM:
To design and construct half adder, full adder, half subtractor and full subtractor
circuits and verify the truth table using logic gates.

APPARATUS REQUIRED:

SL.NO. COMPONENT SPECIFICATION QTY.

1. ANDGATE IC7408 1
2. X-ORGATE IC7486 1
3. NOTGATE IC7404 1
4. ORGATE IC7432 1
5. ICTRAINERKIT - 1
6. PATCHCORDS - 23

THEORY:
HALF ADDER:
A half adder has two inputs for the two bits to be added and two outputs one from
the sum ‘ S’ and other from the carry ‘ c’ into the higher adder position. Above circuit is
called as a carry signal from the addition of the less significant bits sum from the X-OR Gate
the carry out from the AND gate.
FULL ADDER:
A full adder is a combinational circuit that forms the arithmetic sum of input; it
consists of three inputs and two outputs. A full adder is useful to add three bits at a time but a
half adder cannot do so. In full adder sum output will be taken from X-OR Gate, carry output
will be taken from OR Gate.
HALF SUBTRACTOR:
The half subtractor is constructed using X-OR and AND Gate. The half
subtractor has two input and two outputs. The outputs are difference and borrow. The
difference can be applied using X-OR Gate, borrow output can be implemented using an
AND Gate and an inverter.

FULLSUBTRACTOR:
The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a
fullsubtractorthelogiccircuitshouldhavethreeinputsandtwooutputs.Thetwohalfsubtractorput
together gives a full subtractor .The first half subtractor will be C and A B. The
outputwillbedifferenceoutputoffullsubtractor.TheexpressionABassemblestheborrowoutputo
fthehalfsubtractorandthesecondtermistheinverteddifferenceoutputoffirstX-OR.
HALF ADDER
TRUTHTABLE:

A B CARRY SUM

0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

K-Map for SUM K-Map for CARRY:

1
1

SUM=A’B+AB’ CARRY=AB
LOGIC DIAGRAM:
 FULL ADDER

TRUTH TABLE:

A B C CARRY SUM

0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

K-Map for SUM

1 1

1 1

SUM=A’B’C+A’BC’+ABC’+ABC

K-Map for CARRY

CARRY= AB +BC+ AC
 LOGIC DIAGRAM:

FULL ADDER USING TWO HALF ADDER

HALF SUBTRACTOR
TRUTH TABLE:

A B BORROW DIFFERENCE

0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0

K-Map for DIFFERENCE

DIFFERENCE=A’B +AB’

K-Map for BORROW

12
 1
BORROW=A’B
LOGIC DIAGRAM

FULL SUBTRACTOR
TRUTH TABLE:

A B C BORROW DIFFERENCE

0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

K-Map for Difference

1 1

1 1

Difference =A’B’C+A’BC’+AB’C’+ABC
K-Map for Borrow

13
 Borrow=A’B+BC+A’C
LOGIC DIAGRAM:

FULL SUBTRACTOR USING TWO HALF SUBTRACTOR

14
PROCEEDURE:
 Connections are given as per circuit diagram.
 Logical inputs are given as per circuit diagram.
 Observe the output and verify the truth table.

RESULT:

Thus the half adder, full adder, half subtractor and full subtractor circuits are
designed, constructed and verified the truth table using logic gates

15
Ex.No.- 3 4-BITADDERANDSUBTRACTOR

AIM:
To design and implement 4-bit adder and subtractor using basic gates and MSI
device IC7483

APPARATUSREQUIRED:
SL.NO. COMPONENT SPECIFICATION QTY.
1. IC IC7483 1
2. EX-ORGATE IC7486 1
3. NOT GATE IC7404 1
3. ICTRAINERKIT - 1
4. PATCHCORDS - 40

THEORY:

4 BIT BINARY ADDERS:

A binary adder is a digital circuit that produces the arithmetic sum of two binary
numbers. It can be constructed with full adders connected in cascade, with the output carry
from each full adder connected to the input carry of next full adder in chain. The augends bits
of ‘A’ and the addend bits of ‘B’ are designated by subscript numbers from right to left, with
subscript0 denoting the least significant bits. The carries are connected in chain through the
full adder. The input carry to the adder is C0 and it ripples through the full adder to the
output carry C4.

4 BIT BINARY SUBTRACTOR:

The circuit for subtracting A-B consists of an adder with in verters, placed between
each data input ‘B’ and the corresponding input of full adder. The input carry C0 must
beequalto1whenperforming subtraction.

4 BIT BINARY ADDER/ SUBTRACTOR:

The addition and subtraction operation can be combined into one circuit with one
common binary adder. The mode input M controls the operation. When M=0, the circuit is
adder circuit. When M=1,it becomes subtractor.

4 BIT BCD ADDER:

Consider the arithmetic addition of two decimal digits in BCD, together with an
input carry from a previous stage. Since each input digit does not exceed 9, the output sum
cannot be greater than 19, the 1 in the sum being an input carry. The output of two decimal
digits must be represented in BCD and should appear in the form listed in the columns.
ABCD added that adds 2 BCD digits and produce a sum digit in BCD. The 2 decimal digits,

16
together with the input carry, are first added in the top 4 bit adder to produce the binary sum.
PIN DIAGRAM FOR IC7483:

4-BIT BINARY ADDER

LOGIC DIAGRAM:

4-BIT BINARY SUBTRACTOR

LOGIC DIAGRAM:

4- BIT BINARY ADDER/SUBTRACTOR

LOGIC DIAGRAM:

17
5- BIT BINARY ADDER/SUBTRACTOR

LOGIC DIAGRAM:

18
TRUTH TABLE:

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1
1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1
1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

PROCEDURE:
 Connections were given as per circuit diagram.
 Logical inputs were given as per truth table
 Observe the logical output and verify with the truth tables.

RESULT:

Thus the 4-bit adder and subtractor using basic gates and MSI device IC7483 is designed and
implemented

19
Ex.No.-4 CODE CONVERTOR
Date:

AIM:
To design and implement 4-bit
(i) Binary to gray code converter
(ii) Gray to Binary code converter
(iii) BCD to Excess-3 code converter
(iv) Excess-3 to BCD code converter

APPARATUS REQUIRED:
SL.NO. COMPONENT SPECIFICATION QTY.
1. X-ORGATE IC 7486 1
2. ANDGATE IC 7408 1
3. ORGATE IC 7432 1
4. NOT GATE IC 7404 1
5. ICTRAINERKIT - 1
6. PATCHCORDS - 35

THEORY:
The availability of large variety of codes for the same discrete elements of
information results in the use of different codes by different systems. A conversion
circuit must be inserted between the two systems if each uses different codes for same
information. Thus, code converter is a circuit that makes the two systems compatible even
though each uses different binary code.

The bit combination assigned to binary code to gray code. Since each code uses four
bits to represent a decimal digit. There are four inputs and four outputs. Gray code is a non-
weighted code.

The input variable are designated as B3, B2, B1, B0 and the output variables are
designated as C3, C2, C1, Co. from the truth table, combinational circuit is designed. The
Boolean functions are obtained from K-Map for each output variable.

A code converter is a circuit that makes the two systems compatible even though
each uses a different binary code. To convert from binary code to Excess-3 code, the input
lines must supply the bit combination of elements as specified by code and the output lines
generate the corresponding bit combination of code. Each one of the four maps represents
one of the four outputs of the circuit as a function of the four input variables.

20
 A two-level logic diagram may be obtained directly from the Boolean expressions
derived by the maps. These are various other possibilities for a logic diagram that implements
this circuit. Now the OR gate whose output is C+D has been used to implement partially each
of three outputs.

BINARY TO GRAY CODE CONVERTOR

TRUTHTABLE:

Binary Input Gray Code Output

B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

K-Map for G3

G3=B3

21
K-Map for G2

K-Map for G1

K-Map for G0

22
LOGIC DIAGRAM:

GRAY CODE TO BINARY CONVERTOR

TRUTH TABLE:

GRAY CODE BINARY CODE

G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1

23
K-Map for B3:

B3=G3

K-Map for B2:

K-Map for B1:

24
K-Map for B0:

LOGIC DIAGRAM:

25
TRUTH TABLE:
BCD TO EXCESS-3 CONVERTOR

| BCDinput | Excess – 3 output |

B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 1 1

0 0 0 1 0 1 0 0

0 0 1 0 0 1 0 1

0 0 1 1 0 1 1 0

0 1 0 0 0 1 1 1

0 1 0 1 1 0 0 0

0 1 1 0 1 0 0 1

0 1 1 1 1 0 1 0

1 0 0 0 1 0 1 1

1 0 0 1 1 1 0 0

1 0 1 0 x x x x

1 0 1 1 x x x x

1 1 0 0 x x x x

1 1 0 1 x x x x

1 1 1 0 x x x x

1 1 1 1 x x x X

K-Map for E3:

E3=B3+B2(B0+B1)

26
K-MapforE2:

K-MapforE1:

K-MapforE0:

27
EXCESS-3 TO BCD CONVERTOR
TRUTHTABLE:
| Excess– 3 Input | BCDOutput |

B3 B2 B1 B0 G3 G2 G1 G0

0 0 1 1 0 0 0 0

0 1 0 0 0 0 0 1

0 1 0 1 0 0 1 0

0 1 1 0 0 0 1 1

0 1 1 1 0 1 0 0

1 0 0 0 0 1 0 1

1 0 0 1 0 1 1 0

1 0 1 0 0 1 1 1

1 0 1 1 1 0 0 0

1 1 0 0 1 0 0 1

LOGIC DIAGRAM:

28
EXCESS-3 TO BCD CONVERTOR

K-Map for A:

A =X1X2+X3X4X1

K-Map for B:

K-Map for C:

23

29
K-Map for D:

EXCESS-3 TO BCD CONVERTOR

30
PROCEDURE:
 Connections were given as per circuit diagram.
 Logical inputs were given as per truth table
 Observe the logical output and verify with the truth tables

RESULT:

Thus, the following 4-bit converters are designed and constructed

(i) Binary to gray code converter
(ii)Gray to Binary code converter
(iii)BCD to Excess-3 code converter
(iv)Excess-3 to BCD code converter

31
Exp.No.: 5
Date: REALIZATION OF ENCODER AND DECODER

Aim:
To realize the Encoder and Decoder circuit using logic gates and to verify the truth table

Apparatus Required:

Sl. No Component Type Quantity

1 Trainer Kit - 1
2 OR Gate IC 7432 3
3 AND gate(3 input) IC7411 2
4 NOT gate IC 7404 1
5 Connecting wires - Required
6 Patch Chords 13

Theory:
ENCODER: (8:3)
An encoder has 2n (or fewer) input lines and ‘n’ output lines. The output lines
generate the binary code corresponding to the input value. In encoders, it is assumed that only
one input has a value of 1 at any given time. The octal to binary encoder(8:3) has eight inputs,
one for each octal digit, and three outputs that generate the corresponding binary code. In
encoder only one input has a valueof1atanygiventime. The encoders are specified as m-to-n
encoders where m ≤ 2n.

Truth Table:

Inputs Outputs
D0 D1 D2 D3 D4 D5 D6 D7 A B C
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1

Logical Expression:
A=D4+D5+D6+D7
B=D2+D3+D6+D7
32
C=D1+D3+D5+D7
Logic Diagram:

DECODER: (3:8)
Theory:
A decoder is a combinational circuit that converts binary information from ‘n’ input
lines to a maximum of 2n unique output lines. It performs the reverse operation of the
encoder. If then-bit decoded information has unused or don’t-care combinations, the decoder
output will have fewer than 2noutputs.The decoders are represented as n-to-m line decoders,
where m≤2n. Their purpose is to generate the 2n (or fewer) minterms of n input variables. The
name decoder is also used in conjunction with some code converters such as BCD-to-seven
segment decoders. Most, if not all, IC decoders include one or more enable inputs to control
the circuit operation. A decoder with an enable input can function as a de-multiplexer.
Logic Expression:

33
Truth Table:

INPUTS OUTPUTS

A B C D0 D1 D2 D3 D4 D5 D6 D7

0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

Logic diagram:

34
Procedure:
 The Encoder and Decoder circuit is designed and the Boolean function is found out.
 The Low level input is Grounded and the HIGH level input is connected to the +5V
supply.
 Connections are made as per the circuit given.
 Observe the output for various combinations of inputs.
 Thus the truth table is verified.

Result:
Thus the design and implementation the Encoder and Decoder circuit output was
verified with the help of truth table.

35
Ex.No.- 6 MAGNITUDE COMPARATOR
Date:

AIM:
To design and implement the magnitude comparator using MSI device

APPARATUSREQUIRED:

SL.NO. COMPONENT SPECIFICATION QTY.

1 ANDGATE IC7408 2
2 X-ORGATE IC7486 1
3 ORGATE IC7432 1
4 NOT GATE IC7404 1
5 4-BITMAGNITUDECOMPARATOR IC7485 2
6 ICTRAINERKIT - 1
7 PATCHCORDS - 30

THEORY:
The comparison of two numbers is an operator that determines one number is
greater than, less than (or) equal to the other number. A magnitude comparator is a
combinational circuit that compares two numbers A and B and determines their relative
magnitude. The outcome of the comparator is specified by three binary variables that indicate
whether A>B,A=B(or)A<B.
A=A3A2A1A0
B= B3B2B1B0
The equality of the two numbers and B is displayed in a combinational circuit
designated by the symbol (A=B).
This indicates A greater than B, then inspect the relative magnitude of pairs of significant
digits starting from most significant position. A is 0 and that of B is 0.

36
PIN DIAGRAM FOR IC7485:

8-BIT MAGNITUDE COMPARATOR

LOGIC DIAGRAM:

TRUTH TABLE:

A B A>B A=B A<B

0000 0000 0000 0000 0 1 0
0001 0001 0000 0000 1 0 0
0000 0000 0001 0001 0 0 1

37
PROCEDURE:
 Connections are given as per circuit diagram.
 Logical inputs are given as per circuit diagram.
 Observe the output and verify the truth table.

RESULT:
Thus , the magnitude comparator using MSI device was designed and implemented.

38
Ex.No.: 7 MULTIPLEXER AND DEMULTIPLEXER
Date:

AIM:
To design and implement the multiplexer and demultiplexer using logic gates and
study of IC74150 and IC74154

APPARATUS REQUIRED:

SL.NO. COMPONENT SPECIFICATION QTY.

1. 3I/PANDGATE IC7411 2
2. ORGATE IC7432 1
3. NOT GATE IC7404 1
2. ICTRAINERKIT - 1
3. PATCHCORDS - 32

THEORY:

MULTIPLEXER:
Multiplexer means transmitting a large number of information units over a smaller
number of channels or lines. A digital multiplexer is a combinational circuit that selects
binary information from one of many input lines and directs it to a single output line. The
selection of a particular input line is controlled by a set of selection lines. Normally there n
are 2 input line and n selection lines whose bit combination determine which input is
selected.

DEMULTIPLEXER:
The function of Demultiplexer is in contrast to multiplexer function. It takes
information from one line and distributes it to a given number of output lines. For this reason,
the demultiplexer is also known as a data distributor. Decoder can also be used as
demultiplexer.
In the 1:4 demultiplexer circuit, the data input line goes to all of the AND gates. The
data select lines enable only one gate at a time and the data on the data input line will pass
through the selected gate to the associated data output line.

39
4:1 MULTIPLEXER

BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:

FUNCTION TABLE:
S1 S0 INPUTS Y
0 0 D0→D0S1’S0’
0 1 D1→D1S1’S0
1 0 D2→D2S1S0’
1 1 D3→D3S1S0

Y =D0S1’S0’+D1S1’S0+D2S1S0’+D3S1S0
TRUTH TABLE:

S1 S0 Y=OUTPUT

0 0 D0

0 1 D1

1 0 D2

1 1 D3

40
CIRCUIT DIAGRAM FOR MULTIPLEXER:

1:4 DEMULTIPLEXER

BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:

FUNCTION TABLE:

S1 S0 INPUT
0 0 X→D0=XS1’S0’
0 1 X →D1=XS1’S0
1 0 X →D2=XS1S0’
1 1 X →D3=XS1S0
Y=XS1’S0’ +XS1’S0+XS1S0’+XS1S0

41
TRUTH TABLE:

INPUT OUTPUT
S1 S0 I/P D0 D1 D2 D3
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 0 0
0 1 1 0 1 0 0
1 0 0 0 0 0 0
1 0 1 0 0 1 0
1 1 0 0 0 0 0
1 1 1 0 0 0 1

LOGIC DIAGRAM FOR DEMULTIPLEXER:

42
PIN DIAGRAM FOR IC74150:

PIN DIAGRAM FOR IC74154:

43
PROCEDURE:

 Connections are given as per circuit diagram.

 Logical inputs are given as per circuit diagram.
 Observe the output and verify the truth table.

RESULT:
Thus, the multiplexer and demultiplexer using logic gates were designed and
implemented.

44
Ex.No.-8 SHIFT REGISTER
Date:

AIM:
To design and implement the following shift registers
(i) Serial in serial out
(ii) Serial in Parallel out
(iii) Parallel in serial out
(iv) Parallel in Parallel out

APPARATUS REQUIRED:

SL.NO. COMPONENT SPECIFICATION QTY.

1. DFLIPFLOP IC7474 2

2. ORGATE IC7432 1

3. ICTRAINERKIT - 1

4. PATCHCORDS - 35

THEORY:
A register is capable of shifting its binary information in one or both directions is
known as shift register. The logical configuration of shift register consist of a D-Flip flop
cascaded with output of one flip flop connected to input of next flip flop. All flip flops receive
common clock pulses which causes the shift in the output of the flip flop. The simplest
possible shift register is one that uses only flip flop. The output of a given flip flop is
connected to the input of next flip flop of the register. Each clock pulse shifts the content of
register one bit position to right.

PIN DIAGRAM OF IC7474:

45
 SERIAL IN SERIAL OUT

LOGIC DIAGRAM:

TRUTH TABLE:

CLK SerialIn SerialOut

1 1 0
2 0 0
3 0 0
4 1 1
5 X 0
6 X 0
7 X 1

SERIAL IN PARALLEL OUT

LOGIC DIAGRAM:

46
TRUTH TABLE:

OUTPUT
CLK DATA
QA QB QC QD
1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 1
4 1 1 0 0 1

PARALLEL IN SERIAL OUT

LOGIC DIAGRAM:

TRUTH TABLE:

CLK Q3 Q2 Q1 Q0 O/P

0 1 0 0 1 1

1 0 0 0 0 0

2 0 0 0 0 0

3 0 0 0 0 1

47
PARALLEL IN PARALLEL OUT
LOGIC DIAGRAM:

TRUTH TABLE:

DATAINPUT OUTPUT

CLK DA DB DC DD QA QB QC QD

1 1 0 0 1 1 0 0 1

2 1 0 1 0 1 0 1 0

48
PROCEDURE:
 Connections are given as per circuit diagram.
 Logical inputs are given as per circuit diagram.
 Observe the output and verify the truth table.

RESULT:
Thus, the following Shift registers were designed and implemented -
(i) Serial in serial out
(ii) Serial in Parallel out
(iii) Parallel in serial out
(iv) Parallel in Parallel out

49
Ex.No.9 SYNCHRONOUS AND ASYNCHRONOUS COUNTER
Date:

AIM
To design and implement synchronous and asynchronous counter

APPARATUS REQUIRED:

S.NO. NAMEOFTHEAPPARATUS RANGE QUANTITY

1. Digital IC trainer kit 1

2. JK FlipFlop IC7473 2
3. D FlipFlop IC7473 1
4. NAND gate IC7400 1
5. Connecting wires As required

THEORY:
Asynchronous decade counter is also called as ripple counter. In a ripple counter the
flip flop output transition serves as a source for triggering other flip flops. In other words the
clock pulse input so fall the flip flops are triggered not by the incoming pulses but rather by
the transition that occurs in other flip flops. The term asynchronous refers to the events that
do not occur at the same time. With respect to the counter operation, asynchronous means
that the flip flop within the counter are not made to change states at exactly the same time,
they do not because the clock pulses are not connected directly to the clock input of each flip
flop in the counter.
A counter is a register capable of counting number of clock pulse arriving at its
clock input. Counter represents the number of clock pulses arrived. A specified sequence of
states appears as counter output. This is the main difference between a register and a counter.
There are two types of counter, synchronous and asynchronous. In synchronous common
clock is given to all flip flop and in asynchronous first flip flop is clocked by external pulse
and then each successive flip flop is clocked by Q or Q output of previous stage. A soon the
clock of second stage is triggered by output of first stage. Because of inherent propagation
delay time all flip flops are not activated at same time which results in asynchronous
operation.

50
PIN DIAGRAM FOR IC7476:

CIRCUIT DIAGRAM:

TRUTH TABLE:

51
LOGIC DIAGRAM FOR MOD-10 RIPPLE COUNTER:

TRUTH TABLE:
CLK QA QB QC QD

0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
9 1 0 0 1
10 0 0 0 0

52
PIN DIAGRAM:

SYNCHRONOUS COUNTER

LOGIC DIAGRAM:

TRUTH TABLE:

OUTPUT
CLK DATA QA QB QC QD
1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 1
4 1 1 0 0 1

56
PROCEDURE:
 Connections are given as per circuit diagram.
 Logical inputs are given as per circuit diagram.
 Observe the output and verify the truth table.

RESULT:

Thus, the synchronous and asynchronous counter were designed and

implemented.

57