Course : ECI620

DIGITAL SYyY STEM DESIGN

Programmable Logic Devices

Instructor: Dr. Muhammad Awais

Department of Computer Engineering.

COMSATS University Islamabad, Wah Campus,Wah Cantt.
 Logic Implementation
Integrated
Circuits (ICs)

General Purpose Application

ICs (GPICs) Specific ICs(ASICs)

General Purpose Integrated Circuits (GPICs) – Discrete Logic ICs

• GPICs are discrete logic ICs that are sold as standard parts
• For example 7400 series (And gates, Or gates, Multiplexers, Memories,
microprocessors etc)
• Many GPICs are connected together to realize a logic function.
 What is an ASIC?
 An ASIC is
• An application specific Integrated Circuit
• A non standard IC designed to perform a particular, specialized function
• It is generally not software programmable (except microcontroller)
• It is not a memory chip but may contain memory
 Examples
• MPEG decoder
• Audio processor
• Digital filter
• Automobile controller etc.
 Pros / Cons
• Gives the best performance (speed, power, throughput, area)
for any application as compared to GPICs
• High reliability v.s. GPICs
• High Initial (NRE) cost and design time
• Can be very cost effective if produced in high volumes
 Making an IC (from sand to shelf)
 Step 1: Wafer Preparation
 Making an IC (from sand to shelf)
 STEP 2 : Photo Lithography

• Beautiful Plain Patterning. Ion Implantation.

Wafer ready to contain • The wafer is covered in a • High powered beams of
100s of microprocessors strategically patterned layer charged atoms or ions
in it of photo resist (stencil) • A.K.A Dopping
• Change in conductive
• 0.004 to 0.01 cm
properties of exposed regions
thick
• Photoresist is then removed
leaving complex traces of
conductive and non conductive
regions on silicon wafer
 Making an IC (from sand to shelf)
 STEP 2 : Photo Lithography

• Add successive layers (one atom • Add a photoresist • The wafer is then
thick) of high K dielectric layer layer exposed to a specific
• It play the role of SiO2 insulator in pattern of ultra violet
a CMOS transistor light which turns
sections of the photo
resist soluble, in a
process called photo
lithography.
The pattern of light is achieved by using finely
detailed ‘masks’, which act like stencils.
 Making an IC (from sand to shelf)
 STEP 2 : Photolithography (contd..)

Zoom in to single transistor Etching the dielectric.

Black line in the middle shows Area of di-electric outside
the area where the mask stopped the photo resist is etched away using
the UV light from reaching the chemical.
photo resist. The photo resist is then removed leaving an
incredibly intricate pattern of High-K dielectric on
top of the conductive and non conductive silicon.

Right Figure: The yellow strip is the High-K

dielectric, and the green is the doped
conductive silicon
 Making an IC (from sand to shelf)
 STEP 3 : Electroplating and metal deposition

a b c d

a) The wafer is then covered in a layer of insulation material. Three holes are made in
to insulating layer.
b) The entire wafer is then placed into a copper sulphate solution and electroplated.
c) This leaves the entire wafer covered in a thin sheen of pure copper which now
needs to be removed.
d) This is done through a delicate polishing process which polishes the wafer back to
the insulation layer, leaving copper still deposited in the three holes etched earlier
in the process.
 Making an IC (from sand to shelf)
 STEP 3 : Electroplating and metal deposition (contd..)

 The transistors are now primed with metal contacts and just need wiring up;
unfortunately wiring up hundreds of millions of microscopic transistors is a mind-
bendingly complex task.
 The interconnects are built up in layers with modern chips, with up to 30 layers of
interconnects arranged above the surface of the chip in a bewilderingly complex
fashion.
 Making an IC (from sand to shelf)
 STEP 4: Testing and Packaging

 Primary Testing is done at  Each Dye is then

wafer level packaged in to a chip.
 The wafer is not cut
in to Dyes, each
representing a stand alone
circuit
 Summary
Wafer : A circular piece of pure silicon (10-15 cm in dia )
 Wafer Lot: 5 ~ 30 wafers, each containing hundreds of chips (Dies)
depending upon size of the die
 Die: A rectangular piece of silicon that contains one IC design
 Mask Layers: Each IC is manufactured with successive mask
layers(10 – 30 layers)
 First half-dozen or so layers define transistors
 Other half-dozen or so define Interconnect
 Types of ASICs

• So, primarily there are two types of ASICs depending upon the fact that whether
all the transistor or interconnect layers are designed by the ASIC designer himself or
he uses some of the lower layers predesigned by the IC manufacturing company .
 Types of ASICs
1. Full Custom ASICs
All transistor and mask layers are customized (designed by ASIC designer)

 Full-custom ASIC design makes sense only

• When no existing libraries exist or are not fit for the current
design’s performance requirements (area, speed, power etc)
• ASIC technology is new or/and so special that no cell library exits.
 Pros and Cons
• Offer highest performance
• Lowest cost (smallest die size) when designed in bulk amounts
• Increased design time, complexity, higher design cost and higher risk.

 Some Examples:
High-Voltage Automobile Control Chips, Analog/Digital Communication Chips, Sensors and
Actuators
 Types of ASICs
2. Semi Custom ASICs
Some of the layers are pre-designed while some layers are customized

2.a ) Standard Cell Based ASICs (CBICs – Sea Bicks)

 Use logic blocks from standard cell libraries.

 Also uses other mega-cells, full-custom

blocks, system-level macros(SLMs), functional
standard blocks (FSBs), cores etc.

 Manufacturing lead time is around 8 weeks

 Less efficient in size and performance but

lower in design cost
 Types of ASICs
2.a ) Standard Cell Based ASICs (CBICs – Sea Bicks) Continued..

Routing a CBIC (cell-based IC)

 A “wall” of standard cells forms a flexible block

 metal2 may be used in a ‘feedthrough’ cell to cross

over cell rows that use metal1 for wiring

 Other wiring cells: spacer cells, row-end cells , and power cells Layout of
a standard cell
 Types of ASICs
2.b ) Gate Array Based ASICs

 A.k.a. masked gate array (MGA) or pre-diffused

array
 A base array composed of base cells or primitive
cells
 Types
1. Channeled Gate Array
2. Channel Less Gate Array
3. Structured Gate Array

2.b.1) Channeled Gate Array

 The base cell array predefined (by foundry )
 Predefined areas for interconnects (channels)
 The interconnect is customized
 The interconnect uses predefined spaces between rows
of base cells
 Manufacturing lead time is between two days and two
weeks
 Types of ASICs
2.b ) Gate Array Based ASICs

2.b.2) Channel Less Gate Array

 A.k.a “Sea of Gates”
 No predefined areas for channel
 Manufacturing lead time is between two days and
two weeks
 Provide higher logic density as compared to
channeled gate array

2.b.3) Structured Gate Array

 Only the interconnect is customized
 Like a channel less gate array but
also contains some embedded custom blocks
 Manufacturing lead time is between two days
and two weeks
 Programmable ASICs

Programmable
ASICs

PLDs FPGAs

ROMs PALs PLAs CPLDs

PLDs: Programmable Logic Devices

ROMs: Read Only Memories
PALs: Programmable Array Logics
PLAs: Programmable Logic Arrays
CPLD: Complex Programmable Logic Device
FPGA: Field Programmable Logic Array
 Programmable Logic Devices
3. Programmable Logic Devices
• Pre-fabricated building block of many AND/OR gates (or NOR, NAND)
• "Personalized" by making or breaking connections among the gates
• None of the layers is customized

Inputs

Dense array of Dense array of

AND gates Product OR gates
terms

Outputs

Sum of products (min terms)

 Programmable ASICs
3. Programmable Logic Devices

• Depending on which of the AND/OR logic arrays is programmable,

we have three basic organizations

ORGANIZATION AND ARRAY OR ARRAY

PAL PROG. FIXED

PROM FIXED PROG.

PLA PROG. PROG.

Programming: Making connection between the input and output

 Programmable ASICs
3.1) Programmable Read Only Memory (PROM)

nx2n

Address Bus

Data Bus

A 2n x m ROM can implement m Boolean functions each with n inputs

 Programmable ASICs
3.1) Read Only Memory (ROM)
Implementation example - Full Adder
a b c Sum cout sum = a bc + abc + ab c + abc
0 0 0 0 0 cout = abc + ab c + abc + abc
0 0 1 1 0
Storage Part
0 1 0 1 0 abc 0 0
0 1 1 0 1
a abc 1 0
1 0 0 1 0 abc
1 0
1 0 1 0 1 abc
0 1
b 3x8 decoder abc
1 1 0 0 1
1 0
abc
1 1 1 1 1
0 1
c abc
abc 0 1
1 1

8x2 ROM Sum Cout

 Programmable ASICs
3.1) Read Only Memory (ROM)
Implementation example - Full Adder
a b c Sum cout sum = a bc + abc + ab c + abc
0 0 0 0 0
cout = abc + abc + abc + abc
0 0 1 1 0
0 1 0 1 0 abc
0 1 1 0 1
a abc
1 0 0 1 0 abc
1 0 1 0 1 abc
b 3x8 decoder abc
1 1 0 0 1
abc
1 1 1 1 1
c abc
abc

Fixed And Array (Decoder : Produces canonical min terms)

Programmable OR array (Produces sum of canonical min terms)
Sum Cout
 Programmable ASICs
3.2) Programmable Logic Array (PLA) Implementation

A B C A B C

AB
BC

AC

BC

F0 F1 F2 F3 F0 F1 F2 F3
Unprogrammed Device Programmed Device
All possible connections Unwanted connections are "blown"
are available
before programming
Note: some array structures
work by making connections
rather than breaking them
 Programmable ASICs
3.2) Programmable Logic Device (PLA) Logic Implementation
Alternative representation
A B C D

AB

AB

CD

CD

Unprogrammed Device
AB+AB CD+CD
Programmed Device
 PALs vs PLAs
What is difference between Programmable Array Logic (PAL) and
Programmable Logic Array (PLA)?

PAL concept — implemented by Monolithic Memories

AND array is programmable, OR array is fixed at fabrication
A given column of the OR array
has access to only a subset of
the possible product terms

PLA concept — Both AND and OR arrays are

programmable

• Of the two organizations the PLA is the most flexible

– One PLA can implement a huge range of logic functions
– BUT many pins; large package, higher cost
• PALs are more restricted / you trade number of OR terms vs number of outputs
– Many device variations needed
– Each device is cheaper than a PLA
 Programmable ASICs
3. Programmable Array Logic (PAL) Implementation
Design Example: BCD to Gray Code Converter

Truth Table AB
A
AB
A

A B C D W X Y Z CD 00 01 11 10 CD 00 01 11 10
0 0 0 0 0 0 0 0 00 0 0 X 1 00 0 1 X 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1 01 0 1 X 1 01 0 1 X 0
0 0 1 1 0 0 1 0 D D
0 1 0 0 0 1 1 0 11 0 1 X X 11 0 0 X X
0 1 0 1 1 1 1 0 C C
0 1 1 0 1 0 1 0 10 0 1 X X 10 0 0 X X
0 1 1 1 1 0 1 1
1 0 0 0 1 0 0 1 B B
1 0 0 1 1 0 0 0 K-map for W K-map for X
1 0 1 0 X X X X
1 0 1 1 X X X X A A
1 1 0 0 X X X X AB AB
1 1 0 1 X X X X CD 00 01 11 10 CD 00 01 11 10
1 1 1 0 X X X X 00 0 1 X 0 00 0 0 X 1
1 1 1 1 X X X X
01 0 1 X 0 01 1 0 X 0
Minimized Functions: D D
11 1 1 X X 11 0 1 X X
W=A+BD+BC C
10 1 1 X X
C
10 1 0 X X
X=BC
Y=B+C B B
Z=ABCD+BCD+AD+BCD K-map for Y K-map for Z
 Programmable ASICs
3. PAL Logic Implementation (And Array Programmable, Or Array
Fixed) A B C D

Design Example: BCD to Gray Code Converter A

BD
Minimized Functions: BC
0
BC
0
W=A+BD+BC
0
X=BC
0
Y=B+C
B
Z=ABCD+BCD+AD+BCD
C
0
0
ABCD
BCD
AD
BCD

W X Y Z
 Programming Technologies

• Consider the following circuit

Logic 1
Potential links

a Pull-up resistors

NOT & y = 1 (N/A)

b
AND

NOT
 Programming Technologies
Fusible Link Technology
• First technique that allowed users to program their devices
• Devices come with all links in place-each link is referred to as fuse
• Fuses can be selectively removed by applying pulses of high voltage and
current (i.e. 5mAmps)
Fuses Logic 1

Fat
a Pull-up resistors

Faf

NOT & y = 0 (N/A)

Fbt
b AND
Fbf

NOT
 Programming Technologies
Fusible Link Technology
Example: Programming for y= a & !b
Logic 1

Fat
a Pull-up resistors

NOT & y = a & !b

b AND
Fbf

NOT
 Programming Technologies
AntiFuse Technology
• Each configurable path has an associated link called as antifuse
• In unprogrammed state, antifuse offer high resistence ‘open circuit’
• Antifuses can be selectively grown by applying pulses of high voltage and
current
Logic 1
Unprogrammed
antifuses

a Pull-up resistors

NOT & y = 1 (N/A)

b
AND

NOT
 Programming Technologies
Anti Fuse Technology

Example: Programming for y= !a & b

Logic 1
Programmed
antifuses

a Pull-up resistors

NOT & y = !a & b

b AND

NOT
 Programming Technologies
AntiFuse Technology
Amorphous silicon column Polysilicon via

Metal
Oxide
Metal
Substrate

(a) Before programming (b) After programming

Growing an antifuse.
Applying a high current (5 mA) melts the liquid (Oxide-nitride-oxide ONO) between the
two electrodes and provides a conductive path.

Link : Alloy of tungsten, titanium an silicon with bulk resistance of 500uohmcm

Note: Both Fuse and Antifuse technology provide permanent connections
i.e. One Time Programmability (OTP)
 Programming Technologies
Mask ROM (MROM)
A ROM whose contents are programmed by the IC manufacturer (foundry) and not by
the user.
Bit is stored with the help of a hardwired connection made in the foundry using
Lithiography
Logic 1
Mask-programmed
connection Pull-up resistor
Row
(word) line

Transistor Column
(data) line
Logic 0
 Programming Technologies
Programmable ROM (PROM)
A ROM whose contents are stored by the user using a specialized programmer
“Actuator”
Logic 1

Fusible link Pull-up resistor

Row
(word) line

Transistor Column
(data) line
Logic 0

One Time Programmable (OTP): Once programmed , the contents cannot be errased
 Programming Technologies
Erasable Programmable ROM (EPROM)
• A special type of ROM that is programmed electrically and yet is erasable under UV light

• The EPROM device is programmed by forcing an electrical charge on a small piece of

Polysilicon material (called the floating gate) located in the memory cell. When this charge is
present on this gate, the cell is “programmed,” usually a logic “0,” and when this charge is not
present, it is a logic “1.”

• To erase the EPROM, it is exposed to an ultraviolet light for approximately 20 minutes

through a quartz window in its ceramic package
 Programming Technologies
Electrically Erasable Programmable
ROM (EEPROM)
• Provides in system programmability (ISP)
• An E2PROM cell is app 2.5 times larger than EPROM cell because it
comprises two transistors and there is a space between them
• An E2PROM cell is similar to EPROM cell in that it contains a floating gate.
The oxide layer b/w two transistors is very thin. The second transistor can be
used to erase the cell electrically

Normal E2PROM
MOS transistor transistor

E2PROM Cell