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 Global
edition

Computer Organization
and Architecture
Designing for Performance
tenth edition

William Stallings
 To Tricia
my loving wife, the kindest
and gentlest person
This page intentionally left blank.
Contents
Foreword 13
Preface 15
About the Author 23

Part One Introduction 25

Chapter 1 Basic Concepts and Computer Evolution 25
1.1 Organization and Architecture 26
1.2 Structure and Function 27
1.3 A Brief History of Computers 35
1.4 The Evolution of the Intel x86 Architecture 51
1.5 Embedded Systems 53
1.6 Arm Architecture 57
1.7 Cloud Computing 63
1.8 Key Terms, Review Questions, and Problems 66
Chapter 2 Performance Issues 69
2.1 Designing for Performance 70
2.2 Multicore, Mics, and Gpgpus 76
2.3 Two Laws that Provide Insight: Ahmdahl’s Law and Little’s Law 77
2.4 Basic Measures of Computer Performance 80
2.5 Calculating the Mean 83
2.6 Benchmarks and Spec 91
2.7 Key Terms, Review Questions, and Problems 98

Part Two The Computer System 104

Chapter 3 A ­Top-​­Level View of Computer Function and Interconnection 104
3.1 Computer Components 105
3.2 Computer Function 107
3.3 Interconnection Structures 123
3.4 Bus Interconnection 124
3.5 ­ Point-​­to-​­Point Interconnect 126
3.6 Pci Express 131
3.7 Key Terms, Review Questions, and Problems 140
Chapter 4 Cache Memory 144
4.1 Computer Memory System Overview 145
4.2 Cache Memory Principles 152
4.3 Elements of Cache Design 155
4.4 Pentium 4 Cache Organization 173
4.5 Key Terms, Review Questions, and Problems 176
Appendix 4A Performance Characteristics of Two-​­Level Memories 181

7
8  Contents
Chapter 5 Internal Memory 189
5.1 Semiconductor Main Memory 190
5.2 Error Correction 198
5.3 DDR Dram 204
5.4 Flash Memory 209
5.5 Newer Nonvolatile ­Solid-​­State Memory Technologies 211
5.6 Key Terms, Review Questions, and Problems 214
Chapter 6 External Memory 218
6.1 Magnetic Disk 219
6.2 Raid 228
6.3 Solid State Drives 236
6.4 Optical Memory 241
6.5 Magnetic Tape 246
6.6 Key Terms, Review Questions, and Problems 248
Chapter 7 Input/Output 252
7.1 External Devices 254
7.2 I/O Modules 256
7.3 Programmed I/O 259
7.4 ­ Interrupt-​­Driven I/O 263
7.5 Direct Memory Access 272
7.6 Direct Cache Access 278
7.7 I/O Channels and Processors 285
7.8 External Interconnection Standards 287
7.9 IBM zEnterprise EC12 I/O Structure 290
7.10 Key Terms, Review Questions, and Problems 294
Chapter 8 Operating System Support 299
8.1 Operating System Overview 300
8.2 Scheduling 311
8.3 Memory Management 317
8.4 Intel x86 Memory Management 328
8.5 Arm Memory Management 333
8.6 Key Terms, Review Questions, and Problems 338

Part Three Arithmetic and Logic 342

Chapter 9 Number Systems 342
9.1 The Decimal System 343
9.2 Positional Number Systems 344
9.3 The Binary System 345
9.4 Converting Between Binary and Decimal 345
9.5 Hexadecimal Notation 348
9.6 Key Terms and Problems 350
Chapter 10 Computer Arithmetic 352
10.1 The Arithmetic and Logic Unit 353
10.2 Integer Representation 354
10.3 Integer Arithmetic 359
 Contents  9

10.4 ­ Floating-​­Point Representation 374

10.5 ­ Floating-​­Point Arithmetic 382
10.6 Key Terms, Review Questions, and Problems 391
Chapter 11 Digital Logic 396
11.1 Boolean Algebra 397
11.2 Gates 400
11.3 Combinational Circuits 402
11.4 Sequential Circuits 420
11.5 Programmable Logic Devices 429
11.6 Key Terms and Problems 433

Part Four The Central Processing Unit 436

Chapter 12 Instruction Sets: Characteristics and Functions 436
12.1 Machine Instruction Characteristics 437
12.2 Types of Operands 444
12.3 Intel x86 and ARM Data Types 446
12.4 Types of Operations 449
12.5 Intel x86 and ARM Operation Types 462
12.6 Key Terms, Review Questions, and Problems 470
Appendix 12A ­Little-, ­Big-, and ­Bi-​­Endian 476
Chapter 13 Instruction Sets: Addressing Modes and Formats 480
13.1 Addressing Modes 481
13.2 x86 and ARM Addressing Modes 487
13.3 Instruction Formats 493
13.4 x86 and ARM Instruction Formats 501
13.5 Assembly Language 506
13.6 Key Terms, Review Questions, and Problems 508
Chapter 14 Processor Structure and Function 512
14.1 Processor Organization 513
14.2 Register Organization 515
14.3 Instruction Cycle 520
14.4 Instruction Pipelining 524
14.5 The x86 Processor Family 541
14.6 The ARM Processor 548
14.7 Key Terms, Review Questions, and Problems 554
Chapter 15 Reduced Instruction Set Computers 559
15.1 Instruction Execution Characteristics 561
15.2 The Use of a Large Register File 566
15.3 ­ Compiler-​­Based Register Optimization 571
15.4 Reduced Instruction Set Architecture 573
15.5 RISC Pipelining 579
15.6 MIPS R4000 583
15.7 SPARC 589
15.8 RISC versus CISC Controversy 594
15.9 Key Terms, Review Questions, and Problems 595
10  Contents
Chapter 16 ­Instruction-​­Level Parallelism and Superscalar Processors 599
16.1 Overview 600
16.2 Design Issues 605
16.3 Intel Core Microarchitecture 615
16.4 ARM ­Cortex-​­A8 620
16.5 ARM ­Cortex-​­M3 628
16.6 Key Terms, Review Questions, and Problems 632

Part Five Parallel Organization 637

Chapter 17 Parallel Processing 637
17.1 Multiple Processor Organizations 639
17.2 Symmetric Multiprocessors 641
17.3 Cache Coherence and the MESI Protocol 645
17.4 Multithreading and Chip Multiprocessors 652
17.5 Clusters 657
17.6 Nonuniform Memory Access 664
17.7 Cloud Computing 667
17.8 Key Terms, Review Questions, and Problems 674
Chapter 18 Multicore Computers 680
18.1 Hardware Performance Issues 681
18.2 Software Performance Issues 684
18.3 Multicore Organization 689
18.4 Heterogeneous Multicore Organization 691
18.5 Intel Core i7-990X 700
18.6 ARM ­Cortex-​­A15 MPCore 701
18.7 IBM zEnterprise EC12 Mainframe 706
18.8 Key Terms, Review Questions, and Problems 709
Chapter 19 ­General-​­Purpose Graphic Processing Units 712
19.1 Cuda Basics 713
19.2 GPU versus CPU 715
19.3 GPU Architecture Overview 716
19.4 Intel’s Gen8 GPU 725
19.5 When to Use a GPU as a Coprocessor 728
19.6 Key Terms and Review Questions 730

Part Six The Control Unit 731

Chapter 20 Control Unit Operation 731
20.1 ­ Micro-​­Operations 732
20.2 Control of the Processor 738
20.3 Hardwired Implementation 748
20.4 Key Terms, Review Questions, and Problems 751
Chapter 21 Microprogrammed Control 753
21.1 Basic Concepts 754
21.2 Microinstruction Sequencing 763
 Contents  11

21.3 Microinstruction Execution 769

21.4 TI 8800 779
21.5 Key Terms, Review Questions, and Problems 790

Appendix A Projects for Teaching Computer Organization and Architecture 792

A.1 Interactive Simulations 793
A.2 Research Projects 795
A.3 Simulation Projects 795
A.4 Assembly Language Projects 796
A.5 Reading/Report Assignments 797
A.6 Writing Assignments 797
A.7 Test Bank 797

Appendix B Assembly Language and Related Topics 798

B.1 Assembly Language 799
B.2 Assemblers 807
B.3 Loading and Linking 811
B.4 Key Terms, Review Questions, and Problems 819

References 824
Index 833
Credits 857

Online Appendices1

Appendix C System Buses

Appendix D Protocols and Protocol Architectures
Appendix E Scrambling
Appendix F Victim Cache Strategies
Appendix G Interleaved Memory
Appendix H International Reference Alphabet
Appendix I Stacks
Appendix J Thunderbolt and Infiniband
Appendix K Virtual Memory Page Replacement Algorithms
Appendix L Hash Tables
Appendix M Recursive Procedures
Appendix N Additional Instruction Pipeline Topics
Appendix O Timing Diagrams
Glossary

1
Online chapters, appendices, and other documents are Premium Content, available via the access card
at the front of this book.
This page intentionally left blank.
Foreword
by Chris Jesshope
Professor (emeritus) University of Amsterdam
Author of Parallel Computers (with R W Hockney), 1981 & 1988

Having been active in computer organization and architecture for many years, it is a pleas-
ure to write this foreword for the new edition of William Stallings’ comprehensive book on
this subject. In doing this, I found myself reflecting on the trends and changes in this subject
over the time that I have been involved in it. I myself became interested in computer archi-
tecture at a time of significant innovation and disruption. That disruption was brought about
not only through advances in technology but perhaps more significantly through access to
that technology. VLSI was here and VLSI design was available to students in the classroom.
These were exciting times. The ability to integrate a mainframe style computer on a single
silicon chip was a milestone, but that this was accomplished by an academic research team
made the achievement quite unique. This period was characterized by innovation and diver-
sity in computer architecture with one of the main trends being in the area of parallelism.
In the 1970s, I had ­hands-​­on experience of the Illiac IV, which was an early example of
explicit parallelism in computer architecture and which incidentally pioneered all semicon-
ductor memory. This interaction, and it certainly was that, ­kick-​­started my own interest in
computer architecture and organization, with particular emphasis on explicit parallelism in
computer architecture.
Throughout the 1980s and early 1990s research flourished in this field and there was a
great deal of innovation, much of which came to market through university ­start-​­ups. Iron-
ically however, it was the same technology that reversed this trend. Diversity was gradually
replaced with a near monoculture in computer systems with advances in just a few instruc-
tion set architectures. Moore’s law, a ­self-​­fulfilling prediction that became an industry guide-
line, meant that basic device speeds and integration densities both grew exponentially, with
the latter doubling every 18 months of so. The speed increase was the proverbial free lunch
for computer architects and the integration levels allowed more complexity and innovation
at the ­micro-​­architecture level. The free lunch of course did have a cost, that being the expo-
nential growth of capital investment required to fulfill Moore’s law, which once again limited
the access to ­state-​­of-​­the-​­art technologies. Moreover, most users found it easier to wait for
the next generation of mainstream processor than to invest in the innovations in parallel
computers, with their pitfalls and difficulties. The exceptions to this were the few large insti-
tutions requiring ultimate performance; two topical examples being ­large-​­scale scientific
simulation such as climate modeling and also in our security services for code breaking. For

13
14  Foreword

everyone else, the name of the game was compatibility and two instruction set architectures
that benefited from this were x86 and ARM, the latter in embedded systems and the former
in just about everything else. Parallelism was still there in the implementation of these ISAs,
it was just that it was implicit, harnessed by the architecture not in the instruction stream
that drives it.
Throughout the late 1990s and early 2000s, this approach to implicitly exploiting con-
currency in ­single-​­core computer systems flourished. However, in spite of the exponential
growth of logic density, it was the cost of the techniques exploited which brought this era to
a close. In superscalar processors, the logic costs do not grow linearly with issue width (par-
allelism), while some components grow as the square or even the cube of the issue width.
Although the exponential growth in logic could sustain this continued development, there
were two major pitfalls: it was increasingly difficult to expose concurrency implicitly from
imperative programs and hence efficiencies in the use of instruction issue slots decreased.
Perhaps more importantly, technology was experiencing a new barrier to performance
gains, namely that of power dissipation, and several superscalar developments were halted
because the silicon in them would have been too hot. These constraints have mandated the
exploitation of explicit parallelism, despite the compatibility challenges. So it seems that
again innovation and diversity are opening up this area to new research.
Perhaps not since the 1980s has it been so interesting to study in this field. That diver-
sity is an economic reality can be seen by the decrease in issue width (implicit parallelism)
and increase in the number of cores (explicit parallelism) in mainstream processors. How-
ever, the question is how to exploit this, both at the application and the system level. There
are significant challenges here still to be solved. Superscalar processors rely on the processor
to extract parallelism from a single instruction stream. What if we shifted the emphasis and
provided an instruction stream with maximum parallelism, how can we exploit this in dif-
ferent configurations and/or generations of processors that require different levels of expli-
cit parallelism? Is it possible therefore to have a ­micro-​­architecture that sequentializes and
schedules this maximum concurrency captured in the ISA to match the current configur-
ation of cores so that we gain the same compatibility in a world of explicit parallelism? Does
this require operating systems in silicon for efficiency?
These are just some of the questions facing us today. To answer these questions and
more requires a sound foundation in computer organization and architecture, and this book
by William Stallings provides a very timely and comprehensive foundation. It gives a com-
plete introduction to the basics required, tackling what can be quite complex topics with
apparent simplicity. Moreover, it deals with the more recent developments in this field,
where innovation has in the past, and is, currently taking place. Examples are in superscalar
issue and in explicitly parallel multicores. What is more, this latest edition includes two very
recent topics in the design and use of GPUs for ­general-​­purpose use and the latest trends in
cloud computing, both of which have become mainstream only recently. The book makes
good use of examples throughout to highlight the theoretical issues covered, and most of
these examples are drawn from developments in the two most widely used ISAs, namely the
x86 and ARM. To reiterate, this book is complete and is a pleasure to read and hopefully
will ­kick-​­start more young researchers down the same path that I have enjoyed over the last
40 years!
Preface
What’s New in the Tenth Edition
Since the ninth edition of this book was published, the field has seen continued innovations
and improvements. In this new edition, I try to capture these changes while maintaining a
broad and comprehensive coverage of the entire field. To begin this process of revision, the
ninth edition of this book was extensively reviewed by a number of professors who teach
the subject and by professionals working in the field. The result is that, in many places, the
narrative has been clarified and tightened, and illustrations have been improved.
Beyond these refinements to improve pedagogy and ­user-​­friendliness, there have been
substantive changes throughout the book. Roughly the same chapter organization has been
retained, but much of the material has been revised and new material has been added. The
most noteworthy changes are as follows:
■■ GPGPU [­General-​­Purpose Computing on Graphics Processing Units (GPUs)]: One
of the most important new developments in recent years has been the broad adoption
of GPGPUs to work in coordination with traditional CPUs to handle a wide range of
­applications involving large arrays of data. A new chapter is devoted to the topic of
GPGPUs.
■■ Heterogeneous multicore processors: The latest development in multicore architecture

is the heterogeneous multicore processor. A new section in the chapter on multicore

processors surveys the various types of heterogeneous multicore processors.
■■ Embedded systems: The overview of embedded systems in Chapter 1 has been substan-

tially revised and expanded to reflect the current state of embedded technology.
■■ Microcontrollers: In terms of numbers, almost all computers now in use are embedded

microcontrollers. The treatment of embedded systems in Chapter 1 now includes cov-

erage of microcontrollers. The ARM ­Cortex-​­M3 microcontroller is used as an example
system throughout the text.
■■ Cloud computing: New to this edition is a discussion of cloud computing, with an over-

view in Chapter 1 and more detailed treatment in Chapter 17.

■■ System performance: The coverage of system performance issues has been

revised, expanded, and reorganized for a clearer and more thorough treatment.
Chapter 2 is devoted to this topic, and the issue of system performance arises through-
out the book.

15
16  Preface

■■ Flash memory: The coverage of flash memory has been updated and expanded, and now
includes a discussion of the technology and organization of flash memory for internal
memory (Chapter 5) and external memory (Chapter 6).
■■ Nonvolatile RAM: New to this edition is treatment of three important new nonvolatile

­solid-​­state RAM technologies that occupy different positions in the memory hierarchy:
­STT-​­RAM, PCRAM, and ReRAM.
■■ Direct cache access (DCA): To meet the protocol processing demands for very high

speed network connections, Intel and other manufacturers have developed DCA tech-
nologies that provide much greater throughput than traditional direct memory access
(DMA) approaches. New to this edition, Chapter 7 explores DCA in some detail.
■■ Intel Core Microarchitecture: As in the previous edition, the Intel x86 family is used as

a major example system throughout. The treatment has been updated to reflect newer
Intel systems, especially the Intel Core Microarchitecture, which is used on both PC and
server products.
■■ Homework problems: The number of supplemental homework problems, with solu-

tions, available for student practice has been expanded.

Support of ACM/IEEE Computer Science Curricula 2013

The book is intended for both an academic and a professional audience. As a textbook,
it is intended as a ­one-​­ or ­two-​­semester undergraduate course for computer science, com-
puter engineering, and electrical engineering majors. This edition is designed to support the
recommendations of the ACM/IEEE Computer Science Curricula 2013 (CS2013). CS2013
divides all course work into three categories: ­Core-​­Tier 1 (all topics should be included
in the curriculum); ­Core-​­Tier-​­2 (all or almost all topics should be included); and Elective
(desirable to provide breadth and depth). In the Architecture and Organization (AR) area,
CS2013 includes five ­Tier-​­2 topics and three Elective topics, each of which has a number of
subtopics. This text covers all eight topics listed by CS2013. Table P.1 shows the support for
the AR Knowledge Area provided in this textbook.

Table P.1 Coverage of CS2013 Architecture and Organization (AR) Knowledge Area
IAS Knowledge Units Topics Textbook Coverage
Digital Logic and Digital ●● Overview and history of computer architecture —Chapter 1
Systems (Tier 2) ●● Combinational vs. sequential logic/Field program- —Chapter 11
mable gate arrays as a fundamental combinational
sequential logic building block
●● Multiple representations/layers of interpretation
(hardware is just another layer)
●● Physical constraints (gate delays, ­fan-​­in, ­fan-​­out,
energy/power)
Machine Level Represen- ●● Bits, bytes, and words —Chapter 9
tation of Data (Tier 2) ●● Numeric data representation and number bases —Chapter 10
●● ­Fixed-​­and ­floating-​­point systems
●● Signed and ­twos-​­complement representations
●● Representation of ­non-​­numeric data (character
codes, graphical data)
 Preface  17

IAS Knowledge Units Topics Textbook Coverage

Assembly Level Machine ●● Basic organization of the von Neumann machine —Chapter 1
Organization (Tier 2) ●● Control unit; instruction fetch, decode, and execution —Chapter 7
●● Instruction sets and types (data manipulation, —Chapter 12
­control, I/O) —Chapter 13
●● Assembly/machine language programming —Chapter 17
●● Instruction formats —Chapter 18
●● Addressing modes —Chapter 20
●● Subroutine call and return mechanisms (­cross-​­ —Chapter 21
reference PL/Language Translation and Execution) —Appendix A
●● I/O and interrupts
●● Shared memory multiprocessors/multicore
organization
●● Introduction to SIMD vs. MIMD and the Flynn
Taxonomy
Memory System Organi- ●● Storage systems and their technology —Chapter 4
zation and Architecture ●● Memory hierarchy: temporal and spatial locality —Chapter 5
(Tier 2) ●● Main memory organization and operations —Chapter 6
●● Latency, cycle time, bandwidth, and interleaving —Chapter 8
●● Cache memories (address mapping, block size, —Chapter 17
replacement and store policy)
●● Multiprocessor cache consistency/Using the memory
system for ­inter-​­core synchronization/atomic mem-
ory operations
●● Virtual memory (page table, TLB)
●● Fault handling and reliability
Interfacing and Commu- ●● I/O fundamentals: handshaking, buffering, pro- —Chapter 3
nication (Tier 2) grammed I/O, ­interrupt-​­driven I/O —Chapter 6
●● Interrupt structures: vectored and prioritized, inter- —Chapter 7
rupt acknowledgment
●● External storage, physical organization, and drives
●● Buses: bus protocols, arbitration, ­direct-​­memory
access (DMA)
●● RAID architectures
Functional Organization ●● Implementation of simple datapaths, including —Chapter 14
(Elective) instruction pipelining, hazard detection, and —Chapter 16
resolution —Chapter 20
●● Control unit: hardwired realization vs. micropro- —Chapter 21
grammed realization
●● Instruction pipelining
●● Introduction to ­instruction-​­level parallelism (ILP)
Multiprocessing and ●● Example SIMD and MIMD instruction sets and —Chapter 12
Alternative Architectures architectures —Chapter 13
(Elective) ●● Interconnection networks —Chapter 17
●● Shared multiprocessor memory systems and memory
consistency
●● Multiprocessor cache coherence
Performance Enhance- ●● Superscalar architecture —Chapter 15
ments (Elective) ●● Branch prediction, Speculative execution, —Chapter 16
­Out-​­of-​­order execution —Chapter 19
●● Prefetching
●● Vector processors and GPUs
●● Hardware support for multithreading
●● Scalability
18  Preface

Objectives 
This book is about the structure and function of computers. Its purpose is to present, as clearly
and completely as possible, the nature and characteristics of ­modern-​­day computer systems.
This task is challenging for several reasons. First, there is a tremendous variety of prod-
ucts that can rightly claim the name of computer, from ­single-​­chip microprocessors costing
a few dollars to supercomputers costing tens of millions of dollars. Variety is exhibited not
only in cost but also in size, performance, and application. Second, the rapid pace of change
that has always characterized computer technology continues with no letup. These changes
cover all aspects of computer technology, from the underlying integrated circuit technology
used to construct computer components to the increasing use of parallel organization con-
cepts in combining those components.
In spite of the variety and pace of change in the computer field, certain fundamental
concepts apply consistently throughout. The application of these concepts depends on the
current state of the technology and the price/performance objectives of the designer. The
intent of this book is to provide a thorough discussion of the fundamentals of computer
organization and architecture and to relate these to contemporary design issues.
The subtitle suggests the theme and the approach taken in this book. It has always
been important to design computer systems to achieve high performance, but never has
this requirement been stronger or more difficult to satisfy than today. All of the basic per-
formance characteristics of computer systems, including processor speed, memory speed,
memory capacity, and interconnection data rates, are increasing rapidly. Moreover, they are
increasing at different rates. This makes it difficult to design a balanced system that maxi-
mizes the performance and utilization of all elements. Thus, computer design increasingly
becomes a game of changing the structure or function in one area to compensate for a per-
formance mismatch in another area. We will see this game played out in numerous design
decisions throughout the book.
A computer system, like any system, consists of an interrelated set of components.
The system is best characterized in terms of ­structure—​­the way in which components are
interconnected, and ­function—​­the operation of the individual components. Furthermore, a
computer’s organization is hierarchical. Each major component can be further described by
decomposing it into its major subcomponents and describing their structure and function.
For clarity and ease of understanding, this hierarchical organization is described in this book
from the top down:
■■ Computer system: Major components are processor, memory, I/O.
■■ Processor: Major components are control unit, registers, ALU, and instruction execu-
tion unit.
■■ Control unit: Provides control signals for the operation and coordination of all proces-

sor components. Traditionally, a microprogramming implementation has been used, in

which major components are control memory, microinstruction sequencing logic, and
registers. More recently, microprogramming has been less prominent but remains an
important implementation technique.
The objective is to present the material in a fashion that keeps new material in a clear
context. This should minimize the chance that the reader will get lost and should provide
better motivation than a ­bottom-​­up approach.
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Sullivan, Timothy P., Concord, N. H.; furnished granite from
his New Hampshire quarries for the new national Library
Building, Washington, D. C.
Sullivan, William B., attorney at law, Tremont Building,
Boston, Mass.
Supple, Rev. James N., rector of St. Francis de Sales Church,
Charlestown, Mass.
Sweeney, John F., the Sweeney Company, 256 Main Street,
Buffalo, N. Y. (Life member of the Society.)
Sweeney, Rev. Timothy P., Fall River, Mass.
Sweeny, William Montgomery, 120 Franklin Street, Astoria,
L. I., N. Y.
Swords, Joseph F., Sulphur, Oklahoma. He is a descendant of
Cornet George Swords, one of the A. D. 1649 officers in the
service of kings Charles I and Charles II in Ireland. Joseph F.
Swords is a member of the Sons of the American Revolution. He
is of the fourth American generation from Francis Dawson
Swords, graduate of Trinity College, Dublin, 1750, who was exiled
from Ireland, 1760, and who served in the Patriot Army
throughout the War of the Revolution. Vice-President of the
Society for Oklahoma.
 Synnott, Martin J., M. D., 30 Tulleston Avenue, Montclair,
N. J.
Tack, Theodore E., 52 Broadway, New York City.
Taggart, Hon. Thomas, Indianapolis, Ind.; proprietor of the
Grand Hotel; was elected auditor of Marion County, 1886; re-
elected, 1890; has been mayor of Indianapolis; chairman of the
Democratic state committee, 1892 and 1894; district chairman of
the seventh Congressional District; member from Indiana of the
Democratic national committee. Is a native of Ireland.
Talley, Alfred G., 27 William Street, New York City.
Teeling, Rt. Rev. Arthur J., D. D., rector of St Mary’s Church,
Lynn, Mass.
Thompson, Frank, 126 Liberty Street, New York City.
Thompson, James, of James Thompson & Bro., 127 West Main
Street, Louisville, Ky.
Tierney, Dennis H., real estate and insurance, Tierney’s Block,
167 Bank Street, Waterbury, Conn. Vice-President for
Connecticut.
Tierney, Edward M., Hotel Marlborough, Broadway, New
York City.
Tierney, Henry S., 59 Prescott Street, Torrington, Conn.
Tierney, Myles, 317 Riverside Drive, New York City. President
Hudson Trust Company, Hoboken, N. J. (Life member of the
Society.)
Tingent, Edward, 68 Broad Street, Elizabeth, N. J.
Toale, Patrick P., Toale P. O., Aiken County, S. C.
Tooley, Frank L., D. D. S., 157 East Seventy-ninth Street, New
York City.
Towle, Felix S., of F. S. Towle Company, Incorporated, 332
Broadway, New York City.
Travers, Vincent P., of the Travers Brothers Company, 41
Worth Street, New York City.
 Tully, Hon. William J., attorney at law, Corning, N. Y.; state
senator.
Vredenburgh, Watson, Jr., civil engineer, 135 Broadway,
New York City.
Waldron, E. M., of E. M. Waldron & Company, building
contractors, 84 South Sixth Street, Newark, N. J.
Waller, Hon. Thomas M., New London, Conn.; attorney at
law; member of the Connecticut Legislature 1867, 1868, 1872,
1876 (speaker, 1876); Secretary of State of Connecticut, 1870;
mayor of New London, 1873; State’s attorney, 1876–’83;
governor of Connecticut, 1882–’84; United States consul-general
to London, England, 1885–89; commissioner to World’s
Columbian Exposition.
Walsh, David I., attorney at law, Fitchburg, Mass.
Walsh, Frank, Secretary and credit manager, Wilkinson,
Gaddis & Company, wholesale grocers, 866–868 Broad Street,
Newark, N. J.
Walsh, P. J., 503 Fifth Avenue, New York City.
Walsh, Philip C., 260 Washington Street, Newark, N. J.; of
Walsh’s Sons & Company, dealers in irons and metals.
Walsh, Philip C., Jr., 260 Washington Street, Newark, N. J.
Walsh, William P., 247 Water Street, Augusta, Me.
Ward, Edward, of Ward Bros., contractors, Kennebunk, Me.
Ward, John T., contractor, Kennebunk, Me.
Ward, Michael J., 17 Shailer Street, Brookline, Mass.
Whalen, Hon. John S., Secretary of State of New York,
Albany, N. Y.
White, John B., Cashier of the Pennsylvania Railroad, 121
East Eighty-sixth Street, New York City. Member Catholic Club
of New York.
Woods, John, 297 Broadway, South Boston, Mass. Coal.
 Wright, Henry, enameled wall tile, vitrified and glazed
ceramics, aseptic floors, encaustic and embossed tiles, 248 East
One Hundred Forty-sixth Street, New York City.
Wynne, E. W., 78 Market Street, Charleston, S. C., of C. Bart &
Company.
Zabriskie, George A., 123 Produce Exchange, New York City.
 INDEX.

“Advantages of Historical Research to Irish

Americans,” by Hon. Robert J. Gamble, 152
American Irish Historical Society, Members of,
252
Ames, Gen. Williams, Address by, 32
Annual Meeting, Next, 157

Banquet, Eleventh Annual, 105

“Capital Welcome,” by Hon. Thomas H. Carter,

148
Carter Day Nursery, Dedication of, 165
Carter, Hon. Thomas H., Address by, 148
“Civic Value of Memorials,” by Miss Mary A.
Greene, 163
Constitution and By-Laws of the Society, 5
Crane, Major John, Memorial of, 87

Dedication of Carter Day Nursery, 165

Dinner Committee at Washington, 157
Dowling, Hon. Victor J., Address by, 117

“Early Marine ‘Wireless,’” by Edgar Stanton

Maclay, Esq., 195
Egan, Karl, “The Irish in the Revolutionary War,”,
218
Egan, Chief Patrick, War Record of, 177
Eleventh Annual Meeting, Proceedings of, 62
Executive Council of 1908, 19
Executive Council of 1909, 69

“First Census of the United States,” etc., by

Michael J. O’Brien, Esq., 209

Gamble, Hon. Robert J., Address by, 152

Gargan, Hon. Thomas J., Memorial of, 76
General Historical Items, 238
General Information About the Society, 13
Greene, Miss Mary A., Essay by, 163
Guests at Sullivan Memorial Dedication, 56

Healy, David, Esq., Address by, 23

Higgins, Gov. James H., Address by, 30
Historical Items, 238

Introduction, 3
“Irish Pioneers in New York,” by Hon. Victor J.
Dowling, 117
“Irish Pioneers of the West and Their
Descendants,” by Hon. Maurice T. Moloney, 139
“Irish in the Revolutionary War,” by Karl Egan,
218

Kelly, Hon. Hugh, Memorial of, 91

Lee, Thomas Zanslaur, Address by, 27

Lenehan, John J., Esq., Essay by, 183
Lippitt, Ex-Gov. Charles Warren, Address by, 49

Maclay, Edgar Stanton, Esq., Essay by, 195

McCarthy, Mayor Patrick J., Address by, 32
McTighe, Patrick J., Memorial of, 248
Members Elected at Eleventh Annual Meeting, 96
Membership Roll of 1909, 252
“Memorial to Jersey Prison Ship Heroes”, 217
Moloney, Hon. Maurice T., Address by, 139
Murray, Thomas Hamilton, Esq., Memorial of, 80

Next Annual Meeting, 157

O’Brien, Michael J., “First Census of the United

States,” etc., 209
O’Connor, Joseph, Memorial of, 171
Officers of the Society for 1908, 19
Officers of the Society for 1909, 68
O’Neill, James L., Esq., Essays by, 202
Organizations Represented at Sullivan Memorial
Dedication, 56

Papers Read Before Society, 14

Phelan, Hon. James J., Memorial of, 78
President-Generals of the Society, 16

Quinlan, Francis J., M. D., LL. D., Address by, 52,

107
Quinlan, Francis J., M. D., LL. D., Sketch by, 169
Quinlan, Col. James, War Record of, 169

Reception Committee at Washington, 157

Recommendations from Secretary-General’s
Office, 239
“Reilly of F,” by John Jerome Rooney, Esq., 243
Report of Treasurer, 100
Review of Some Historical Works, 231
Robinson, Col. David C., Address by, 36
Roche, Hon. James Jeffrey, LL. D., Memorial of,
93
Roll of Members for 1909, 252
Rooney, John Jerome, Esq., Poem by, 243

Sanders, Col. Christopher C., Memorial of, 245

Secretary-General’s Recommendations, 239
“Society of the Friendly Sons of St. Patrick in the
City of New York,” by John J. Lenehan, Esq.,
183
State Vice-Presidents for 1908, 20
State Vice-Presidents for 1909, 70
Sullivan Memorial at Rhode Island, 26

Tenth Annual Meeting, Proceedings of, 17

Thayer, Hon. Eli, An Early Member of the Society,
223
Treasurer’s Report for 1908–’09, 100
Twelfth Annual Meeting, Place Selected for
Holding, 157

Van Hoose, A. W., Esq., Tribute to Col.

Christopher C. Sanders, 245
Vice-Presidents for 1908, 20
Vice-Presidents for 1909, 70

Washington Meeting, 62
White, Hon. Edward D., Justice of the Supreme
Court of the United States, Address by, 113
 TRANSCRIBER’S
NOTES

Page Changed from Changed to

121 death is given as death is given as
September 24, September 24,
1864, and his age 1684, and his age
as 56. His will as 56. His will
207 the place the place
aforesaid, and aforesaid, and
though the good through the good
Providence of Providence of
God towards God towards
272 For some years For some years
pervious. to 1894 previous to 1894
he was a member he was a member
of the Republican of the Republican
State State

Typos fixed; non-standard spelling

and dialect retained.
Used numbers for footnotes,
placing them all at the end of
the paragraph.
*** END OF THE PROJECT GUTENBERG EBOOK THE JOURNAL OF
THE AMERICAN-IRISH HISTORICAL SOCIETY (VOL. VIII) ***

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