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CheckYourUnderstanding FSM Intro Lec 18 Aut22 Ee721 Hdls Onenb

The document outlines modifications to a finite state machine (FSM) for recognizing the sequence '1101' instead of '1011' and describes a variant of a sequential shift-add binary multiplier FSM. It details the states and logic for the FSM, including the initialization and operations during the 'stAdd' and 'stShift' states, along with the necessary VHDL code snippets. The document emphasizes the need for combinational logic and synchronous updates for the registers involved in the FSM operations.

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15 views2 pages

CheckYourUnderstanding FSM Intro Lec 18 Aut22 Ee721 Hdls Onenb

The document outlines modifications to a finite state machine (FSM) for recognizing the sequence '1101' instead of '1011' and describes a variant of a sequential shift-add binary multiplier FSM. It details the states and logic for the FSM, including the initialization and operations during the 'stAdd' and 'stShift' states, along with the necessary VHDL code snippets. The document emphasizes the need for combinational logic and synchronous updates for the registers involved in the FSM operations.

Uploaded by

omkarsutar8991
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Tuesday, October 11, 2022 11:11 AM

( CYU ) CheckYourUnderstanding about brief exposure to FSM from Lec-18-Mon-


10-Oct-2022-ee721

Q.1) Modify the FSM shown in Lec-18 ( for the variant of "1011" recognizer ) to instead recognize
"1101". Write the corresponding VHDL code following the pattern shown in Lec-18 for "1011"
recognizer.
Q.2) Following the outline of sequential-shift-add-binary-multiplier FSM shown in Lec-18 ( also recalled
here below for clarity of notation ), do similar exercise for a variant in which "shifting and adding"
happens during same clock cycle.
Consider the outline ( as described in Lec-18-Mon-10-Oct-2022-ee721 ) of sequential ( school-grade-like
) multiplier of a pair of unsigned binary numbers, a multiplicand ( mcnd ) and a multiplier ( mplr ).
It is a "shift-add" multiplier, where "add/accumulate" and "shift" are being performed in different clock
cycles, even though it is possible to perform them both in same clock cycle.
Therefore, as synchronous-sequential-algo-designer, we plan to use two states, namely, "stAdd" and
"stShift".
As you could see from the outline of this FSM, discussed in Lec-18, that we will need following registers
to hold state of the datapath. Namely, "acc" ( accumulator ), "mcnd_shifted" ( suitably shifted version
of multiplicand ), "count" ( to keep track of iterations, and also to pick the appropriate bit of the
multiplier ), register named "done" that indicates whether results are available in accumulator or not.
And of course, register named "present_state".
We will need signals that carry the nextCC values of these registers, namely, next_acc, next_count,
next_mcnd_shifted, next_done, next_state.

During the clock-cycles, when the algorithm FSM is in the state "stAdd", the following combinational
logic is evaluated.
case ( present_state ) is
.....................
when stAdd => compute the value nextAcc, which would be put inside accumulator Acc in the
next clock cycle, as follows :
if ( presently_considered_bit of multiplier = '1' ) then
nextAcc <= Acc + suitably _shifted_version_of_multiplicand
end if ;
nextState <= stShift ; -- state of the FSM in the next clock cycle
.....................

end case ;

During the clock-cycles, when the algorithm FSM is in the state "stShift", the following combinational
logic is evaluated.
case ( present_state ) is
....................
when stAdd => ................ -- as shown above .........
when stShift => compute the value next_mcnd_shifted, which would be put inside the register
that presents shifted_version_of_multiplicand in the next clock cycle, as follows :
if ( not all_iterations_are_over ) then
next_mcnd_shifted <= mcnd_shifted << 1 ; -- left shift by 1 bit
next_count <= count + 1 ;
next_state <= stAdd ; -- in next clock cycle go to state stAdd
else
next_done <= '1' ; -- in the next clock cycle, assert high "done" flag
next_count <= 0 ;
next_state <= stInit ; -- in next clock cycle go the beginning of algo FSM
end if ;
.....................

end case ;

What about the initial state of this FSM ? Let's call it stInit. The FSM remains in this state until "reset" is
deasserted ( or we could use a "start" signal ).

case ( present_state ) is
when stInit =>
if ( start signal is still not asserted ) then
next_state <= stInit ; -- in next clock cycle continue stay in state stInit
else -- initialize
nextAcc <= 0 ; -- in next clock cycle, accumulator register would be 0
next_mcnd_shifted <= mcnd ;
-- next CC, multiplicand will appear in the register mcnd_shifted
nextCount <= 0 ; -- in next CC, register holding count will be set to 0
next_done <= '0' ;
next_state <= stAdd ; -- in next clock cycle go stAdd
end if ;
when stAdd => ................ -- outlined as above .........

when stShift => ................ -- outlined as above .........

end case ;

Note that above vhdl-like code snippets describe combinational logic portions only. So they will be
inside a combinational process, like the following :

process ( present_state , mplr, mcnd, mcnd_shifted, count , start , .... ) begin


-- initialize the default values for signals driven combinationally
next_acc <= acc ; next_done <= done ; next_count <= count ;
next_mcnd_shifted <= mcnd_shifted ; ....
next_state <= present_state ;
case ( present_state ) is
when stInit => ..................
when stAdd => ..................
when stShift => ..................
end case ;
end process ;

And of course, we also need the following synchronous updates of registers acc, mcnd_shifted, count

process ( clk ) begin


if rising_edge( clk ) then
add <= nextAcc ; mcnd_shifted <= next_mcnd_shifted ; count <= nextCount ;
done <= next_done ;
present_state <= next_state ;
end if ;
end process ;

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