RF Transceiver Design

Lecture 1
Basics of Wireless Communication – I

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
Why this course?
Impact on ElectronicsIndustry.
▪ 5G
▪ Vehicular Radar
▪ IoT
▪ Satellite Communication
▪ Defence

2
Market Overview

Source: https://www.databridgemarketresearch.com/reports/global-rf-power-semiconductor-market

3
4
Various disciplines are necessary for RF design.

Communication
Theory Random
Microwave
Theory Signals

Signal Transceiver
Propagation RF Design Architectures

Multiple
IC Design
Access
Wireless CAD
Standards Tools

5
Chart of the electromagnetic wave spectrum
THz Photonics
Electronics

Microwaves Visible X-ray γ-ray

MF, HF, VHF, UHF, SHF, EHF

Frequency
(Hz)

100 103 106 109 1012 1015 1018 1021

Kilo Mega Giga Tera Peta Exa Zetta

Applications: Radio Radar ?? Optical Medical Astrophysics

Communications Communications Imaging

6
STANDARD DEFINITIONS OF RADIO SPECTRUM SEGMENTS
Name Frequency Range Applications
Low Frequency (LF) 30 to 300 kHz Navigation, time standards
Medium Frequency (MF) 300 kHz to 3 MHz Marine/aircraft navigation, AM broadcast
High Frequency (HF) 3 to 30 MHz AM broadcasting, mobile radio, Amateur
radio, Shortwave broadcasting
Very High Frequency (VHF) 30 to 300 MHz Land mobile, FM/TV broadcast, Amateur
radio
Ultra High Frequency (UHF) 300 MHz to 3 GHz Cellular phones, Mobile radio, Wireless
LAN, PAN
Super High Frequency (SHF) 3 to 30 GHz Satellite, Radar, Backhaul, Experimental,
Millimeter-wave range 5G cellular
Extremely High Frequency 30 to 300 GHz Satellite, Radar, Backhaul, Experimental,
(EHF) 5G cellular

Terahertz, Tremendously High

Frequency (THF) or Far Infrared 300 GHz to IR R & D, Experimental
(FIR)

7
 STANDARD DEFINITIONS OF RADIO SPECTRUM SEGMENTS
Band Frequency range Applications
L 1 to 2 GHz Satellite, navigation (GPS, etc.), cellular phones
S 2 to 4 GHz Satellite, SiriusXM radio, unlicensed (Wi-Fi, Bluetooth, etc.),
cellular phones
C 4 to 8 GHz Satellite, microwave relay, Wi-Fi, DSRC
X 8 to 12 GHz Radar
KU 12 to 18 GHz Satellite TV, police radar
K 18 to 26.5 GHz Microwave backhaul
Ka 26.5 to 40 GHz Microwave backhaul, 5G cellular
Q 30 to 50 GHz Microwave backhaul, 5G cellular
U 40 to 60 GHz Experimental, radar
V 50 to 75 GHz New WLAN, 802.11ad/WiGig
E 60 to 90 GHz Microwave backhaul
W 75 to 110 GHz Automotive radar
F 90 to 140 GHz Experimental, radar
D 110 to 170 GHz Experimental, radar

8
Comparison of 4G, 5G, and 6G communication standards
Issue 4G 5G 6G
Per device peak
1 Gbps 10 Gbps 1 Tbps
data rate
E2E latency 100 ms 10 ms 1 ms

Maximum spectral
15 bps/Hz 30 bps/Hz 100 bps/Hz
efficiency

Up to 350 Up to 500 Up to 1000

Mobility support
km/hr km/hr km/hr

Satellite
No No Fully
integration
AI No Partial Fully
Autonomous
No Partial Fully
vehicle
XR No Partial Fully
Haptic
No Partial Fully
Communication

9
FMCW Radar on-chip (240 GHz)*

*Fraunhofer FHR
Source: https://www.fhr.fraunhofer.de/en/the-institute/core-competencies/High-frequency-systems/High-Resolution-240-GHZ-Radar-with-SiGe-Chip.html

10
Packaging and interconnects

Source: https://www.fhr.fraunhofer.de/en/the-institute/core-competencies/High-frequency-systems/High-Resolution-240-GHZ-Radar-with-SiGe-Chip.html

11
Atmosphere effect

http://web.tiscali.it/decartes/phd_html/node2.html

12
 Rain attenuation

• Attenuation increases with frequency

(mm-wave) and rain rate.
• Problem for long-distance
communication (e.g. Satellite Links)

Source: https://www.sciencedirect.com/science/article/abs/pii/B9780128097328000077

13
Pros & Cons of mmWave Source: I. A. Hemadeh, K. Satyanarayana and M. "Millimeter-
Wave Communications: Physical Channel Models, Design
Considerations, Antenna Constructions, and Link-Budget," in
IEEE Communications Surveys & Tutorials, vol. 20, no. 2, pp.
870-913

14
 Acharya J C Bose
• In 1865 – Maxwell’s Equations
• In 1888 – Hertz demonstrated the generation of EM
waves.
• In 1895 – Bose demonstrated mm-Wave transmission.
• In 1901 – Marconi demonstrated wireless
communication

J C Bose demonstrated the world's first mm-Wave/ Wireless

Communication System.
- Transmission and Reception of 2.5 cm (~12 GHz) to 5 mm
(60 GHz) wavelength over the 23 meters distance

15
History

Worlds’ first mmWave system

Jagadish Chandra Bose Museum - Bose Institute - Kolkata

16
Experimental Setup

17
Original Setup Point Contact detector
Radiator

Different Polarisers used by Bose

18
 RF Transceiver Design
Lecture 2
Basics of Wireless Communication – II

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
Millimeter-wave applications
• Mm-Wave Spectrum
– Highly Directional (Pencil beam)
– Point-to-point communications, inter-satellite links, and point-to-multipoint
communications.
– Alternative of fiber optics.
– 38.6—40.0 GHz band for licensed high-speed microwave data link
– IEEE 802.11ad Wi-Gig technology - 60 GHz Wi-Fi standard (data transfer rate 7 Gbps)
• Automotive Radar
• mm-Wave Imaging
– Object Detection
– Tumor detection, temperature measurements,
blood flow and water/oxygen content measurements

2
Millimeter-wave applications Commercial Apps

▪ 802.11x Markets
Commercial

➢ WLAN
➢ WPAN
▪ Automotive Radar at 77/79 GHz
▪ Telecommunications backhaul
▪ Consumer
▪ Wireless Last Mile …

Integrated
▪ Military Markets (38, 60, 94 GHz) Wireless
➢ Future Combat systems
Military

➢ Secure communications
➢ Satellite Communications
➢ Military phased array markets
➢ Reconfigurable, software definable systems

3
THz Imaging

4
 Radio Astronomy
• Scientific Research:
– Radio astronomy and remote sensing: ground-based radio astronomy is limited to
high-altitude sites due to atmospheric absorption issues
– Satellite-based remote sensing near 60 GHz can determine the temperature in the
upper atmosphere by measuring radiation emitted from oxygen molecules that is a
function of temperature and pressure.

https://www.sciencenews.org/wp-content/
uploads/2021/08/100-worlds_spotlight-radio_feat

5
Remote Sensing

Source: https://crisp.nus.edu.sg/~research/tutorial/intro.htm

6
Key Challenges for Silicon RFIC Circuits
▪ Lossy silicon substrate → poor isolation, lower Q components.

▪ Need for a predictive design kit such that 1st pass success is achievable.
➢ Accurate transmission line and transistor models.
➢ Accurate parasitic extraction (the distinction between device and parasitic blurred).
➢ Silicon CAD tools (e.g., Cadence with EM simulation).

▪ Need to yield circuits in the silicon environment → density requirements on metal, poly,
and active layers. Effect on RF performance of passives?

▪ Achieving very high levels of integration in silicon while maintaining

MMW functionality.

7
 RFIC Design Flow

Design Decide Design Design Post layout Send For Testing of

Specific- Technology Schematic Layout Simulations Fabrication chip
ation from •CMOS (14nm to •Simulate desired •Complete DRC •Compare results •More than 20 •Probe Testing
Link Budget 180nm) parameters (Design Rule between steps process. •PCB Testing
•BiCMOS •Monte Carlo and Check) Schematic and •Photolitho- •PCB+Probe
•Frequency/BW corner variations •Complete LVS RCX file graphy Testing
•Power (Layout vs •Modify design
•Gain Schematic) accordingly
•Noise Figure •Complete RCX (R
and C Extraction)

8
 RF Transceiver Design
Lecture 3
Basics of Wireless Communication - III

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
General Consideration

2
Outline
Wireless Multiple Access
Modulation Mobile Systems
Standards Techniques
• AM,PM,FM • Cellular Systems • GSM • Duplexing
• ISI • Hand-off • IS-95 CDMA • FDMA
• Symbol • Multipath Fading • Wideband CDMA • TDMA
Constellation • Diversity • Bluetooth • CDMA
• ASK, PSK, FSK • IEEE 802.11
• QPSK, GMSK, a/b/g
QAM
• OFDM
• Spectral
Regrowth

3
Generic Communication

Transmitter Receiver
Baseband Medium/ Signal
Modulator Demodulator
Signal Channel Reconstruction

0 -ωc 0 ωc
Baseband Signal Passband Signal

x(t) = a(t) cos[ωct + ϴ(t)]

4
Impact of Modulation in RF system Design
❖ Detection of signal:
1 0 1 00 11 10 00

❖ Bandwidth Impact:
The bandwidth occupied by the modulated carrier for
a given information rate in the baseband signal. i.e. WiFi (
22 MHz BW)
❖ Power Impact:
PA design for linear vs. nonlinear

5
Amplitude Modulation sAM(t) = Ac[1 + msBB(t)] cos ωct
sBB (t)

X
t t
Ac cos ωct

SBB (f) SAM(f)

0 ω -ωc 0 ωc -ωc 0 ωc

6
Angle Modulation :Phase and Frequency Modulation
• If angle of carrier is modulated
s(t) = Ac cos (ωct + θ(t))
• Angle Modulation : Frequency or Phase is varying
• Phase Modulation :
Angle is directly proportional to baseband signal
• → θ(t) =msBB(t)
• Frequency Modulation
Phase is proportional to integral of baseband signal
𝑡
→ θ(t) =m‫׬‬−∞ sBB(t)d𝜏

7
DIGITAL MODULATION
• The carrier is modulated by a digital baseband signal.
1 0

t t
1 0

t t

sPSK(t) = Accos ωct if data = 0

= Accos(ωct + 180) if data = 1 t

8
Two basic concepts in digital communications
• Intersymbol interference (ISI):
Linear time-invariant systems can “distort” a signal if they do not provide
sufficient bandwidth.

• A signal cannot be both time-limited and bandwidth

limited:
• The time-limited pulse passes through the band-limited
system, the output must extend to infinity in the time
domain.
9
Cont.. sBB(t)= σ∞
𝑛=0 𝑎𝑛 𝑝(𝑡 − 𝑛𝑇𝑏)
sBB (t)
2
𝑆𝑖𝑛 π𝑓𝑇𝑏
Px(f) = 𝑇𝑏
π𝑓𝑇𝑏

Px(f) Q. if this signal is applied to a low-pass filter having

Effect of LPF Tb a narrow bandwidth, e.g., 1/(2Tb)?
A. Since the frequency components above 1/(2Tb)
are suppressed, the signal experiences substantial ISI

10
Solution ISI
• Reduce BW of the modulated signal.
• The sharp transitions between ZEROs and ONEs lead to an unnecessarily
wide bandwidth
• Pulse Shaping: It reduces the BW of the pulse.

s (t) Px(f)
Tb

sinc2

11
• Why cant we use the Sinc function in the time domain?
• Yes. Sinc in the time domain gives a “Bricwall” spectrum in the frequency domain.
• Spectrum occupies less BW.

s (t)
The waveform is sampled at exactly
integer multiples of Tb, then ISI is
zero .

s (t)
Nyquist
signaling

12
 RF Transceiver Design
Lecture 4
Basics of Wireless Communication – IV

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
Pulse shape P(f)
P(t)

t f

• A common pulse shape is

• It exhibits a “raised-cosine” spectrum, α is a roll of factor

– 𝛼 = 0, the pulse reduces to a sinc
– 𝛼 = 1, the spectrum becomes relatively wide
• Typical values of α are in the range of 0.3 to 0.5.
2
Signal Constellations
• “Signal constellations” allow us to visualize modulation schemes and, more
importantly, the effect of nonidealities on them.

𝑠𝑃𝑆𝐾 𝑡 = 𝑏𝑛 𝑐𝑜𝑠𝜔𝑐 𝑡 𝑏𝑛 = ±1

-1 0 +1
Ideal

0 +1 bn
Noisy

3
FSK Constellation
• An FSK receiver must decide whether the received frequency is ω1 (i.e., b1 = 1,
b2=0) or ω2 (i.e., b1 = 0, b2 = 1)
𝑠𝑃𝑆𝐾 𝑡 = 𝑏1 𝑐𝑜𝑠𝜔1 𝑡 + 𝑏2 𝑐𝑜𝑠𝜔2 𝑡 𝑏1 𝑏2 = 10 or 01
• PSK signals are less susceptible to noise than FSK signals because their
constellation points are farther from each other.
𝒃𝟐 𝒃𝟐
Ideal Noisy

𝒃𝟏 𝒃𝟏

4
EVM
• the “error vector magnitude” (EVM) is a measure of Representing the deviation
of the constellation points from their ideal positions.
• The EVM is defined as the rms magnitude of these error vectors normalized to
the signal rms voltage:
• to express EVM in decibels, we compute 20 log EVM1 or 10 log EVM2
𝒃𝟐

𝒃𝟏

5
Quadrature Modulation
• PSK signal without pulse shaping BW > 2/Tb
• PSK signal with pulse shaping BW=2/Tb
• How to reduce the BW? -> Quadrature Modulation
• “Quadrature PSK” (QPSK) Generation
𝑠 𝑡 = 𝑏2𝑚 𝐴𝑐 𝑐𝑜𝑠𝜔𝑐 𝑡 − 𝑏2𝑚+1 𝐴𝑐 𝑠𝑖𝑛𝜔𝑐 𝑡 Bit Rate

S/P
Converter +

Symbol Rate
• QPSK modulation halves the occupied bandwidth.
6
QPSK Constellation

• we assume bits 𝑏2𝑚 and 𝑏2𝑚+1 are pulses with a height of ±1

𝑠 𝑡 = α1𝐴𝑐 𝑐𝑜𝑠𝜔𝑐 𝑡 + α2𝐴𝑐 𝑠𝑖𝑛𝜔𝑐 𝑡
• More generally, the pulses appearing at A and B in Figure
are called “quadrature baseband signals”
• It denoted by I (for “in-phase”) and Q (for quadrature).
For QPSK, 𝐼 = 𝛼1 𝐴𝑐 and 𝑄 = 𝛼2 𝐴𝑐

7
Drawback of QPSK stems
Abrupt phase transition

S/P
Converter

square baseband pulses

shaped baseband pulses

A variable-envelope signal requires a linear power amplifier

8
GMSK and GFSK Modulation
• Constant-Envelope Modulation -> High Power Efficient
• FSK Generation
sBB (t) sFSK (t)

VCO

• GMSK Signal Generation

sBB (t) sGMSK (t)
Gaussian
VCO
Filter

• GMSK is used in GSM cell phones as well as in Bluetooth

9
QAM
• Spectral efficient
𝑠16𝑄𝐴𝑀 𝑡 = α1𝐴𝑐 𝑐𝑜𝑠𝜔𝑐 𝑡 − α2𝐴𝑐 𝑠𝑖𝑛𝜔𝑐 𝑡

+ + + +

+ + +

• This type of modulation requires a highly-linear power

amplifier.
10
QAM
• The concept of QAM can be extended to even denser constellations.
• if eight consecutive bits in the binary baseband stream are grouped and,
accordingly, each quadrature component of the carrier is allowed to have eight
possible amplitudes, then 64QAM is obtained.
• Several applications employ QAM to save bandwidth. For example,
IEEE802.11g/a uses 64QAM for the highest data rate (54 Mb/s).

11
 RF Transceiver Design
Lecture 5
Basics of Wireless Communication – V

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
Multipath fading

2
• The ISI resulting from multipath effects worsens for larger delay spreads or
higher bit rates.
• communication inside office buildings and homes begins to suffer from
multipath effects for data rates greater than 10 Mb/s.
• How does wireless communication handle higher data rates?
• An interesting method of delay spread mitigation is called “orthogonal
frequency division multiplexing” (OFDM)

3
Orthogonal frequency division multiplexing (OFDM)
Modulator

Modulator

Modulator

subchannel
subcarrier

4
• The “single-carrier” modulated spectrum -> occupies large bandwidth.
• In OFDM, the baseband data is first demultiplexed by a factor of N, producing N streams,
each having a (symbol) rate of rb/N.
• The N streams are then impressed on N different carrier frequencies, fc1-fcN, leading to a
“multi-carrier” spectrum.
• Due to low data rate in each sub-carrier, the modulated signal can tolerate delay spread.
• All of the subchannels utilize the same modulation scheme.
• IEEE802.11a/g employs 48 subchannels with 64QAM in
Each for the highest data rate (54 Mb/s).
• Thus, each subchannel carries a symbol rate of
(54 Mb/s)/48/8=141 ksymbol/s

5
OFDM Linearity Requirement

• OFDM imposes severe linearity requirements on power amplifiers.

• “peak-to-average ratio” (PAR) is a quantitative measure of the signal’s
envelope variations.
• PAR is defined as the ratio of the largest value of the square of the
signal (voltage or current) divided by the average value of the square
of the signal:

6
Three effects lead to a large PAR
• Pulse shaping in the baseband.
• Amplitude modulation schemes such as QAM.
• Orthogonal frequency division multiplexing.
• For N subcarriers, the PAR of an OFDM waveform is about 2 ln N if N is large.
• Spectral Regrowth
– This effect corrupts the adjacent channels.

7
𝑠 𝑡 = 𝐴𝑐 𝑐𝑜𝑠𝜔𝑐 𝑡 + 𝜙 𝑡
𝑠𝑜𝑢𝑡 𝑡 = 𝛼3 𝑠 3 𝑡
𝛼3 𝐴3𝑐 3𝛼3 𝐴3𝑐
= cos 3𝜔𝑐 𝑡 + 3𝜙 𝑡 + [𝑐𝑜𝑠𝜔𝑐 𝑡 +𝜙 𝑡 ]
4 4

t t

ω 𝑠𝑜𝑢𝑡 𝑡 = 𝛼3 [𝑆𝐼 𝑡 𝑐𝑜𝑠𝜔𝑐 𝑡 − 𝑆𝑄 𝑡 𝑠𝑖𝑛𝜔𝑐 𝑡]3

ω 3
𝛼 𝑠3 𝑡 𝛼3 𝑠𝑄 𝑡
= 3 4𝐼 𝑐𝑜𝑠3𝜔𝑐 𝑡 + 3𝑐𝑜𝑠𝜔𝑐 𝑡 − ሺ−𝑐𝑜𝑠3𝜔𝑐 𝑡 +
4
3𝑠𝑖𝑛𝜔𝑐 𝑡ሻ

t t

ω ω
𝑠 𝑡 = 𝑆𝐼 𝑡 𝑐𝑜𝑠𝜔𝑐 𝑡 − 𝑆𝑄 𝑡 𝑠𝑖𝑛𝜔𝑐 𝑡

8
MOBILE RF COMMUNICATIONS
• Each mobile receives and transmits information from and to the base station
via two RF channels called the “forward channel” or “downlink” and the
“reverse channel” or “uplink,” respectively.
• Cellular System :
– limited available spectrum (e.g., 25 MHz around 900 MHz)
– In mobile communications, the concept of frequency reuse is implemented in a “cellular”
structure

f1 f1
f2
f1 f1 f1 f1 f2
f1
f1 f1

9
Co-Channel Interference (CCI)
• A base station serves the mobile units in each cell, and all base stations are
controlled by a “mobile telephone switching office” (MTSO).
• CCI effect depends on the distance ratio between two co-channel cells to the cell
radius and is independent of the transmitted power.
• Given the frequency reuse plan, this ratio is approximately 4.6 for the 7-cell
pattern.
• It can be shown that this value yields a signal-to-co-channel interference ratio of
18 dB f1 f1

f1

f1 f1

10
• Hand-off

MTSO

• Multipath fading

• Overcome path loss & Strong multipath fading:

– The transmitter output power
– The receiver dynamic range

11
• Diversity
– “Space diversity” or “antenna diversity” employs two or more antennas spaced
apart by a significant fraction of the wavelength to achieve a higher probability of
receiving a non-faded signal.
– “Frequency diversity” refers to the case where multiple carrier frequencies are
used, with the idea that fading is unlikely to co-occur at two frequencies sufficiently
far from each other.
– “Time diversity” is another technique whereby the data is transmitted
Or received more than once to overcome short-term fading.

• Delay Spread
• many signals arrive at the receiver with different delays, yielding
rms delay spreads as large as several microseconds and hence
fading bandwidths of several hundreds of kilohertz. Thus, an
entire communication channel may be suppressed during such a
fade.

12
MULTIPLE ACCESS TECHNIQUES

RX
Time-division duplexing (TDD)
TX

Base
Station
TX TX

RX RX

Frequency-division duplexing (TDD)

13
 RF Transceiver Design
Lecture 6
Basics of Wireless Communication – VI

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
MULTIPLE ACCESS TECHNIQUES

RX
Time-division duplexing (TDD)
TX

Base
Station
TX TX

RX RX

Frequency-division duplexing (TDD)

2
• TDD:
▪ TDD allows direct (“peer-to-peer”) communication between two transceivers, a handy feature
in short-range, local area network applications.
▪ The primary drawback of TDD is that the strong signals generated by all of the nearby mobile
transmitters fall in the receive band, thus desensitizing the receiver.
• FDD:
▪ Two front-end band-pass filters are combined to form a “duplexer
filter.”
▪ Components of the transmitted signal that leak into the receive
band are attenuated by typically only about 50 dB
▪ Owing to the trade-off between the loss and the quality factor of
filters, the loss of the duplexer is typically quite higher than that of
a TDD switch.
▪ The spectral leakage to adjacent channels in the transmitter
output.

3
Frequency-Division Multiple Access
• the available frequency band can be partitioned into many channels,
each assigned to one user.

200 kHz in GSM 25 MHz in GSM

• Note that in FDMA with FDD, two channels are assigned to each user,
one for transmit and another for receive.
• In multiple-user, two-way communications, on the other hand, the
channel assignment may remain fixed only until the end of the call

4
Time-Division Multiple Access

Transceiver 1

Transceiver 2

Transceiver N

5
Code-Division Multiple Access
• A certain code is assigned to each transmitter-receiver pair
• each bit of the baseband data is “translated” to that code before modulation

Walsh’s code

DS-CDMA

• A method of generating orthogonal codes is based

on Walsh’s recursive equation

6
How is the received data affected when another CDMA
signal is present?
• Two CDMA signals 𝑥𝐵𝐵1 (𝑡) and 𝑥𝐵𝐵2 (𝑡) are received

• Thus, if 𝑊1 (𝑡) and 𝑊2 (𝑡) are exactly orthogonal, then

• 𝑥𝐵𝐵1 (𝑡) and 𝑥𝐵𝐵2 (𝑡) -> Experience different delays -> corruption of y(t)
by 𝑥𝐵𝐵2 𝑡 -> long codes are used.
• CDMA is a special case of “spread spectrum” (SS) communications.
• The baseband data of each user is spread over the entire available
bandwidth.

7
• CDMA is also called “direct sequence” SS (DS-SS) communication and the code is called
the “spreading sequence” or “pseudo-random noise.”
• each pulse in the spreading sequence is called a “chip.”
• the rate of the sequence is called the “chip rate.”

8
• An important feature of CDMA is its soft capacity limit.
• In FDMA and TDMA, the maximum number of users is fixed.
• In CDMA, increasing the number of users only gradually (linearly) raises the
noise floor.
• Near/far effect: the strong interferer greatly raises the noise floor, degrading
the reception of the desired signal
• Power control is a must for multiple transmitters.

De-spreader

9
Frequency-Hopping CDMA
• This access technique can be viewed as FDMA with pseudo-random channel
allocation.
• The carrier frequency in each transmitter is “hopped” according to a chosen
code (similar to the spreading codesin DS-CDMA).
• FH may require relatively fast settling in the control loop of the oscillator.

Oscillator

10
WIRELESS STANDARDS
The typical specifications that standards quantify:
• Frequency Bands and Channelization:
Bluetooth uses the industrial scientific-medical (ISM) band from 2.400 GHz to 2.480 GHz.
Bluetooth incorporates a channel of 1 MHz, allowing at most 80 users.
• Data Rate(s):
The standard specifies the data rate(s) that must be supported.
• Antenna Duplexing Method.
FDD / TDD
• Type of Modulation.
IEEE802.11a/g utilizes 64QAM for its highest rate (54 Mb/s)

11
• TX Output Power.
▪ The standard specifies the power level(s) that the TX must produce.
For example, Bluetooth transmits 0 dBm.
▪ Some standards require a variable output level to save battery power
when the TX and RX are close to each other and/or to avoid near/far
effects.
• TX EVM and Spectral Mask.
The signal transmitted by the TX must satisfy several requirements besides the
power level.
▪ To ensure acceptable signal quality, the EVM is specified.
▪ To guarantee that the TX out-of-channel emissions remain sufficiently
small, a TX “spectral mask” is defined. Excessive PA nonlinearity may
violate this mask.
▪ The standard limits other unwanted transmitted components, e.g.,
spurs and harmonics.

12
• RX Sensitivity.
The standard specifies the acceptable receiver sensitivity, usually in terms of a maximum bit error rate,
BERmax.
• RX Input Level Range.
The desired signal sensed by a receiver may range from the sensitivity level to a much larger value.
• RX Tolerance to Blockers.

Receiver

2ω1-ω2 ω1

Receiver

13
 RF Transceiver Design
Lecture 7
Noise in RF Systems – I

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
Units in RF A𝑉(𝑑𝐵) = 20 𝑙𝑜𝑔
Vout
Vin
Ex1: An amplifier senses a sinusoidal and delivers a power of
Pout
0 dBm to a load resistance of 50 ohms. Determine the peak- A𝑝(𝑑𝐵) = 10 𝑙𝑜𝑔
Pin
to-peak voltage swing across the load. V2out/Ro
= 10 𝑙𝑜𝑔
V2in/Ro
V
= 20 𝑙𝑜𝑔 out
Vin
= A𝑉 (𝑑𝐵)

Valid only when the input and

output matched to Ro

2
Units in RF Pin Pout Vin Vout
➢ dBm --> Relative to 1mW power
Pout Vout
Pin dB--> Power gain= 10 log Voltage gain= 20 log
Pin Vin
10 log
1mW 30 dBm Gain=10 dB
0 dBm, If Pin= 1mW Pin Pout = 30 dBm+10 dB = 40 dBm

(1000mW) 30 dBm
+ dBm+dBm= ?
(100mW) 20 dBm

Pin 30 dBm
➢ dBw → Relative to 1W power 10 log 1W
➢ dBc → Decibels relative to the carrier power 30 dBc

-20 dBm

3
Noise
▪ Noise is a Random Process
• Generated due to the flow of charge carriers in any conductor or
semiconductor.
• Generated through vibrations.
• It can be generated externally or internally within the system.
▪ If there is no input to the amplifier and there is still output power,
then this is called as a Noise Floor of the system.
▪ Typical value can be less than -100 dBm over the BW of the system.
▪ Noise is generated by the random motion of charge carriers in
devices or materials.

4
Noise Sources:
▪ Shot Noise:
• Random fluctuation of charges in electron tubes or solid-state devices.
▪ Thermal Noise:
• Basic Noise
• Caused by thermal vibration of charges
• Known as Johnson or Nyquist noise
▪ Flicker Noise:
• Due to trap charges, and mostly happens in solid-state
components.
• Vn∝ 1/f
▪ Plasma Noise:
• Due to plasmons caused by the random motion of charges
in an ionized gas, sparking electrical components.
5
▪ Quantum Noise:
• It is very insignificant and results from quantized the number of photons and charge
carriers.
▪ Burst Noise (Popcorn Noise):
• It is a low-frequency noise found in integrated circuits and discrete transistors.
• It is due to heavy-metal ion contamination.
• Gold-doped devices show very high burst noise.
• Popping sound when played through a loudspeaker.
▪ Avalanche Noise:
• This is produced by Zener or avalanche breakdown in a pn
junction.
• The cumulative electron-hole recombination process by
colliding Si atoms creates large noise spikes.
• The noise is always associated with a direct-current flow,

6
Shot Noise
• It is associated with a direct-current flow and is present in diodes, MOS transistors, and
bipolar transistors.
• The current I is composed of a series of
random independent pulses with average
value ID, then the mean-square value of noise
current is 𝑖ഥ2 = 2𝑞𝐼𝐷 Δ𝑓
Where q is the electronic charge (1.6 × 10−19 C), and Δf is the
bandwidth in hertz.

Junction diode small-signal equivalent circuit with noise.

7
Thermal Noise To K
• Random in nature
• The kinetic energy is proportional to
Temperature
• The average value of this noise voltage is
zero, but the RMS value given by Plank’s black
h → Plank’s constant
body radiation law is, K → Boltzmann constant
4ℎ𝑓𝐵𝑅
𝜈𝑛 = T → Temperature in degree oK
ⅇℎ𝑡/𝐾𝑇 − 1 B → BW in Hz
f → Centre Frequency
• At microwave frequency ℎ𝑡 ≪ 𝐾𝑇 R → Resistance
∴ ⅇℎ𝑡/𝐾𝑇 −1 ≈ ℎ𝑡/𝐾𝑇
∴ 𝜈𝑛 = 4𝐾𝑇𝐵𝑅
• This noise is independent of the
frequency.

8
• White Noise Source: PSD is constant with
frequency
• What is PSD?
x(t) 1Hz ( )2 →|xf1(t)|2
o The power present in the signal as a function
of freq. Sx(f)
o How much power the signal carries at each
frequency.
o The PSD Sx(f) of the waveform x(t) is defined
as the average power carried by filters with
center frequency f1 and 1Hz BW f1 f2 f3 f
o Units:

9
 2
𝑉𝑛2
𝑃𝑛 = 𝐼 𝑅 = 𝑅
2𝑅
𝑉𝑛2
= = KTB
4𝑅
• KTB is the maximum available noise power from a noisy
Thevenin’s equivalent circuit with a noiseless resistor
resistor at a temperature T oK

• Notes:
• B → 0, Pn → 0
• T → 0, Pn → 0
• B → ∞, P n → ∞
• If noise power is denoted by N0 and the equivalent temperature Te then,
N0 = KTeB
𝑁
∴ 𝑇𝑒 = 𝐾𝐵0

10
 RF Transceiver Design
Lecture 8
Noise in RF Systems – II

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
• White Noise Source: PSD is constant with
frequency
• What is PSD?
x(t) 1Hz ( )2 →|xf1(t)|2
o The power present in the signal as a function
of freq. Sx(f)
o How much power the signal carries at each
frequency.
o The PSD Sx(f) of the waveform x(t) is defined
as the average power carried by filters with
center frequency f1 and 1Hz BW f1 f2 f3 f
o Units:

2
 2
𝑉𝑛2
𝑃𝑛 = 𝐼 𝑅 = 𝑅
2𝑅
𝑉𝑛2
= = KTB
4𝑅
• KTB is the maximum available noise power from a noisy
Thevenin’s equivalent circuit with a noiseless resistor
resistor at a temperature T oK

• Notes:
• B → 0, Pn → 0
• T → 0, Pn → 0
• B → ∞, P n → ∞
• If noise power is denoted by N0 and the equivalent temperature Te then,
N0 = KTeB
𝑁
∴ 𝑇𝑒 = 𝐾𝐵0

3
 Amp 𝑁0
N0 Po = GKTB 𝑇𝑒 =
G 𝐺𝐾𝐵

• Active Noise Source:

• Diode, tube, or solid-state devices used to provide
calibrated noise output
• Useful in measurement
Excess Noise Ratio
𝑁𝑔−𝑁0
ENR (dB) = 10 log 𝑁0
𝑇𝑔−𝑇0
= 10 log 𝑇0

Ng → Noise power from the generator

N0 → Noise power from 50 ohms impedance at room
temperature
4
Measurement of Noise Temperature: Y factor Method
T1 > T2

5
Ex: For X-Band, the amplifier gain is 20 dB, and BW is 1GHz; find Te using the Y-
factor method with the following data.
T1= 290K, T2= 77K, N1= -62.0 dBm, N2= -64.7 dBm,

6
Noise Figure
• It measures the degradation of the signal-to-noise ratio between (SNR) the input and
output of the system.

𝑆𝑁𝑅 𝑆𝑖
• Noise figure (F) = 𝑆𝑁𝑅 in ≥ 1 𝑁𝑖
Noiseless
out

7
Noise Figure of a Cascaded System
Ni G1 N1 G2 No
F1 F2
T0 Te1 Te2

Ni G1 No
F1
T0 Te1

8
9
 RF Transceiver Design
Lecture 9
Noise in RF Systems – III

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
Noise Figure of a Cascaded System
Ni G1 N1 G2 No
F1 F2
T0 Te1 Te2

Ni G1 No
F1
T0 Te1

2
3
• Passive components don’t have a gain but the insertion loss L = 1/G > 1, G is gain.

4
Ex: a. Find the output noise power LNA BPF Mixer
in dBm.
b. If the minimum output SNR is 20dB,
then what is the input power?
Z0 = 50ohms, IF BW = 10MHz Si, Ni Ga = 10dB Lf = 1dB Lm= 3dB
Fa = 2dB Fm = 4dB

5
6
7
Useful for Noise Calculations

8
 RF Transceiver Design
Lecture 10
Noise in RF Systems – IV

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
Useful for Noise Calculations

2
3
 RF Transceiver Design
Lecture 11
Non-Linearity in RF Systems – I

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
Non-Linearity
▪ Memoryless or Static system: Output doesn’t depend on the past values of its input.
Pout (dBm)
▪ Dynamic Range and Sources of Noise Ideal
• All passive devices are linear at microwave frequency 30 1 dB
• Deterministic
Real

Ex: For the transistor amplifier, Pout = 10 Pin -70

Pin Pout -100

Pin (dBm)

▪ 1 – dB compression point: Defined as the input power for

which the output power is 1 dB below that of the ideal
amplifier.

2
3
1. Even order harmonics results from 𝛼𝑗 with even j vanishes if the system has odd symmetry
Ex: Fully differential amplifier
2. Amplitude of the harmonics proportional to the nth power of its amplitude (A2, A3,…., An)
3. The harmonics of the amplifier can be filtered out at RF frequencies
Gain Compression

20 log(Aout)

1 dB

20 log(Ain)

4
 RF Transceiver Design
Lecture 12
Non-Linearity in RF Systems – II

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
1. Even order harmonics results from 𝛼𝑗 with even j vanishes if the system has odd symmetry
Ex: Fully differential amplifier
2. Amplitude of the harmonics proportional to the nth power of its amplitude (A2, A3,…., An)
3. The harmonics of the amplifier can be filtered out at RF frequencies
Gain Compression

20 log(Aout)

1 dB

20 log(Ain)

2
3
Intermodulation
• Single signal: Harmonic Distortion
Large interferer (desensitization)
• Two Interferer signals: Two-Tone
ω1
nω1, nω2, nω1-ω2,
ω2 Non-Linear ω1-nω2

• Components that are not harmonics of this frequency are called “intermodulation.”

4
5
6
Third-order Intercept Point (IIP3)
Output
AOIP3

AIIP3 Input

7
 RF Transceiver Design
Lecture 13
Non-Linearity in RF Systems – III

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
Third-order Intercept Point (IIP3)
Output
AOIP3

AIIP3 Input

2
Ex: What IIP3 is required if the IM products must remain 20dB below the signal

3
Cascaded Non-Linear Stages
IIP3,1 IIP3,2
X(t) y1(t) y2(t)

4
5
6
Sensitivity
“ Minimum signal level that a receiver can detect with acceptable quality ”
𝑆𝑁𝑅𝑖𝑛 Sufficient SNR
𝑁𝐹 =
𝑆𝑁𝑅𝑜𝑢𝑡 • SNR requirement is based on the
✓ Modulation scheme
✓ Shannon capacity theorem
✓ Bandwidth
✓ Range
Typically it will be in the range of 6 to 25 dB

7
8
Dynamic Range
➢ It is defined as the maximum input level that a receiver can ‘tolerate’ divided by the
minimum input level that it can detect (sensitivity).

Maximum Input
that is possible
SFDR
Sensitivity Sensitivity

Compression based Interference based

1st order non-linearity

➢ Noise defines the lower limit (sensitivity)

➢ Interference/non-linearity/compression defines the upper limit

9
SFDR → Spurious Free Dynamic Range
➢ The maximum relative level of the interferers that a receiver can tolerate while producing an
Acceptable signal quality from a small input level.

10
11
RF Transceiver Design
Lecture 14
Transceiver Architecture – I

Prof. Darshak Bhatt

DEPARTMENT of Electronics & Communication

1
Aim of Receiver Design – 1 : Amplification

LNA ADC

• Weak signal is received at receiver.

• ADC requires higher input signal
• LSB/offset/input-referred noise -> Range of mV
• Requirement of High dynamic range.
• Higher sampling rate - 2fRF

2
Aim of Receiver Design – 2 : Variable Gain

LNA VGA ADC

• Requirement of High dynamic range :

• Sol: Variable gain of ∼ 0-100 dB.
• ADC detection range is limited ~ 6 dB/bit
• Power consumption increases if no of bits increased.
• Implementation of VGA (variable gain amplifier) at RF is challenging.
• Interfering signal limits the sensitivity.

3
 Aim of Receiver Design – 3 : Down Conversion
LNA VGA ADC

• Base-band frequencies are lower compared to RF frequency

• It reduces the power consumption.
▪ Up conversion – Down conversion
• It can be achieved by “Mixer / Multiplier
• Mixer -> Translate the frequency
-> Noisy (NF ∼ 10 dB).
-> Require Image rejection.
• As per the Friis Formula -> First component dominate the Noise
• LNA followed by mixer architecture is popular.

4
Aim of Receiver Design – 4 : Filtering

LNA VGA ADC

• Presence of in-band blockers

• Compression will reduced required SNR at output.
• Required Sharp filters to suppress the unwanted signal/interferers/blockers.
• Effect of blockers/interferers/jammers:
✓ Due to compression (P−1dB ), the gain of the signal (P−1dB ) reduced.
✓ NF of the receiver increases.
✓ Intermodulation will lower the sensitivity.

5
TRANSCEIVER ARCHITECTURES
Transmitted
Channel
Power
Amplifier

BPF
ω
Adjacent
(a) Channels
Band-Pass Adjacent
Filter Response Channel

Low Noise
Amplifier

BPF
r
r
f
Desired
Channel Alternate
Adjacent (b)
Channel

6
Channel Selection and Band Selection
• Linearity requirement to get rid of compression or excessive intermodulation.
• Filtering channel required very high Q filters.
• Band selection followed by channel selection after down conversion.

Desired
channel
LNA
BPF
Receive f
Band

7
full-duplex standards
TX RX
BAND BAND
-20dBm LNA
30dB

10dB/div
55dB
Duplexer

1W f2 f1
(+30dBm)
PA 20MHz/div

8
GSM Standard
935-960MHz

Duplexer LNA 200KHz

FDD
PA
f GMSK Digital Baseband
Modulator Signal (271kb/s)
890-915MHz

In-Band Blocker Levels Out-Of-Band Blocker Levels

0dBm

Desired -23dBm
Channel
-33dBm
-99dBm -43dBm
20MHz

f
0 600 1600 3000 Edge of Band (KHz)
9
Basic Heterodyne Receivers
LNA Mixer
RF BPF IF -ωin 0 ωin ω
INPUT Output

Local -ωLO 0 +ωLO ω

Oscillator

-ωin -ωLO +ωin -ωLO +ωin +ωLO

-ωin +ωLO 0 ω

10
RF Transceiver Design
Lecture 15
Transceiver Architecture – II

Prof. Darshak Bhatt

DEPARTMENT of Electronics & Communication

1
Basic Heterodyne Receivers
LNA Mixer
RF BPF IF -ωin 0 ωin ω
INPUT Output

Local -ωLO 0 +ωLO ω

Oscillator

-ωin -ωLO +ωin -ωLO +ωin +ωLO

-ωin +ωLO 0 ω

2
Problem of Image
Desired
Signal
Image

LPF
ωin ωim ω ωIF ω
ωIF ωIF
CosωLOt
-ωLO ω
ωim = ωin + 2ωIF = 2ωLO - ωin
Image Reject
LNA Filter
Image
Reject
Filter
ωin ωim
CosωLOt 2ωIF

3
 Image Rejection versus Channel selection
LNA Channel • A high IF allows substantial rejection of
Image
Select the Image, whereas a low IF helps with
Reject
Filter the suppression of in-band interferers.
Filter
Desired
Signal CosωLOt
Image Reject
Filter Image Channel Select
Interferer Filter

ωin ωim ω ωIF ω

2ωIF

2ωIF ω ωIF ω

4
Dual Down Conversion Channel IF
Band Image Channel Select Amplifier
Select Reject RF Mixer Select IF Mixer Filter
Filter LNA Filter MX1 Filter MX2
BPF1 BPF2 BPF3 BPF4
A B C D E F G H

ωLO1 ωLO2

5
Direct-Conversion Receivers
• Mixing Spurs: due to non-ideal mixing and LO generation. Mixing of RF input by all LO
harmonics.
ωint ± mωLO1 ± nωLO2 = ωin - ωLO1 – ωLO2

LPF I

LNA
BPF CosωLOt
ωin

LPF Q

SinωLOt

6
Self Image
Symmetrically-modulation Asymmetrically-modulation
S(f) S(f-fLO) xBB(t)
VCO
fc f
0 f fLO ω t

fLO f
-ωIF1 +ωIF1 ω

0 ω

7
Modern Heterodyne Receiver
• Heterodyne RX with quadrature down-conversion

LPF XBB,I(t)
LNA
BPF
ωin CosωLO2t

ωLO1
LPF XBB,Q(t)
• Sliding-IF Receivers SinωLO2t

LPF XBB,I(t)
LNA
BPF LO2,I
ωin
fLO1
LPF XBB,Q(t)
LO2,Q 𝑓𝐿𝑂1
LO1 ÷2 2
Example
𝑓𝐿𝑂1 2
𝑓𝐿𝑂1 + = 𝑓𝑖𝑛 𝑓𝐿𝑂1 = 𝑓𝑖𝑛
2 3
Mix2 BB
VGA
LPF XBB,I(t)
IF
Mix1
LNA VGA
I
ωin
BB
Mix2 VGA

LPF
48GHz XBB,Q(t)
PLL
4:1 12GHz Q

9
RF Transceiver Design
Lecture 16
Transceiver Architecture – III

Prof. Darshak Bhatt

DEPARTMENT of Electronics & Communication

1
Example
𝑓𝐿𝑂1 2
𝑓𝐿𝑂1 + = 𝑓𝑖𝑛 𝑓𝐿𝑂1 = 𝑓𝑖𝑛
2 3
Mix2 BB
VGA
LPF XBB,I(t)
IF
Mix1
LNA VGA
I
ωin
BB
Mix2 VGA

LPF
48GHz XBB,Q(t)
PLL
4:1 12GHz Q

2
LO Planning in Super-heterodyne
• Two separate VCOs and synthesizers are used.
• The IF LO is fixed,
• The RF LO is variable to down-convert the desired channel to the passband of the IF filter (SAW).
• This typically results in a 3-4 chip solution with many off-chip components.
• LO1 should never be close to an integer multiple of LO2 for any channel. The Nth harmonic of the fixed LO2
could leak into the RF mixer and cause unwanted mixing.

LO2 LO1
IF
nLO2 leaks
nLO2 Into RF mixer

IF
IF
3
The 1/2 IF Problem
LO
1/2IF

IF IF

• Assume that there is a blocker half-way between theLO and the desired channel. Due to second-
order non-linearity in the RF front-end:
2 2 1+cos 2ω𝐿𝑂+ω𝐼𝐹 𝑡
𝑚𝑏𝑙𝑜𝑐𝑘𝑒𝑟 𝑡 cos ω𝐿𝑂 + ω𝐼𝐹 𝑡 = 𝑚𝑏𝑙𝑜𝑐𝑘𝑒𝑟 (t) 2
• If the LO has a second-order component, then this signal will fold
right on top of the desired signal at IF:
2 2
𝑚𝑏𝑙𝑜𝑐𝑘𝑒𝑟 𝑡 cos 2ω𝐿𝑂 + ω𝐼𝐹 𝑡} cos 2ω𝐿𝑂 𝑡 = 𝑚𝑏𝑙𝑜𝑐𝑘𝑒𝑟 cos(ω𝐼𝐹 )t

4
Cont.
DC DC
1/2IF
1/2IF

IF
IF
• If the IF stage has strong second-order non-linearity, then the half-IF problem occurs
through this mechanism:
1 2
2{𝑚𝑏𝑙𝑜𝑐𝑘𝑒𝑟 𝑡 cos ( 2 ω𝐼𝐹 )} 2 = 𝑚𝑏𝑙𝑜𝑐𝑘𝑒𝑟 (t)+cos(ω𝐼𝐹 )t
• This highlights the importance of frequency planning.
• One should select the IF by making sure that there is no strong
half-IF blocker.
• If one exists, then the second-order non-linearity must be
carefully managed.

5
Heterodyne Architecture
➢ Disadvantages:
• Requires bulky off-chip SAW filters
• As before, two synthesizers are required
• Typically a three-chip solution (RF, IF, and Synth)
➢ Advantages:
• Robust. The clear choice for extremely high sensitivity radios High dynamic
range SAW filter reduces/relaxes the burden on active circuits. This makes it
much easier to design the active circuitry.
• The power consumption is lower.

6
Properties of Zero-IF Receiver
Merits:
• The absence of an image greatly simplifies the design process.
• Channel selection is performed by low-pass filters (on chip).
• Mixing spurs are considerably reduced in number and hence simpler to handle.
Demerits: LO Leakage

LNA
LNA Mixer
RF LO
INPUT

Local
Oscillator

7
DC Offsets Example:
Receiver Sensitivity = -80 dBm
VRF+KVLO
Pad LNA Mixer
VIF+VDC
Receiver Gain=80 dB
output desired power=0 dBm
LO leakage=-60 dBm
DC offset amplitude=20 dBm
Local HPF
Oscillator Frequency
Response
Baseband
LNA Mixer
A1 Signal
BPF C1
R
R1
1
Local
-f1 0 f1
Oscillator
Vb

8
Even-Order Distortion
Beat
Component
Interferers

0 ω1 − ω2 ω
LNA feedthrough

ω 0 ω

Local
Oscillator

• The problem of even-order distortion is critical enough to merit a

quantitative measure. Called the “second intercept point” (IP2).
• Measured by using Two-Tone analysis. However, the frequency of
interest is beat component

9
 (log scale)
• 𝑘𝛼2 𝐴2𝐼𝐼𝑃2 = 𝛼1 𝐴𝐼𝐼𝑃2
1
𝐴𝐼𝐼𝑃2 • 𝐴𝐼𝐼𝑃2 = 𝑘 𝛼1 /𝛼2
⍺1 𝐴

α2 𝐴2
𝐴𝐼𝐼𝑃2 𝐴𝑖𝑛
(log scale)

Flicker Noise (log scale)

𝑆1ൗ (𝑓)
𝑓

𝑆𝑡ℎ

𝑓𝐵𝑊 𝑓𝑐 𝑓𝐵𝑊 f
1000

10
• I/Q Mismatch:
Phase and Gain Error

LPF I Q Ideal

Phase and Gain

90⁰

Error
I
𝑉𝑅𝐹
𝑉𝐿𝑂

LPF Q

Phase and Gain Error

• Mixing Spurs:
• The issue of LO harmonics does manifest itself if the receiver is designed
for a wide frequency band (greater than two octaves). Examples include
TV tuners, “software-defined
radios,” and “cognitive radios.”
11
RF Transceiver Design
Lecture 17
Transceiver Architecture – IV

Prof. Darshak Bhatt

DEPARTMENT of Electronics & Communication

1
Hilbert Transform (90-degree phase shift)

Hilbert Transform
Im
+j A/2 +j X(ω) Im

A/2
-ωc X(ω)
Re -ωc
Re
A/2 X(ω)
+ωc
+ωc
-ω
-j A/2 -ω
-j X(ω)

2
Plot of I+jQ
• 𝐼 + 𝑗𝑄 = 𝐴𝑐𝑜𝑠𝜔𝑐 𝑡 + 𝑗𝐴𝑠𝑖𝑛𝜔𝑐 𝑡 = 𝑓(𝑡)

Im
Im
+j A/2

-ωc Re
-A/2 -ωc Re
-A/2
+ωc A
+ωc
-ω
-ω
-j A/2

3
Image-Reject Receivers
• Hartley Architecture

LPF 90ͦ
A

RF SinωLOt
Input
+ IF
Output
LPF
B

CosωLOt Desired
Channel
Image
RF
Input

-ω𝐿𝑂 0 +ω𝐿𝑂
4
 Desired
Image Channel
RF
Input

-ω𝐿𝑂 0 +ω𝐿𝑂
(ω)
(ω) 𝑗
𝑋𝐶
𝑋𝐴 𝑗
+2 +2 90ͦ

0 ω
0 ω

0 ω
𝑗 𝑗
− − 90ͦ
2 2
(ω)
0 ω
𝑋𝐵

IF
0 ω Output

0 ω
0 ω

5
6
• High Side LO injection

𝑗
+
1 1 2
+ +
2 2 −ω𝑐
−ω𝑐 +ω𝑐 +ω𝑐
1 1 𝑗 −ω𝐼𝐹
+ + + −ω𝐼𝐹 0
2 2 0 2
−ω𝐼𝐹 +ω𝐼𝐹 +ω𝑙𝑜
−ω𝐿𝑂 0 +ω𝑙𝑜 −ω𝐿𝑂 0 𝑗
−
𝑗 2
−
2

• Low Side LO injection

𝑗
𝑗 +
+ 2
2

−ω𝑐 0 +ω𝑐 −ω𝐼𝐹

𝑗 0
−ω𝑐 0 +ω𝑐 +
1 1 0 2 −ω𝐼𝐹
+
2
+
2 −ω𝐼𝐹 +ω𝐼𝐹 0 +ω𝑙𝑜
−ω𝐿𝑂 𝑗
0 +ω −
−ω𝐿𝑂 𝑗 2
𝑙𝑜 −
2

7
RCCR Filter

𝑉𝑜𝑢𝑡1 𝑅1 𝐶1 𝑠 𝜋
𝐻𝐻𝑃𝐹 𝑠 = =𝑅 < 𝐻𝐻𝑃𝐹 = − 𝑡𝑎𝑛−1 (𝑅1 𝐶1 𝜔)
𝑉𝑖𝑛 1 𝐶1 𝑠+1
2
𝑉𝑜𝑢𝑡2 1 < 𝐻𝐿𝑃𝐹 = −𝑡𝑎𝑛−1 (𝑅1 𝐶1 𝜔)
𝐻𝐿𝑃𝐹 𝑠 = =
𝑉𝑖𝑛 𝑅1 𝐶1 𝑠+1
𝜋
< 𝐻𝐻𝑃𝐹 − < 𝐻𝐿𝑃𝐹 =
2

8
Image Rejection
𝐴𝑠𝑖𝑔 𝐴𝑖𝑚
𝑋𝐴 𝑡 = cos[ 𝜔𝑐 − 𝜔𝐿𝑂 𝑡 + ∅𝑠𝑖𝑔 ] + cos[(𝜔𝑖𝑚 − 𝜔𝐿𝑂 )t + ∅𝑖𝑚 ]
2 2
𝐴𝑠𝑖𝑔 𝐴𝑖𝑚
𝑋𝐵 𝑡 = − sin 𝜔𝑐 − 𝜔𝐿𝑂 𝑡 + ∅𝑠𝑖𝑔 − sin[ 𝜔𝑖𝑚 − 𝜔𝐿𝑂 𝑡 + ∅𝑖𝑚 ]
2 2
𝐴𝑠𝑖𝑔 𝐴𝑖𝑚
𝑋𝐶 𝑡 = cos 𝜔𝑐 − 𝜔𝐿𝑂 𝑡 + ∅𝑠𝑖𝑔 − cos[ 𝜔𝑖𝑚 − 𝜔𝐿𝑂 𝑡 + ∅𝑖𝑚 ]
2 2
• One LO waveform is expressed as Sin𝜔𝐿𝑂 𝑡 and the other as 1 +∈ cos(𝜔𝐿𝑂 𝑡 + ∆𝜃)
𝐴𝑠𝑖𝑔 𝐴𝑖𝑚
𝑋𝐴 𝑡 = 1 +∈ cos[ 𝜔𝑐 − 𝜔𝐿𝑂 𝑡 + ∅𝑠𝑖𝑔 + ∆𝜃 + 1 +∈ cos[ 𝜔𝑖𝑚 − 𝜔𝐿𝑂 𝑡 + ∅𝑖𝑚 + ∆𝜃]
2 2
𝐴𝑠𝑖𝑔
𝑋𝑠𝑖𝑔 𝑡 = + 1 +∈ cos (𝜔𝑐 −𝜔𝐿𝑂 𝑡 + ∅𝑠𝑖𝑔 + ∆𝜃] +
2
𝐴𝑠𝑖𝑔
cos 𝜔𝑐 − 𝜔𝐿𝑂 𝑡 + ∅𝑠𝑖𝑔 ]
2
𝐴𝑖𝑚 𝐴𝑖𝑚
𝑋𝑖𝑚 𝑡 = 1 +∈ cos 𝜔𝑖𝑚 − 𝜔𝐿𝑂 𝑡 + ∅𝑖𝑚 + ∆𝜃 - cos[ 𝜔𝑖𝑚 − 𝜔𝐿𝑂 𝑡 + ∅𝑖𝑚 ]
2 2

9
Image Reject Ratio
(𝑖𝑚𝑎𝑔𝑒 𝑡𝑜 𝑠𝑖𝑔𝑛𝑎𝑙 𝑟𝑎𝑡𝑖𝑜)𝑖𝑝
𝐼𝑅𝑅 =
(𝑖𝑚𝑎𝑔𝑒 𝑡𝑜 𝑠𝑖𝑔𝑛𝑎𝑙 𝑟𝑎𝑡𝑖𝑜)𝑜𝑝

The average power of the vector sum acos ω𝑡 + 𝛼 + 𝑏𝑐𝑜𝑠𝜔𝑡 is given by (𝑎2 + 2𝑎𝑏𝑐𝑜𝑠𝛼 + 𝑏2 )Τ2

𝑃𝑖𝑚 𝐴2𝑖𝑚 (1 +∈)2 −2 1 +∈ 𝑐𝑜𝑠∆𝜃 + 1

| =
𝑃𝑠𝑖𝑔 𝑜𝑢𝑡 𝐴2𝑠𝑖𝑔 (1 +∈)2 +2 1 +∈ 𝑐𝑜𝑠∆𝜃 + 1

𝐴2𝑖𝑚
The image-to-signal ratio at the input is given by 𝐴2 .
𝑠𝑖𝑔
(1 +∈)2 +2 1 +∈ 𝑐𝑜𝑠∆𝜃 + 1
(1 +∈)2 −2 1 +∈ 𝑐𝑜𝑠∆𝜃 + 1

10
Drawbacks of Hartley Architecture
• Amplitude and phase mismatch
• Limitation of RCCR filter
• Voltage addition mismatch

11
 RF Transceiver Design
Lecture 18
Transceiver Architecture – V

Prof. Darshak Bhatt

Department of Electronics & Communication Engineering

1
 Weaver Architecture
A C
LPF LPF E +
RF
Input CosωLO1t CosωLO2t + IF
Output
-
LPF B LPF
D F

SinωLO1t SinωLO2t
𝐴𝑠𝑖𝑔 𝐴𝑖𝑚
𝑋𝐶 𝑡 = cos[(𝜔𝐶 − 𝜔1 − 𝜔2 )t + ∅𝑠𝑖𝑔 ] + cos[ 𝜔𝑖𝑚 − 𝜔1 − 𝜔2 𝑡 + ∅𝑖𝑚 ]
4 4
𝐴𝑠𝑖𝑔 𝐴
+ cos[(𝜔𝑐 − 𝜔1 + 𝜔2 )t + ∅𝑠𝑖𝑔 ] + 𝑖𝑚 cos[ 𝜔𝑖𝑚 − 𝜔1 + 𝜔2 𝑡 + ∅𝑖𝑚 ]
4 4
𝐴𝑠𝑖𝑔
𝑋𝐷 𝑡 = − cos[(𝜔𝐶 − 𝜔1 − 𝜔2 )t + ∅𝑠𝑖𝑔 ]
4
𝐴𝑖𝑚
− cos[ 𝜔𝑖𝑚 − 𝜔1 − 𝜔2 𝑡 + ∅𝑖𝑚 ]
4
𝐴𝑠𝑖𝑔
+ cos[(𝜔𝑐 − 𝜔1 + 𝜔2 )t + ∅𝑠𝑖𝑔 ]
4
𝐴𝑖𝑚
+ cos[ 𝜔𝑖𝑚 − 𝜔1 + 𝜔2 𝑡 + ∅𝑖𝑚 ]
4
2
Low-IF Receivers
• Direct conversion of the 200-kHz desired channel to a zero IF may significantly corrupt
the signal by 1/f noise

Adjacent
90 dB Channel

𝑓𝑐 𝑓

0 𝑓 𝑓𝑐 𝑓
𝑓𝐿𝑂 𝑓

• The GSM standard requires that receivers tolerate an

adjacent channel only 9 dB above the desired channel.
• If IRR = 30 dB, the image remains 21 dB below the signal.

3
Polyphase Filters 𝑉1 + 𝑅1 C1 𝑠𝑉2
𝑉out =
Case1: When 𝑽𝟐 = -j 𝑽𝟏 , 𝒂𝒏𝒅 𝒔 = 𝒋ω 𝑅1 𝐶1 𝑠 + 1

= -j 𝑉1
𝑉1
Case2: When 𝑽𝟐 = +j 𝑽𝟏 (𝒏𝒆𝒈𝒂𝒕𝒊𝒗𝒆 𝒉𝒊𝒍𝒃𝒆𝒓𝒕), 𝒂𝒏𝒅 𝒔 = 𝒋ω
𝑉out
𝑉2 = -j 𝑉1 = +j 𝑉1

𝑅1 C1 𝜔 + 1
𝑉out = 𝑉1
𝑗𝑅1 C1 𝜔 + 1
−𝑅1 C1 𝜔 + 1 𝑉2 = +j 𝑉1
𝑉out = 𝑉1
𝐼𝑓 𝜔 = 𝑅𝐶 −1 𝑗𝑅1 C1 𝜔 + 1
2𝑉1
𝑉out = = 𝑉1 1 − 𝑗 𝑉1
1+𝑗 𝐼𝑓 𝜔 = 𝑅𝐶 −1
𝑡ℎ𝑒𝑛 𝑉out = 0 𝑉out
𝑉out = 2𝑉1 , ∠ 𝑉out = ∠ 𝑉in − 450

4
Ex: Extend the topology of the previous figure if V1 and -jV1 are available in differential form and construct an image-
reject receiver.
+j 𝑉1
= -j 𝑉1
𝑉out2
1

2
-V1 +V1
= +j 𝑉1
𝑉out1
Quadrature Downconverter

+Vsig+Vim -j 𝑉1

-Vsig-Vim
Cos ωLOt
𝑉RF
Sin ωLOt
+jVsig-jVim

-jVsig+jVim

5
Sequence-Asymmetric Polyphase Filter.
+j 𝑉1
+ +
+V1 -jV1 𝑉out2
- - 𝑉out3

-V1 +V1
Vout4

𝑉out4 𝑉out1

-j 𝑉1
+ +
+jV1 -V1
- -

• This circuit is called a “sequence-asymmetric polyphase filter.”

• Since the signal and the image arrive at the inputs with different sequences,
one is passed to the outputs while the other is suppressed.

6
Ex: The outputs of a quadrature downconverter contain the signal, Vsig, and the image, Vim, and drive
the circuit in the previous Fig as shown in the below Fig. Determine the outputs, assuming all
capacitors are equal to C and all resistors equal to R. +Vsig+Vim
1
+j 𝑉sig 2
-Vsig-Vim
Cos ωLOt
4 𝑉RF
𝑉out2 𝑉out3
-Vsig 3 1
+Vsig Sin ωLOt
𝑉out4 𝑉out1
+jVsig-jVim
2 3
-jVsig+jVim 4
-j 𝑉sig +j 𝑉Im

2
-VIm 3 1
+Vim 𝑉out1 , 𝑉out1 , 𝑉out1 , 𝑉out1 = 0

4
-j 𝑉Im

7
Effect of a polyphase filter at a frequency offset of Δω on signal and image
−1 𝑅1 C1 𝜔 + 1
➢ But what happens if 𝜔 ≠ 𝑅𝐶 ?Substituting ω = (R1C1)-1 + Δω in 𝑉out = 𝑉1
𝑗𝑅1 C1 𝜔 + 1

𝑉out1 ≈ 2𝑉sig − tan−1 (1 + 𝑅𝐶Δω)

𝜋 𝑅𝐶Δω
∠ 𝑉out1 = ∠ 𝑉sig − +
4 2

+j 𝑉1
𝑉out3
𝑉out2

-V1 +V1

Signal Image
𝑉out1
𝑉out4

𝑅𝐶Δω -j 𝑉1
2

8
 RF Transceiver Design
Lecture 19
Transceiver Architecture – VI

Prof. Darshak Bhatt

Department of Electronics & Communication Engineering

1
 Alternative schematic
Cascaded polyphase sections

Source: RF Microelectronics, Behzad Razavi

2
 LPF
𝑅1 +
𝐶1 SinωLOt
RF
Input
+ IF
Output
-
𝐶1
LPF

Quadrature Phase of 𝑅1 CosωLOt

Image and signal
LPF ADC 90ͦ
A

RF
Input
SinωLOt +
LPF
B

CosωLOt

3
Digital IF

RF BP Down IF
Filter Mixer Filter
Image Digital Data
LNA Reject ADC Channel
𝜔𝑅𝐹 Filter Selection

VCO Reconfigurable
software

𝜔𝑅𝐹 Digital Data

LNA ADC Channel
Selection

4
Super Regenerative Receiver
• Edwin Armstrong invented the first regenerative radio.(1914)
• SRR used the variable amplifier in positive feedback for tuning the single frequency.
• The amplifier was tuned in order to amplify the received signal.

Amplifier Detector Filter

Feedback

Tuning

5
Impulse Radio Receiver
• Short range, low power and high speed applications.
• The UWB standard employs impulse transmission within a frequency band between 3.1
GHz and 10.6 GHz.

Correlation

Mix1
LNA
න 𝑑𝑡 BBPS
𝜔𝑈𝑊𝐵

Template
Waveform

6
Archetucture Complexity Full integration Power cons. Comments
Super- Low Possible Very low No carrier, impulse with High sensitivity
regenerative wide bandwidth can because of
cause interferences resonant
with other sys- items if feedback
Impulse emitted power not High bandwidth
radio limited of 3.11-10.6 GHz
allows high data
rates Comparison of
Super Moderate Off-chip image Moderate IF has to be traded off channel selection Receiver Architectures
heterodyne reject and for image rejection and
channel select
Dual super High filter required High Good image rejection possible
heterodyne and channel selection

Direct Low Possible Low DC offsets can significantly degrade

conversion performance, sensitive to
degrade the flicker noise
Low-IF Low/modera te Possible Low/mode Good overall performance
rate
Digital-IF RF: very low Possible Very high Very flexible architecture can handle
Baseband: very different standards, modulation, and
high frequencies; ADC limits dynamic range,
which is a major drawback.

7
8
TRANSMITTER ARCHITECTURES
I ROM DAC LPF

CosωLO2t
Baseband
Data
Address + Modulated
Signal
Generator

t
Q ROM DAC LPF

SinωLO2t

t t
t

9
Direct-Conversion Transmitters
XBB,I(t)

CosωLO2t Matching
+ PA
Network

Duplexer

XBB,Q(t)

SinωLO2t
I/Q Mismatch: It follows that the power of the unwanted
sideband divided by that of the wanted sideband is given by
(1 +∈)2 −2 1 +∈ 𝑐𝑜𝑠∆𝜃 + 1
(1 +∈)2 +2 1 +∈ 𝑐𝑜𝑠∆𝜃 + 1

10
Carrier Leakage Base
station

Carrier
CosωLO2t leakage

Processor
Baseband + PA

SinωLO2t Receiver

Mixer Non-linearity

11
 RF Transceiver Design
Lecture 20
Transceiver Architecture – VII

Prof. Darshak Bhatt

Department of Electronics & Communication Engineering

1
Direct-Conversion Transmitters
XBB,I(t)

CosωLO2t Matching
+ PA
Network

Duplexer

XBB,Q(t)

SinωLO2t
I/Q Mismatch: It follows that the power of the unwanted
sideband divided by that of the wanted sideband is given by
(1 +∈)2 −2 1 +∈ 𝑐𝑜𝑠∆𝜃 + 1
(1 +∈)2 +2 1 +∈ 𝑐𝑜𝑠∆𝜃 + 1

2
Carrier Leakage Base
station

Carrier
CosωLO2t leakage

Processor
Baseband + PA

SinωLO2t Receiver

Mixer Non-linearity

3
4
TX Linearity
VBB,I(t)
PA
CosωLO2t Predriver

+ 𝑉𝑥 𝑉𝑑𝑟 𝑉𝑜𝑢𝑡

VBB,Q(t)

SinωLO2t 𝑉𝑜𝑢𝑡

𝑉𝑑𝑟
𝑉𝑥

VBB

5
6
Oscillator Pulling

LO + LO

Vout

Vin
t

7
Factors causing the injection pulling
• The internal voltage and current swings of the LO (the larger
they are, the less the effect of pulling).
• The Q of the tank used in the oscillator.
• Whether the PA output is differential, in which case its coupling to the
LO is 30–40 dB lower than if it is single-ended.
• How much is the feedback loop controlling the LO (the
synthesizer) counteracts the pulling.
• The symmetry of the layout and the type of packaging.

8
Modern Direct-Conversion Transmitters
XBB,I(t)

LO ÷2 + PA
𝜔𝑐 2𝜔𝑐 𝜔

XBB,Q(t)

• Injection pulling is greatly reduced

• The divider readily provides quadrature phases of the carrier,
an otherwise difficult task.

9
Heterodyne Transmitters

VBB,I(t)

CosωLO2t
+ BPF PA
𝜔1 + 𝜔2 ω

𝑐𝑜𝑠𝜔2 𝑡
VBB,Q(t)

𝜔1 − 𝜔2 𝜔2 𝜔1 + 𝜔2 ω
𝜔1 ω
• Demerits:
o Carrier Leakage
o Mixing Spurs

10
OOK TRANSCEIVERS
• OOK(On-off keying) does not require quadrature baseband.
• It is also less bandwidth-efficient.
• It is attractive for low-cost, low-power applications.

PA PA
LO LO

Transmitter

LNA
Envelope
Detector

Receiver

11
What are the important components to design?

12
Thank You

13
 RF Transceiver Design
Lecture 21
Active Devices – I

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
 Device Technologies For Wireless Communication Systems

III-V compound semiconductor

Silicon-based
based devices
• Low-cost, high-volume production, • Advantages of their intrinsic material properties and
improved frequency response. superior device performance in high-frequency
• Well-established manufacturing applications (MMIC).
infrastructures. • Manufacturing is limited to certain types of
• Two major types depending on their applications
physical carrier transportation
• Ex: GaAs MESFETs, GaAs-
mechanisms: Unipolar (FETs) and
based high electron
Bipolar Junction Transistors (BJTs).
mobility transistors
• Ex: BJTs, silicon metal–oxide
(HEMTs), InP-PHEMTs,
semiconductor FETs (MOSFETs), LDMOS
GaAs-based HBTs, and InP-
transistors, and SiGe- heterojunction
based HBTs.
bipolar transistors (HBTs)

2
Q. What does mean by unipolar and bipolar devices?

• FET devices are also referred to as unipolar devices because the majority of carriers are
responsible for transport characteristics.
• Drain current in an FET is modulated by gate voltage through a channel width modulation
scheme.
• The amplification process in FET is characterized by a transconductance (gm ).
• Carrier transportation mechanisms in bipolar transistors involve both electrons and holes.
• The minority current injection from the base modulates the collector current.
• BJT is equivalent to a current amplifier as the input base current
is “amplified” by a factor of β (current gain), and the output
current is “collected” at the collector end.

3
 Semiconductor Material Systems

Si Ge GaAs GaN InP

• Silicon has higher thermal • GaAs material has higher electron
Followed in the next slide
conductivity, but the electron drift mobility compared with silicon.
velocity and mobility are slow. • It has been a choice for MMIC
• Lack of semi-insulating substrates applications for decades.
→ additional development costs • The drawback → Poor thermal
• Semi-insulating substrates are dissipation capability.
easily prepared in most compound • High thermal resistance value in RF
semiconductors. power application is harmful.
• This property is beneficial in terms • Special care must be taken to
of providing RF applications with mitigate thermal-related system
high device isolation and low performance degradation in GaAs
dielectric loss

4
 GaN InP
• It has the fastest drift velocity among all • It has been widely used in semiconductor-based
other semiconductor materials. optoelectronics for decades.
• The wide bandgap in GaN translates to a • This will ease the problematic thermal issues, as
higher breakdown field. we have seen in GaAs to some extent.
• Low thermal resistance and possible • They can yield the fastest transistors among all
epitaxial growth on silicon carbide the semiconductor devices on both FET and HBT
substrates make this material system devices.
perfect for high-power RF applications. • InP have been sought to become a technological
alternative for GaAs-based material system due
to their superior intrinsic electrical properties

5
Comparisons of Field Effect Transistor (FET) and Heterojunction Bipolar Transistor Technologies (HBT/BJT)
HBT/BJT FET
• A narrower base and a thinner collector in a • A shorter gate length in a FET can reduce the
bipolar device can decrease the carrier transit carrier transport time.
time. • The gate length is defined by photolithography.
• The vertical layers in HBT are defined by epitaxial • The high-performance sub-micrometer FET
growth. demands advanced photolithography.
• Commonly available crystal growth techniques → • A gate length of < 0.15 um in FET will be
precise epitaxial growth. required to achieve comparable RF
• The fT and fmax in the 100 to 300-GHz range can be performance regarding larger fT and fmax .
achieved with a conventional 1um • Prone to
photolithography technology. mismatches
• HBTs intrinsically have better device matching and (process variations
are suitable for differential pairs. & channel
formation

6
Contd.
HBT/BJT FET
• Higher current density than FET devices because • The breakdown characteristic of an FET is
of a larger emitter area than a thin channel in an affected by the lateral device dimensions, such
FET as gate-to-drain.
• HBTs can handle more power within a smaller chip • In general, a FET has better noise performance
size than the FET-based power circuits. at high frequencies.
• The breakdown voltage of an HBT can be tailored • The noise source of a FET is mainly the thermal
for optimized power performance via epitaxial noise → suitable for low-power LNA
growth. applications.
• For a BJT, the noise figures are determined by shot • Simple to fabricate → requires 3 to 4 masks for
noise related to the operating currents. a device.
• Very complex device-level fabrication → multiple
etching & metal deposition steps

7
 SiGe HBT GaN HEMT

Schematic cross-section of SiGe HBT on wafer-bonded SOI with buried

silicide collector layer and buried silicide ground plane
Source:
M. Bain et al., "SiGe HBTs on bonded SOI incorporating buried silicide layers," in IEEE Transactions on Electron Devices, vol. 52, no. 3, pp. 317-324, March 2005, doi:
10.1109/TED.2005.843872.
https://www.researchgate.net/publication/329795065_Simulation_and_comparative_analysis_of_the_DC_characteristics_of_submicron_GaN_HEMTs_for_use_in_CAD_software

8
Comparison Chart for Different Device Technologies in Wireless Communication RF Transceiver Applications
Parameters GaAs GaAs HBT GaAs HEMT Si RF CMOS SiGe HBT InP HBT
MESFET
Device speed Good Good Good Fair Good Excellent

Chip density Low High Low Low High High

Transconductance Medium High High Low High High

Device matching Poor Good Poor Poor Good Good

1/f noise Poor Good Poor Poor Good Good

PAE Medium High High Medium Medium High
Linearity High High High Low Medium High
Device matching Poor Good Poor Poor Good Good

Output Medium Low Medium High Low Low

conductance
Integration level MSI, LSI MSI, LSI MSI, LSI VLSI LSI, VLSI MSI, LSI

Breakdown voltage High High High Medium Medium High

Possible primary VCO, PA, Pre-Amp LNA Gain Back end logic LNA, PA, Gain PA, LNA, VCO
applications in RF Mixer, gain blocks, blocks, control, blocks
transceivers Switches Oscillator Switches switches,
amps. mixers

9
 RF Transceiver Design
Lecture 22
Active Devices – II

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
A Summary of PA Power Performance at Frequency Around 2 GHz

Technology Power Gain Output ACPR @5 Efficiency (%) Group

(dB) Power (dBm) MHz (dBc)

InGaP/GaAs 31 27 -40 35 RFMD

HBT

InGaP/GaAs - 27 -37 38 M/A- COM

HBT

InGaP/GaAs 28.5 26.3 -35 50.5 NEC

HBT

GaAs HFET 22.3 26 -35.5 47.2 NEC

GaAs pHEMT 12.1 29.5 -40 25.6 Motorola
GaN HEMT 25 50 - 54 Cree

2
Generic Three TerminalDevice
Io
Output current is dependent on input voltage
I0 = f(Vi ,V0) ≈ f(Vi)

+
Vi
-

3
Generic Model: Large Signal Equations Io Vin5
Saturation or constant
current region

Vin4

Vin3

Vin2

Vin1
Vo

• Regions:
• Resistive (triode) region
• Non-linear region (small output voltage)
• Saturation or constant current region

4
MOSFET

𝑤 1 2
𝐷𝑟𝑎𝑖𝑛 𝐶𝑢𝑟𝑟𝑒𝑛𝑡: 𝐼𝐷 = 𝜇𝑛 𝐶0𝑥 𝑉𝐺𝑆 − 𝑉𝑇𝐻 𝑉𝐷𝑠 − 𝑉𝐷𝑠
𝐿 2

5
MOSFET Large Signal Characteristics 𝐼𝐷𝑠𝑎𝑡 = 2 𝜇𝑛 𝐶0𝑥
1 𝑤
𝑉𝐺𝑆 − 𝑉𝑇𝐻 2
ID 𝐿

1 𝑤 2
Triode Region ID Saturation Region
𝐼𝐷𝑚𝑎𝑥 = 𝜇 𝑛 𝐶0𝑥 𝑉𝐺𝑆 − 𝑉𝑇𝐻
2
When VDS = VGS - VTH
𝐿
VGS3 VGS3

VGS2 VGS2
𝑤
𝐼𝐷 ≈ 𝜇𝑛 𝐶0𝑥 𝐿 𝑉𝐺𝑆 − 𝑉𝑇𝐻 𝑉𝐷𝑆 VGS1
When VDS << 2 (𝑉𝐺𝑆 − 𝑉𝑇𝐻 ) VGS1
1
𝑅𝑂𝑁 = VDS

VGS1 - VTH
VGS2 - VTH
VGS3 - VTH
𝑤
𝜇𝑛 𝐶0𝑥 𝑉𝐺𝑆 −𝑉𝑇𝐻
VDS

VGS3 - VTH
𝐿

VGS1 - VTH
VGS2 - VTH
NMOS Transistor
Region VGS VGD
Cutoff < 𝑉𝑡ℎ < 𝑉𝑡ℎ
𝜖0𝑥 𝑓𝐹
Saturation(Active) ≥ 𝑉𝑡ℎ < 𝑉𝑡ℎ 𝐶0𝑥 = = 3.45
𝑡0x 𝑢𝑚2
Triode ≥ 𝑉𝑡ℎ ≥ 𝑉𝑡ℎ 𝑓𝑜𝑟 𝑡0x = 100 Ao

6
MOSFET Small-Signal Model

𝑤 𝑤
𝑇𝑟𝑎𝑛𝑠𝑐𝑜𝑛𝑑𝑢𝑐𝑡𝑎𝑛𝑐𝑒 𝑔𝑚 = 𝜇𝑛 𝐶0𝑥 𝑉𝐺𝑆 − 𝑉𝑇𝐻 = 2𝐼D 𝜇𝑛 C0x
𝐿 𝐿
𝑔𝑚 2
=
𝐼𝐷 𝑣𝐺𝑠 − 𝑣𝑇
𝛾
Body-effect Transconductance 𝑔𝑚𝑏 = 𝑔𝑚 = 𝜒𝑔𝑚
2 2𝜙𝑓 +𝑉𝑆𝐵
1 1 d𝑥𝑑
𝐶ℎ𝑎𝑛𝑛𝑒𝑙 − 𝑙𝑒𝑛𝑔𝑡ℎ 𝑀𝑜𝑑𝑢𝑙𝑎𝑡𝑖𝑜𝑛 𝑝𝑎𝑟𝑎𝑚𝑎𝑡𝑒𝑟 𝜆= =
𝑣𝐴 𝐿𝑒𝑓𝑓 d𝑉𝐷𝑠

7
MOSFET Capacitance

8
 RF Transceiver Design
Lecture 23
Active Devices – III

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
MOSFET Capacitance

2
Frequency Response of a MOSFET
Q. What if fT and fmax of the MOSFET, Derive the expression for them?

3
4
5
 RF Transceiver Design
Lecture 24
Active Devices – IV

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
Bipolar Transistor E B C

n p
n

𝐼𝑐 = 𝐼𝑠 exp 𝑉𝑏𝑒 /𝑉𝑇

npn Bipolar Transistor
Region VBE VBC
Cutoff < VBE(on) < VBC(on)
Forward Active > VBE(on) < VBC(on)
Reverse Active < VBE(on) ≥ VBC(on)
Saturation ≥ VBE(on) ≥ VBC(on)

2
Bipolar Large-Signal Characteristics
𝐼𝑐 = 𝐼𝑠 exp 𝑉𝑏𝑒 /𝑉𝑇
𝐼𝐶
Early Voltage 𝑉𝐴 =
𝜕𝐼𝑐
Active Region
𝜕𝑉𝐶𝐸

VA = Early Voltage

3
Bipolar Small-Signal Model: Parasitics
Collector Base Emitter

4
Bipolar Small-Signal Model:
Base Collector

Emitter

• The resistor Rπ dominates the input impedance at low frequency.

• At high frequency, though, Cπ dominates.
• Cµ is due to the collector-base reverse-biased diode capacitance.
• Ccs is the collector-to-substrate parasitic capacitance. In some processes, this is
reduced with an oxide layer.
• Cπ has two components due to the junction capacitance (forward-biased) and a
diffusion capacitance

5
Small Signal Parameters of BJT
Transconductance 𝑞𝐼𝑐 𝐼𝑐
𝑔𝑚 = =
𝑘𝑇 𝑉𝑇
Transconductance-to-current ratio 𝑔𝑚 1
=
𝐼𝑐 𝑉𝑇
Input resistance 𝛽0
𝑟𝜋 =
𝑔𝑚
Output resistance 𝑉𝐴 1
𝑟𝑜 = =
𝐼𝑐 𝜂𝑔𝑚
Collector-base resistance 𝑟𝑢 = 𝛽0 𝑟𝑜 to 5𝛽0 𝑟𝑜
Base-charging capacitance 𝐶𝑏 = 𝜏f 𝑔𝑚
Base-emitter capacitance 𝐶𝛱 = 𝐶𝑏 + 𝐶𝑗𝑒
Emitter-base junction depletion capacitance 𝐶𝑗𝑒 ≈ 2𝐶𝑗𝑒0

where VT= kT /q = 26mV

at room temperature

6
Q. What if fT and fmax of the Bipolar transistor Derive the expression for them?

7
8
 ➢ In semiconductor device technologies, a device with a similar size but a higher fT value is usually a
favorable choice of technology.
➢ The reasons are:
1) The higher fT device can operate at lower power without compromising switching speed.
2) The devices with higher fT have a faster switching time, higher power gain, and better efficiency
without an increase in power consumption.

➢ fT for SiGe BiCMOS and

RF CMOS

Source: https://www.researchgate.net/publication/228847109_Choosing_RF_CMOS_or_SiGe_BiCMOS_in_mixed-signal_design/citationsSource

9
SiGe Technology

• Higher Performance: Demonstrations of fT > 500GHz

and approach 1THz.
• Problem: As WB decreases → rb increases
• Solution: SiGe base allows for higher fT without
reducing WB

10
SiGe HBT
• A SiGe BJT is often called an HBT (heterojunction bipolar transistor)
• Ge is epitaxially grown in base
• Causes strain in the crystal
• Causes extra potential barrier for holes (majority carrier) in the base from
flowing into the emitter
• Benefits:
• WB decreases, NB increases, rb low
• NE decreases, Cj decreases

11
FinFETs and Multigate Transistors

• FinFET -> scaling of MOSFET below 45nm Technology

• Double Gate Technology
• TSMC, Intel, GlobalFoundries Inc. uses FinFET in lower
node technologies
• Gate control is improved due to the thin body and double
gates. -> To enhanced output resistance and lower
leakage in the subthreshold.

12
FinFET Structure and Layout • Gate straddles thin silicon fin, forming two
conducting channels on the sidewall
• Multi-finger layout very similar to RF
layout.

13
Advantages of BJT over MOSFET

• For fixed current, BJT gives more gain (High BJT

transconductance)
• Precision:
• Important in multiplication, log, and exponential
functions
• More difficult in FETs due to process/temp.
dependence
• Is process dependent in BJT ... use circuit tricks

14
 RF Transceiver Design
Lecture 25
Passive Components & Impedance Matching – I

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
Problems of High-Frequency Design
• Circuit dimension becomes comparable to wavelength at microwave frequencies.
• Phase effects are more apparent. With small 𝜆, signals at different points along a line are
no longer in phase.
• At high frequencies, electrical signals behave more like ‘waves’.
• At high frequencies, circuit elements become more ‘distributed’ rather than ‘lumped’.
• Parasitic effects due to stray inductances and capacitances in cablings.
• Skin effect is more apparent.(Resistivity increases).

2
Three Regimes
• Lumped circuit regime
➢ Physical dimension << wavelength of signal
➢ Maxwell’s equations simplified considerably: wave nature ignored; Kirchoff’s law,
Inductance, Capacitance
• Optics regime
➢ Physical dimension >> wavelength of signal
➢ Maxwell’s equations simplified considerably: Waves become rays; Snell’s law, mirrors,
lenses, polarizers.
• Transmission line/distributed circuit regime
➢ Physical dimensions ~ wavelength of signal
➢ Maxwell’s equations can not be simplified: waves are waves;
T-lines, microwave circuits, optical fiber.

3
Distributed vs lumped
Rise Time vs Travel Time Period vs Travel Time Component Size vs Wavelength

Vin(t) 𝑣
V0 λ=𝑓
0.9 V0

L < 0.01λ (lumped)

L < 0.01λ (Distributed)
0.1 V0

tr t
𝑙
td= 𝑣
T=1/f
td < 0.01T (lumped)
td < 0.01T (Distributed)
(tr/td) > 6 (lumped)
(tr/td) < 2.5 (Distributed)
Source: Inan, Umran S., Aziz S. Inan, and Ryan K. Said. "Engineering electromagnetics and waves." (No Title) (2016).

4
Distributed vs lumped
0.35
• 𝑓𝑚𝑎𝑥 = 𝑡𝑟
commonly taken as the highest frequency of interest

𝑣
• Corresponding to 𝑓𝑚𝑎𝑥 , shortest wavelength 𝜆𝑠ℎ𝑜𝑟𝑡 = 𝑓 .
𝑚𝑎𝑥

• Distributed regime: physical length; 𝑙 ≈ 𝜆𝑠ℎ𝑜𝑟𝑡 “Much less” which is

say 0.01 of 𝜆𝑠ℎ𝑜𝑟𝑡

• Example: 𝑓𝑚𝑎𝑥 = 30 𝐺𝐻𝑧 in air, 𝜆𝑠ℎ𝑜𝑟𝑡 = 10𝑚𝑚; length should no

more than 100um ; People sized object can’t be treated as
lumped.

• Speed of EM waves in PCB less than speed in air; 30→ 14 GHz

5
 Two circuit blocks connected by a long wire
𝑖(𝑧, 𝑡)
Block
B
+ Block
𝑣(𝑧, 𝑡) A
−
𝑧 Two circuit blocks connected by T-wire
∆𝑧
Block Block
i(z, t) 𝑖(𝑧 + ∆𝑧, 𝑡) A B

+ 𝑅∆𝑧 𝐿∆𝑧 +

𝑣(𝑧, 𝑡) 𝐺∆𝑧 𝑣(𝑧 + ∆𝑧, 𝑡)

𝐶∆𝑧
− −

6
 𝜕𝑖 𝑧, 𝑡
𝑣 𝑧, 𝑡 − 𝑅∆𝑧𝑖 𝑧, 𝑡 − 𝐿∆𝑧 − 𝑣 𝑧 + ∆𝑧, 𝑡 = 0
𝜕𝑡
𝜕𝑣 𝑧 + ∆𝑧, 𝑡
𝑖 𝑧, 𝑡 − 𝐺∆𝑧𝑣 𝑧 + ∆𝑧, 𝑡 − 𝐶∆𝑧 − 𝑖 𝑧 + ∆𝑧, 𝑡 = 0
𝜕𝑡
• Dividing Δz and taking the limit as Δ𝑧 → 0
𝜕𝑖(𝑧, 𝑡) 𝜕𝑖(𝑧, 𝑡)
= −𝑅𝑖 𝑧, 𝑡 − 𝐿
𝜕𝑧 𝜕𝑡
𝜕𝑖(𝑧, 𝑡) 𝜕𝑣(𝑧, 𝑡)
= −𝐺𝑣 𝑧, 𝑡 − 𝐶
𝜕𝑧 𝜕𝑡
• This is called the time domain form of the transmission line
equations, also known as the telegrapher equations
𝜕𝑉 𝑧, 𝑡
= − R + jω𝐿 𝐼 𝑧
𝜕𝑧
𝜕𝐼(𝑧)
= − 𝐺 + 𝑗𝜔𝐶 𝑉(𝑧)
𝜕𝑧
7
 𝜕 2 𝑉(𝑧) 2𝑉 z = 0
𝜕 2 𝐼(𝑧) 2𝐼 𝑧 = 0
− 𝛾 − 𝛾
𝜕2𝑧 𝜕2𝑧
Where,
𝛾 = 𝛼 + 𝑗𝛽 = (𝑅 + 𝑗𝜔𝐿)(𝐺 + 𝑗𝜔𝐶)

Hence, by solving above two equations:

𝑉 𝑧 = 𝑉𝑜+ 𝑒 −𝛾𝑧 + 𝑉𝑜− 𝑒 𝛾𝑧 𝐼 𝑧 = 𝐼𝑜+ 𝑒 −𝛾𝑧 + 𝐼𝑜− 𝑒 𝛾𝑧
𝛾
𝐼 𝑧 = (𝑉𝑜+ 𝑒 −𝛾𝑧 − 𝑉𝑜− 𝑒 𝛾𝑧 )
𝑅 + 𝑗𝜔𝐿
𝑅 + 𝑗𝜔𝐿 𝑅 + 𝑗𝜔𝐿
𝑍0 = =
𝛾 𝐺 + 𝑗𝜔𝐶

𝑉𝑜+ −𝛾𝑧 𝑉0− 𝛾𝑧

𝐼 𝑧 = 𝑒 − 𝑒
𝑍0 𝑍0
8
The Lossless Line
R=G=0, 𝛾 = 𝛼 + 𝑗𝛽 = 𝑗𝜔 𝐿𝐶

𝛽 = 𝜔 𝐿𝐶
𝛼=0
𝐿
𝑍𝑜 =
𝐶
The general solutions for voltage and current on a lossless transmission line can then be
written as
𝑉 𝑧 = 𝑉𝑜+ 𝑒 −𝛾𝑧 + 𝑉𝑜− 𝑒 𝛾𝑧 𝐼 𝑧 = 𝐼𝑜+ 𝑒 −𝛾𝑧 + 𝐼𝑜− 𝑒 𝛾𝑧

The wavelength, and the phase velocity

2𝜋 2𝜋 𝜔 1
λ= = 𝑣𝑝 = =
𝛽 𝜔 𝐿𝐶 𝛽 𝐿𝐶

9
THE TERMINATED LOSSLESS TRANSMISSION LINE
𝑉 𝑧 , 𝐼(𝑧) 𝐼𝐿
+
𝑍0 , 𝛽 𝑉𝐿 𝑍𝐿
−
𝑧
𝑙 0
𝑉(0) 𝑉0+ + 𝑉0−
𝑉 𝑧 = 𝑉𝑜+ 𝑒 −𝛾𝑧 + 𝑉𝑜− 𝑒 𝛾𝑧 𝑍𝐿 = = 𝑍
𝐼(0) 𝑉0+ − 𝑉0− 0
𝑉0+ −𝑗𝛽𝑧 𝑉0− 𝑗𝛽𝑧
𝐼 𝑧 = 𝑒 − 𝑒
𝑍0 𝑍0
Reflection Coefficient
𝑉0− 𝑍𝐿 − 𝑍0
ᴦ= +=
𝑉0 𝑍𝐿 + 𝑍0

10
• The voltage and current on the line consist of a superposition of an incident and a
reflected wave; such waves are called standing waves

𝑉 𝑧 = 𝑉𝑜+ (𝑒 −𝑗𝛽𝑧 + ᴦ𝑒 𝑗𝛽𝑧 )

𝑉𝑜+ −𝑗𝛽𝑧
𝐼 𝑧 = (𝑒 − ᴦ𝑒 𝑗𝛽𝑧 )
𝑍0
• The time-average power flow along the line at the point z:
1 ∗
1 𝑉𝑜+ 2
𝑃𝑎𝑣𝑔 = 𝑅𝑒 𝑉 𝑧 𝐼(𝑧) = 𝑅𝑒 1 − ᴦ
2 2 𝑍0
• Loss in power due to mismatch is called as return loss
𝑅𝐿 = −20𝑙𝑜𝑔 ᴦ 𝑑𝐵
ᴦ = 0, ᴦ = 1, ᴦ = 0.1

11
Measure of mismatch of the line is called standing wave ratio (SWR).
𝑉𝑚𝑎𝑥 1 + ᴦ 𝑉 𝑧 , 𝐼(𝑧) 𝐼𝐿
𝑆𝑊𝑅 = =
𝑉𝑚𝑖𝑛 1 − ᴦ
+
𝑉(−𝑙) 𝑉𝑜+ (𝑒 𝑗𝛽𝑙 +ᴦ𝑒 −𝑗𝛽𝑙 ) 1+ᴦ𝑒 −2𝑗𝛽𝑙 𝑍0 , 𝛽 𝑉𝐿 𝑍𝐿
𝑍𝑖𝑛 = = 𝑍𝑜 = 𝑍
𝐼(−𝑙) 𝑉𝑜+ (𝑒 𝑗𝛽𝑙 −ᴦ𝑒 −𝑗𝛽𝑙 ) 1−ᴦ𝑒 −2𝑗𝛽𝑙 𝑜 −
𝑧
𝑍𝐿 + 𝑍0 𝑒 𝑗𝛽𝑙 + 𝑍𝐿 − 𝑍0 𝑒 −𝑗𝛽𝑙
𝑍𝑖𝑛 = 𝑍𝑜
𝑍𝐿 + 𝑍0 𝑒 𝑗𝛽𝑙 𝑍𝐿 − 𝑍0 𝑒 −𝑗𝛽𝑙

(𝑍𝐿 𝑐𝑜𝑠𝛽𝑙 + 𝑗𝑍𝑜 𝑠𝑖𝑛𝛽𝑙)

𝑍𝑖𝑛 = 𝑍0
𝑍𝑜 𝑐𝑜𝑠𝛽𝑙 + 𝑍𝐿 𝑠𝑖𝑛𝛽𝑙

(𝑍𝐿 + 𝑗𝑍𝑜 𝑡𝑎𝑛𝛽𝑙)

𝑍0
𝑍𝑜 + 𝑗𝑍𝐿 𝑡𝑎𝑛𝛽𝑙

12
 𝑉(𝑧)

Short Circuit Load 2𝑗𝑉𝑜+

−λ 3λ λ λ 𝑧
−
𝑉 𝑧 , 𝐼(𝑧) 𝐼𝐿 4 −
2
−
4

𝐼 𝑧 𝑍0
+ 2𝑉𝑜+
𝑍0 , 𝛽 𝑉𝐿 = 0 𝑍𝐿 = 0 λ λ
−λ 3λ −
− −
4
−
2 4

𝑧
−𝑙 0
3λ λ λ
−λ −
if 𝑙 = 0, 𝑍𝐿 = 0, −
4 −
2 4

𝑍𝑖𝑛 = 𝑗𝑍𝑜 𝑡𝑎𝑛𝛽𝑙

𝑛𝜆
if 𝑙 = , 𝑍𝑖𝑛 = 0,
2

2𝑛+1 𝜆
if 𝑙 = , 𝑍𝑖𝑛 = ∞ 𝑜𝑝𝑒𝑛 .
4

13
Open Circuit Load 𝑉 𝑧
2𝑉𝑜+

λ λ
−λ 3λ − − 𝑧
𝑉 𝑧 , 𝐼(𝑧) 𝐼𝐿 = 0 −
4 2 4

𝐼(𝑧)𝑍0
2𝑗𝑉𝑜+
+
𝑍0 , 𝛽 𝑉𝐿 𝑍𝐿 = ∞ −λ 3λ λ λ 𝑧
− − −
4
− 2 4

𝑧 𝑋𝑖𝑛

−𝑙 0
𝑍𝑜

3λ
if 𝑙 = 0, 𝑍𝐿 = ∞, −λ −
4 −
λ
2
−
λ
4
𝑧

𝑍𝑖𝑛 = − 𝑗𝑍𝑜 𝑐𝑜𝑡𝛽𝑙

𝑛𝜆
if 𝑙 = , 𝑍𝑖𝑛 = ∞ 𝑜𝑝𝑒𝑛 ,
2
2𝑛+1 𝜆
if 𝑙 = , 𝑍𝑖𝑛 = 0.
4

14
Quarter Wave Transformer
λ
ᴦ 4

𝑍0 𝑍𝐼 𝑅𝐿

𝑍𝑖𝑛
(𝑅𝐿 + 𝑗𝑍1 𝑡𝑎𝑛𝛽𝑙)
𝑍𝑖𝑛 = 𝑍1
𝑍1 + 𝑗𝑅𝐿 𝑡𝑎𝑛𝛽𝑙
𝑍12
𝑍𝑖𝑛=
𝑅𝐿
𝑍1 = 𝑍0 𝑅𝐿

15
 RF Transceiver Design
Lecture 26
Passive Components & Impedance Matching – II

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
Transmission coefficient
ᴦ ζ

𝐼 𝑉 𝑧 = 𝑉𝑜+ 𝑒 −𝑗𝛽𝑧 + ᴦ𝑒 𝑗𝛽𝑧 , 𝑧<0

𝑍𝐼
𝑍0 𝑉 𝑧 = 𝑉𝑜+ ζ𝑒 −𝑗𝛽𝑧 , z>0

0 𝑧
• Transmission Coefficient is given by:
𝑍1 − 𝑍0 2𝑍1
ζ= 1+ᴦ= 1+ =
𝑍1 + 𝑍0 𝑍1 + 𝑍0
• ζ is often expressed in dB and described as Insertion Loss (IL)
IL=−20𝑙𝑜𝑔 ζ 𝑑𝐵

2
Richard’s Transformations
Note that the input impedances are purely reactive—just like
lumped elements!

𝑍𝑖𝑛 = 𝑗𝑍0 𝑡𝑎𝑛𝛽𝑙 𝑍0 , 𝛽 𝑍𝑖𝑛 = −𝑗𝑍0 𝑐𝑜𝑡𝛽𝑙 𝑍0 , 𝛽

𝑙 𝑙
However, the reactance of lumped inductors and capacitors have a
much different mathematical form to that of transmission line stubs:

𝑍𝐿 = 𝑗𝜔L L 𝑍𝑐 = −𝑗Τ𝜔𝐶 C
• For a given lumped element (L or C) and a given stub (with a given Z0 and length l) the
functions will be equal at precisely one frequency!

• To make things easier, let’s set the length of our transmission line stub to λc/8, where:
𝑣𝑝 2𝜋
λ𝑐 = =
𝜔𝑐 𝛽𝑐
Q: Why l = λc/8?

A: Well, for one reason, βcl =π/4 and therefore tan (π /4) = 1.0!

This greatly simplifies our earlier results:

𝜋
𝑗𝜔𝑐 𝐿 = 𝑗𝑍𝑜 𝑡𝑎𝑛 = 𝑗𝑍0
4
−𝑗 𝜋
= −𝑗𝑍0 𝑐𝑜𝑡 = −𝑗𝑍0
𝜔𝑐 𝐶 4

4
• If we wish to build a short circuited stub with the same impedance as an inductor L at
frequency ωc, we set the characteristic impedance of the stub transmission line to be
𝑍𝑜 = 𝜔𝑐 𝐿:
• Similarly, if we wish to build open circuited stub with the same impedance as a capacitor C
at ωc, we set the characteristic impedance of the stub transmission line to be 𝑍0 = 𝜔𝑐 𝐿:

𝑠 𝑍0 = 𝜔𝑐 𝐿
𝑍𝐿 = 𝑗𝜔𝑐 𝐿 = 𝑍𝑖𝑛

𝜆𝑐
𝑙=
8

0 𝑍0 = 𝜔𝑐 𝐿
𝑍𝐿 = 𝑗Τ𝜔𝑐 = 𝑍𝑖𝑛

𝜆𝑐
𝑙=
8
5
• However, it is important to remember that Richard’s Transformations do not result in
perfect replacements for lumped elements—the stubs do not behave like capacitors and
inductors!
• Instead, the transformation is perfect—the impedances are equal—at only one frequency
(ωc).
• We can use Richard’s transformations to replace the inductors and capacitors of a designed
lumped element.
• The impedance is periodic in nature.

6
Stripline Transmission lines
Ground 𝑦
Plane

∈𝑟 𝑤

x
Ground Plane 𝑧

H
E

𝐿 𝛽 = 𝜔 𝐿𝐶
𝑍0 =
𝐶
𝜔
𝜖
𝜔 = 𝜖𝜇 𝑐 𝑟

7
An analytic approximation of characteristic impedance:
30𝜋 𝑏
𝑍0 = 𝑊
∈𝑟 𝑊𝑒 + 0.441𝑏 0 𝑓𝑜𝑟 > 0.35
𝑊𝑒 𝑊 𝑏
Where We is given by: = −
𝑏 𝑏 2 𝑊
(0.35 − 𝑊 Τ𝑏) 𝑓𝑜𝑟 > 0.35
𝑏
• These formulas assume a strip with zero thickness and are quoted as being accurate to
about 1% of the exact results.
• to find the strip width, given the characteristic impedance (and height b and relative
permittivity 𝜖𝑟 )
𝑊 𝑥 𝑓𝑜𝑟 ∈𝑟 𝑍0 < 120Ω
=൝
𝑏 0.85 − 0.6 − 𝑥 𝑓𝑜𝑟 ∈𝑟 𝑍0 < 120Ω
• Where
30𝜋
𝑥= − 0.441
𝜖𝑟 𝑍0

8
Microstrip line Transmission lines
𝑦

𝑑 ∈𝑟 𝑊
𝑥 ∈𝑒
H
𝑑
E

The propagation constant 𝛽 of a microstrip line is related to its

effective relative dielectric ∈𝑒 :
𝑐
𝑣𝑝 = 𝛽=𝑘0 ∈𝑒
∈𝑒
∈𝑟 +1 ∈𝑟 −1 1
∈𝑒 = +
2 2 1 + 12 𝑑Τ𝑊
9
Given the dimensions of the microstrip line, the characteristic impedance can be calculated as
60 8𝑑 𝑊
𝑙𝑛 + 𝑓𝑜𝑟 𝑊ൗ𝑑 ≤ 1
∈𝑒 𝑊 4𝑑
𝑍0 = 120𝜋
𝑓𝑜𝑟 𝑊ൗ𝑑 ≥ 1
𝜖𝑒 𝑊 Τ𝑑 + 1.393 + 0.667𝑙𝑛 𝑊 Τ𝑑 + 1.444

For a given characteristic impedance Z0 and dielectric constant 𝜖𝑟 , the W /d ratio can be found
as
𝑒𝐴
𝑊 𝑓𝑜𝑟 𝑊Τ𝑑 < 2
𝑒 2𝐴 −2 𝑊Τ > 2
= ൞ 2 ∈ −1 0.61
𝑓𝑜𝑟 𝑑
𝑑 𝑟
𝐵 − 1 − ln 2𝐵 − 1 + 2∈ ln 𝐵 − 1 + 0.39 − 𝜖
𝜋 𝑟 𝑟

𝑍0 ∈𝑟 +1 ∈𝑟 −1 0.11 377𝜋
𝐴= +∈ +1 0.23 + 𝐵=
60 2 𝑟 ∈𝑟 2𝑍0 𝜖𝑟

10
Back end of line CMOS Process
M9

0.7 um 𝜖𝑟 = 3.5
𝜖𝑟 = 7
M8

M1

Poly
Substrate

11
Two port parameters 𝐼1 𝐼2
𝑍 𝑀𝑎𝑡𝑟𝑖𝑥 Two
𝑉1 𝑉2
𝑉1 = 𝑍11 𝐼1 + 𝑍12 𝐼2 𝑉2 = 𝑍21 𝐼1 + 𝑍22 𝐼2 Port

𝑌 𝑀𝑎𝑡𝑟𝑖𝑥
𝐼1 = 𝑌11 𝑉1 + 𝑌12 𝑉2 𝐼2 = 𝑌21 𝑉1 + 𝑌22 𝑉2
𝐻 𝑀𝑎𝑡𝑟𝑖𝑥

𝑉1 = ℎ11 𝐼1 + ℎ12 𝑉2 𝐼2 = ℎ21 𝐼1 + ℎ22 𝑉2

𝐴𝐵𝐶𝐷 𝑀𝑎𝑡𝑟𝑖𝑥

𝑉1 = 𝐴𝐼1 + 𝐵𝑉2 𝐼1 = 𝐶𝐼1 + 𝐷𝑉2

12
Why S Parameters
No equipment is available to measure total voltage and total current at these frequencies.

The open-circuit and short-circuit terminations are difficult.

Active devices such as transistors may become unstable under open-circuit or short-circuit
conditions.
S Matrix 𝑉1− 𝑆11 𝑆12 … 𝑆1𝑁 𝑉1+
𝑉2− 𝑆 𝑆22 … 𝑆2𝑁 𝑉2+
= 21
⋮ ⋮ ⋮ ⋮ ⋮
−
𝑉𝑁 𝑆𝑁1 𝑆𝑁2 … 𝑆𝑁𝑁 𝑉𝑁+

𝑉𝑖−
𝑉− = 𝑆 𝑉+ 𝑆𝑖𝑗 = + ቉ 𝑉𝑘+ =0 𝑓𝑜𝑟 𝑘≠0
𝑉𝑗
13
VNA

14
Generalized S Parameters
• S-parameters are defined based on normalized traveling wave voltages a and b –
𝑉+ 𝑉−
𝑎= ; 𝑏=
2𝑍𝑜 2𝑍𝑜

𝑎1 𝑏1 𝑏2 𝑎2

𝑍𝑜 = 1Ω 𝑍𝑜 = 1Ω

𝑡1 𝑡2
𝑙1 = 0 𝑙2 = 0
a= normalized incident voltage wave
b= normalized reflected voltage wave

15
 𝑏1 = 𝑆11 𝑎1 + 𝑆12 𝑎2 𝑏2 = 𝑆21 𝑎1 + 𝑆22 𝑎2

𝑏 𝑏
𝑆11 = 𝑎1 ቃ input reflection coefficient 𝑆12 = 𝑎1 ቃ reverse transmission coefficient
1 2 𝑎1 =0
𝑎2 =0

𝑏2 𝑏
𝑆21 = ቃ forwaed transmission coefficient 𝑆22 = 𝑎2 ቃ output reflection coefficient
𝑎1 𝑎 =0 2 𝑎1 =0
2

∗
1 1 𝑉+ 1
𝑃+ = 𝑅𝑒 𝑉 + (𝐼 + )∗ = 𝑅𝑒 𝑉 + = 𝑉+ 2
2 2 𝑍𝑜 2𝑍𝑜

1
𝑃− = 2𝑍 𝑉 − 2
= 𝑏1 2
𝑃 = 𝑎1 2 − 𝑏1 2
𝑜

16
Shifting reference planes for lossless lines
𝑎1, 𝑎1 𝑎2 𝑎1,
𝑏1, 𝑏1 𝑏2 𝑏2,
𝑍1 𝑆11 𝑆12 𝑍2
𝑆21 𝑆22
New OLD OLD New
𝑋1 0 0 𝑋2

𝑏𝑘, = 𝑏𝑘 𝑒 −𝑗𝛽𝑘 𝑥𝑘 = 𝑏𝑘 𝑒 −𝑗𝜃𝑘 𝑎𝑙, = 𝑎𝑙 𝑒 𝑗𝛽𝑙 𝑥𝑙 = 𝑎𝑙 𝑒 𝑗𝜃𝑙

𝑤𝑖𝑡ℎ 𝜃𝑘 = 𝛽𝑘 𝑋𝑘 𝑤𝑖𝑡ℎ 𝜃𝑙 = 𝛽𝑙 𝑥𝑙

, 𝑏𝑘, 𝑏𝑘 𝑒 −𝑗𝜃𝑘
𝑆𝑘𝑙 = ൨ = ൨ =𝑆𝑘𝑙 𝑒 −𝑗 𝜃𝑘 +𝜃𝑙
(𝒑𝒉𝒂𝒔𝒆 𝒄𝒐𝒓𝒓𝒆𝒄𝒕𝒊𝒐𝒏)
𝑎𝑙, , 𝑎𝑙 𝑒 𝑗𝜃𝑙 ,
𝑎𝑖∗𝑙 =0
𝑎𝑖∗𝑙 =0

17
 The relationship between matrices can be written more conveniently as

𝑒 −𝑗𝜃1 0 … 0 𝑒 −𝑗𝜃1 0 … 0
−𝑗𝜃2 −𝑗𝜃2
𝑆′ = 0 𝑒 0 𝑠 0 𝑒 0
0 … 0 0 … 0
0 ⋯ 𝑒 −𝑗𝜃𝑁 0 ⋯ 𝑒 −𝑗𝜃𝑁

Properties of S-Parameters: Reciprocal : Sji = Sij; e.g.S21 = S12

Lossless Network: The total power flowing out is equal to the total power
flowing in.
𝑁 ∗ 𝑆22 = 𝑆11
𝑆𝑛𝑖 𝑆𝑛𝑗 = 𝛿𝑖𝑗 = 1 𝑓𝑜𝑟 𝑖 = 𝑗
෍
= 0 𝑓𝑜𝑟 𝑖 ≠ 𝑗 𝑆21 = 𝑆12 = 1 − 𝑆11 2
𝑛=1

18
The Smith Chart
• It is a polar plot of Γ.
• Bilateral Transform connecting the impedance Z and the Reflection coefficient Γ.
• The Smith chart maps the x-plane on the Γ plane.

𝑍
Z−𝑍0 −1 ɀ−1 𝑍
𝑍0
𝛤= = Z = 𝑤𝑖𝑡ℎ ɀ = = r+jx
Z+𝑍0 +1 ɀ+1 𝑍0
𝑍0

19
 RF Transceiver Design
Lecture 27
Passive Components & Impedance Matching – III

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
The Smith Chart
• It is a polar plot of Γ.
• Bilateral Transform connecting the impedance Z and the Reflection coefficient Γ.
• The Smith chart maps the x-plane on the Γ plane.

𝑍
Z−𝑍0 −1 ɀ−1 𝑍
𝑍0
𝛤= = Z = 𝑤𝑖𝑡ℎ ɀ = = r+jx
Z+𝑍0 +1 ɀ+1 𝑍0
𝑍0

2
 Z=1+j1
V
. 𝛤 = 1∠90o
Mapping of z=r+j1 (r≥0)
x
Z=j1 . Z=r+jx
. 𝛤 = 0.447∠±63.43o

. .
Z=0
.
Z=1 r . U
𝛤=0
Z=1-j1
𝛤=−1
.
Z=0+jx Mapping of z=1-j1
Z=1+jx Mapping of z=0+jx

ɀ plane |𝛤|=1 𝛤 plane 𝛤 = 0.447∠±63.43o

𝑍 R+jX
(ɀ = 𝑍 = Z = r+jx) 𝛤= U+jV
0 0

𝑗𝑥
For ɀ = 1+jx 𝛤= or 𝛤= 0 for x=0
2+𝑗𝑥
𝛤 = 0.447∠±63.43o for x= ±1
𝛤 = 0.707∠±45o for x=±2

3
Resistance & Reactance circles
2 2
𝑟𝐿 1
• Γ𝑖 = 0, 𝛤𝑟 − 2
+ 𝛤i =
1 + 𝑟𝐿 1 + 𝑟𝐿
2 2
2
1 1
𝛤𝑟 − 1 + 𝛤𝑖 − =
𝑥𝐿 𝑥𝐿
j
x
0.5
1

0.5 Open
0 0
0 -1 1
0 0.5 1 0 0.5 1
r
-0.5 Short
-0.5
-1

-j
4
▪ For negative resistance r<0 we have |Γ|>1

j
-0.5
0.5
x 1
-1
0 Open
1 Short 0
-0.5
0
0.5 1
0.5
-j
0
-0.5 0 0.5 1 r
-0.5

-1

5
Active and Passive Load
𝐼𝑚[𝛤L]
|𝛤L|>1
Active Devices

𝑅𝑒[𝛤L]
|𝛤L|<1
Passive Devices

6
Inductance and Capacitance on Smith Chart
• Locus of the reflection coefficient for an inductor and a capacitor In a Z Smith chart

ω=ꝏ
Open
ω=0
Open
ω=0
Short ω=ꝏ
Short

7
Reflection Coefficient
• The reflection coefficient is the ratio of the reflected to the incident wave.
𝛤(x)
. Line
.
V+(x) load

. V-(x)
.
x=-d 0
• For a loss-less line, we have : d
− 𝑗𝛽𝑥
𝑉 𝑒 𝑉 − 𝑗2𝛽𝑥
𝛤 𝑥 = −d = + −𝑗𝛽𝑥
= +e = 𝛤𝐿 e−𝑗2𝛽𝑑
𝑉 𝑒 𝑉
𝑉−
Where 𝛤𝐿 = 𝛤 𝑥 = 0 = +
𝑉

8
 𝐼𝑚[𝛤]
Reflection Coefficient along a line 𝑇𝑜𝑤𝑎𝑟𝑑
𝑡ℎ𝑒 𝑙𝑜𝑎𝑑
𝛤𝐿 =|𝛤𝐿 |e−𝑗 𝛼

For a loss-less line, the reflection coefficient can be written: . 𝑇𝑜𝑤𝑎𝑟𝑑 𝑡ℎ𝑒
Generator

𝛼
𝑅𝑒[𝛤]
2𝛽𝑑

𝛤 (d)= 𝛤𝐿 e−2𝑗𝛽𝑑 = |𝛤𝐿 |e−𝑗 𝛼−2𝛽𝑑

𝑖𝑓 𝑤𝑒 𝑑𝑒𝑓𝑖𝑛𝑒 𝛤𝐿 =|𝛤𝐿 |e−𝑗 𝛼
. 𝛤 𝑑 𝑓𝑜𝑟 𝑑 > 0

𝛤 plane

• As we move along the line, Γ(d) moves along a circle of radius |Γ𝐿 |.
• The reflection coefficient Γ(d) rotates clockwise as d increases,
and we moves towards generator

9
Voltage Standing Wave Ratio (VSWR) on the Smith chart

𝛤
𝛼

• A perfect matching (|Γ|=0) corresponds to

VSWR of 1.
• VSWR should be less than 2.

Read VSWR

10
Y Smith Chart
• The Y - smith chart can be obtained by expressing Γ in terms of Y
𝑍L 1 𝑌L
Z − 𝑍0 𝑍0 − 1 ɀ − 1 𝑦 − 1 𝑦−1 𝑌0
−1
𝛤𝐿 = = = = =− =−
Z + 𝑍0 𝑍L + 1 ɀ + 1 1 + 1 𝑦+1 𝑌L
+1
𝑍0 𝑦 𝑌0

Short Open Open Short

𝛤 Plane −𝛤 Plane
𝑁𝑜𝑟𝑚𝑎𝑙 𝑅𝑜𝑡𝑎𝑡𝑒𝑑
• The Y Smith Chart is obtained by inverting the Z Smith chart.
• In the rotated Y-Smith Chart, the short and open are exchanged.

11
Impedance and Admittance Smith Charts
𝑍 𝑠𝑚𝑖𝑡ℎ 𝑐ℎ𝑎𝑟𝑡 𝑍𝑌 𝑠𝑚𝑖𝑡ℎ 𝑐ℎ𝑎𝑟𝑡

Short Open Short Open

𝛤 Plane 𝛤 Plane

Y 𝑠𝑚𝑖𝑡ℎ 𝑐ℎ𝑎𝑟𝑡 𝑌 𝑠𝑚𝑖𝑡ℎ 𝑐ℎ𝑎𝑟𝑡

Open Short Short Open

−𝛤 Plane 𝛤 Plane

12
Addition of an Inductor in Series with a Load zin 𝑍𝐿
• Given the load z = 0.5 - j1.0 by adding 𝑍𝐿 = 𝑗1.5
• 𝑧𝑖𝑛 = 𝑧 + 𝑧𝐿 = 0.5 + 𝑗0.5. z = 0.5 - j1.0
zin = 0.5 + j0.5

.
zin

Short Open

.
z
z = 0.5 - j1.0

13
Addition of a Capacitor in Series with a Load zin 𝑍𝐶

• Given the load z = 0.5 – j0.5 by adding 𝑧𝐶 = −𝑗0.5

z = 0.5 – j0.5
• 𝑧𝑖𝑛 = 𝑧 + 𝑧𝑐 = 0.5 − 𝑗1.

Short Open

z ..
zin
z = 0.5 – j0.5 zin = 0.5 + j0.5

14
Addition of an Inductor in Shunt with a Load yin
• Given the load y = 0.5 + j0.5 by adding yL = −𝑗1.5.
• 𝑦𝑖𝑛 = 𝑦 + 𝑦𝑙 = 0.5 − 𝑗1. 𝑦𝐿 y
yin = 0.5 – j1

.
yin y = 0.5 + j0.5

Short Open

.
y

y = 0.5 + j0.5

15
Addition of an Capacitor in Shunt with a Load yin
y = 0.5 – j1
• Given the load y = 0.5 – j1 by adding yc = 𝑗0.5.
• 𝑦𝑖𝑛 = 𝑦 + 𝑦𝑐 = 0.5 − 𝑗0.5. 𝑦𝐿 y
y = 0.5 – j1

y
.. yin yin = 0.5 – j0.5

Short Open

16
How to match a load with a series L and Shunt C
• We want to realize a transformer with a series inductor and shunt capacitor to match
the complex impedance z = 0.5 – j1 to 50-ohm load. Yin
𝑍𝑖𝑛 𝑍𝐿
50Ω

z
𝑍𝐶

Short . 𝟓𝟎 Ω Open
z = 0.5 – j1.0

.z

z = 0.5 – j1.0
17
• Given the load z=0.5- j1.0, by moving up on the constant resistance r=0.5 circle on the Z Smith chart we obtain
• 𝒛𝒊𝒏 = 𝒛 + 𝒛𝒍 = 𝟎. 𝟓 + 𝒋𝟎. 𝟓. using 𝑧𝐿 = 𝑗1.5
• Since 𝑦𝑖𝑛 = 1 − 𝑗1, using yc = 𝑗1. we obtain 𝑦𝑖𝑛 + 𝑦𝑐 = 1 by moving on the constant conductance g=1 circle on
the Y Smith chart.
Yin
𝑍𝑖𝑛 𝑍𝐿
50Ω

zin . z

Short .𝟓𝟎 Ω Open

𝑍𝐶
z = 0.5 – j1.0

.
z

z = 0.5 – j1.0
18
 RF Transceiver Design
Lecture 28
Passive Components & Impedance Matching – IV

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
Alternate Design: Matching a Load with a series L and shunt L
• Given the load z=0.5- j1.0, by moving up on the constant resistance r=0.5 circle on the Z Smith chart we obtain
• 𝑧𝑖𝑛 = 𝑧 + 𝑧𝑙 = 0.5 − 𝑗0.5. using 𝑧𝐿 = 𝑗0.5
• Since 𝑦𝑖𝑛 = 1 + 𝑗1, using yc = −𝑗1. we obtain 𝑦𝑖𝑛 + 𝑦𝑐 = 1 by moving on the constant conductance g=1 circle on
the Y Smith chart.
Yin
𝑍𝑖𝑛 𝑍𝐿
50Ω

Short . Open
𝑦𝐿
z = 0.5 – j1.0

..
𝟓𝟎 Ω

zin

z = 0.5 – j1.0
2
Matching a Load with a series C and Shunt C
• Given the load z=0.5+j1.0, by moving down on the constant resistance r=0.5 circle on the Z Smith
chart we obtain 𝑧𝑖𝑛 = 𝑧 + 𝑧𝑙 = 0.5 + 𝑗0.5. using 𝑧𝑐 = −𝑗0.5
• Since 𝑦𝑖𝑛 = 1 − 𝑗1, using yc = 𝑗1. we obtain 𝑦𝑖𝑛 + 𝑦𝑐 = 1 Yin
by moving down on the constant conductance g=1 circle on the Y Smith chart. 𝑍𝑖𝑛 𝑍𝐿
50Ω

yin. . z z = 0.5 + j1.0 𝑦𝐶 z

.𝟓𝟎 Ω
Open
z = 0.5 + j1.0

3
Parallel RLC Tank
Admittance of RLC tank:
1 1
𝑌 = 𝐺 + 𝑗𝜔𝐶 + = 𝐺 + 𝑗 𝜔𝐶 −
𝑗𝜔𝐿 𝜔𝐿

At resonance:

1 1
𝜔𝑜 𝐶 − =0 𝜔𝑜 =
𝜔𝑜 𝐿 𝐿𝐶

1-nH inductor and a 1-pF capacitor resonate at 5 GHz to an

excellent (better than 1%) approximation.

4
Quality Factor Q
Q is dimensionless, and that it is proportional to the ratio of energy stored to the energy lost,
per unit time. 𝑒𝑛𝑒𝑟𝑔𝑦 𝑠𝑡𝑜𝑟𝑒𝑑
𝑄=𝜔
𝑎𝑣𝑒𝑟𝑎𝑔𝑒 𝑝𝑜𝑤𝑒𝑟 𝑑𝑖𝑠𝑠𝑖𝑝𝑎𝑡𝑒𝑑

The voltage across the network is simply 𝐼𝑖𝑛 𝑅.

The total network energy:

1
𝐸𝑡𝑜𝑡 = 𝐶(𝐼𝑝𝑘 𝑅)2
2

The average power dissipated in the resistor at resonance is therefore

simply : 1 2
𝑃𝑎𝑣𝑔 = 𝐼𝑃𝑘 𝑅
2

5
The Q of the network at resonance is then
2
𝐸𝑡𝑜𝑡 1Τ2 𝐶 𝐼𝑃𝐾 𝑅
𝑄 = 𝜔0 =
𝑃𝑎𝑣𝑔 1 2
2 𝐼𝑃𝑘 𝑅
𝐿
The quantity has the dimensions of resistance, and is sometimes called the characteristic
𝐶
impedance of the network
𝐿 𝐿
𝑍𝐶 = 𝑍𝐿 = 𝜔0 𝐿 = =
𝐿𝐶 𝐶
Additional expressions for the Q of our parallel RLC network at
resonance:
𝑅 𝑅
𝑄= = = 𝜔0 𝑅𝐶
𝑍𝐿 , 𝐶 𝜔𝑜 𝐿

6
BRANCH CURRENTS AT RESONANCE
Since the inductive and capacitive reactances are equal at resonance, the inductive and
capacitive branch currents will be equal in magnitude:
𝑉 𝐼𝑖𝑛 𝑅 𝐼𝑖𝑛 𝑅 𝐿𝐶 𝑅
𝐼𝐿 = 𝐼𝐶 = = = = 𝐼𝑖𝑛 = Q 𝐼𝑖𝑛
𝑍 𝜔0 𝐿 𝐿 𝐿 Τ𝐶

That is, the current flowing in the inductive and capacitive branches is Q times as large as the
net current.

if Q = 100 and we drive the network at resonance with a one-

ampere current source, that one ampere will flow through the
resistor, but one thousand amperes will flow through the inductor
and capacitor

7
Series RLC network BANDWIDTH AND Q
1 1
𝑍 = 𝑗𝜔𝐿 + + 𝑅 = 𝑅 + 𝑗𝜔𝐿 1 − 2
𝑗𝜔𝐶 𝜔 𝐿𝐶
𝜔0 𝐿 1 1 𝐿𝐶 1 𝐿 1 𝑍𝑜
𝑄= = = = =
𝑅 𝜔0 𝐶 𝑅 𝐶 𝑅 𝐶𝑅 𝑅
𝜔2 −𝜔02
𝑍 = 𝑅 + 𝑗𝜔𝐿 𝜔2

𝑍 = 𝑅 + 𝑗2𝐿Δ𝜔
2𝑅𝑄Δ𝜔
=𝑅+𝑗 𝜔
0
2
Due to Half Power fractional BW, 𝑍 = 2𝑅2

8
OTHER RESONANT RLC NETWORKS
Equate the impedances of the series and parallel LR sections:
2
𝜔𝑜 𝐿𝑝 𝑅𝑝 + 𝑗𝜔0 𝐿𝑝 𝑅𝑝2
𝑗𝜔0 𝐿𝑠 + 𝑅𝑠 = 𝑗𝜔0 𝐿𝑝 𝑅𝑝 = 2
𝑅𝑝2 + 𝜔𝑜 𝐿𝑝

Equating 𝑄 = 𝑅𝑝 Τ𝜔0 𝐿𝑝 = 𝜔0 𝐿𝑠 Τ𝑅𝑠

𝑅𝑃 = 𝑅𝑠 𝑄2 + 1 𝑅𝑃 = 𝑅𝑠 (𝑄2 + 1)

𝑄2 + 1 𝑄2
𝐿𝑃 = 𝐿𝑠 𝐶𝑃 = 𝐶𝑠
𝑄2 𝑄2 + 1

9
The Generalised form of Transformation:
𝑅𝑃 = 𝑅𝑆 𝑄2 + 1

𝑄2 + 1
𝑋𝑃 = 𝑋𝑆
𝑄2

Maximum Power Transfer: To maximize the power delivered to RL, XL and

Xs should be inverses so that they sum to zero and RL=RS
𝑍𝑠 = 𝑅𝑠 + 𝑗𝑋𝑠

𝑉𝑠 𝑍𝐿 = 𝑅𝐿 + 𝑗𝑋𝐿

10
Impedance matching (L Match)

𝑅𝑠

2
1 1 𝐿𝑆 𝑅𝑃 = 𝑅𝑆 𝑄2 + 1
𝑅𝑃 ≈ 𝑅𝑆 𝑄2 = 𝑅𝑆 =
𝜔𝑂 𝑅𝑆 𝐶 𝑅𝑆 𝐶
𝑄2 + 1
𝐿𝑆 𝑋𝑃 = 𝑋𝑆
𝑅𝑃 𝑅𝑆 ≈ = 𝑍𝑂2 𝑄2
𝐶
𝑋𝑃 ≈ 𝑋𝑆
𝑅𝑃
𝑄≈
𝑅𝑆

11
Example
Center frequency of 1GHz, R1= 50 ohm, R2 = 5 ohm,

𝑅1
𝑄= − 1=3
𝑅2

𝜔𝑜 𝐿 𝑄𝑅2
𝑄= 𝐿= ≈ 2.39
𝑅2 𝜔𝑜

𝑄
𝑄 = 𝜔𝑜 𝑅1 𝐶 𝐶= = 9.55
𝜔𝑜 𝑅1
If BW is narrow ?
Example: If bandwidth of 25 MHz, Q = 40.

12
𝝅 − 𝒎𝒂𝒕𝒄𝒉

RI

𝜔𝑜 𝐿2 𝑅𝑃
= − 1 = 𝑄𝑟𝑖𝑔ℎ𝑡 𝜔𝑂 𝐿1 𝑅𝑖𝑛
𝑅𝐼 𝑅𝐼 = −1 = 𝑄𝑙𝑒𝑓𝑡
𝑅𝐼 𝑅𝐼

𝜔0 𝐿1 + 𝐿2 𝑅𝑖𝑛 𝑅𝑃 𝑄𝑅𝐼
𝑄= = −1 + −1 𝐿1 + 𝐿2 =
𝑅𝐼 𝑅𝐼 𝑅𝐼 𝜔𝑂
2
𝑄𝑙𝑒𝑓𝑡 𝑄𝑟𝑖𝑔ℎ𝑡 𝑅𝑖𝑛 + 𝑅𝑃
𝐶1 = 𝐶2 = 𝑅𝐼 ≈
𝜔𝑂 𝑅𝑖𝑛 𝜔𝑂 𝑅𝑝 𝑄2

13
Example
• The required Q is still 40.
• A Q of 40 is large enough to calculate the image resistance with the approximate formula
2
𝑅𝑖𝑛 + 𝑅𝑃
𝑅𝐼 ≈ ≈ 0.054 Ω
𝑄2
• The capacitors are calculated as follows: 𝑅𝑝𝑙𝑒𝑓𝑡 = 5, 𝑅𝑃𝑟𝑖𝑔ℎ𝑡 = 50
, 𝑄𝑙𝑒𝑓𝑡 = 9.57, 𝑄𝑟𝑖𝑔ℎ𝑡 = 30.4
𝑄𝑙𝑒𝑓𝑡 𝑄𝑟𝑖𝑔ℎ𝑡
𝐶1 = ≈ 305𝑝𝐹 𝐶2 = ≈ 96.8𝑝𝐹
𝜔𝑜 𝑅𝑖𝑛 𝜔0 𝑅𝑃

Finally, the required inductance is:

𝑄𝑅𝐼
𝐿= = 0.345 𝑛𝐻
𝜔𝑂

14
T match

𝑅𝐼 𝑅𝐼
𝑄 = 𝜔0 𝑅𝐼 𝐶1 + 𝐶2 = − 1+ −1
𝑅𝑖𝑛 𝑅𝑆

𝑄
𝐶1 + 𝐶2 = 𝜔
𝑜 𝑅𝐼

𝑄𝑙𝑒𝑓𝑡 𝑅𝑖𝑛
𝐿1 =
𝜔𝑂
𝑄𝑟𝑖𝑔ℎ𝑡 𝑅𝑆
𝐿2 =
𝜔𝑂
15
 RF Transceiver Design
Lecture 29
Passive Components & Impedance Matching – V

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
TAPPED CAPACITOR RESONATOR AS AN IMPEDANCE MATCHING NETWORK

2 2
𝑅2 1Τ𝑆𝐶2 𝐶1
≈ =
𝑅𝑖𝑛 1Τ𝑆𝐶1 + 1Τ𝑆𝐶2 𝐶1 + 𝐶2

• That the network transforms a resistance Rin downward to a

value R2, or a resistance R2 upward to a value Rin.
• This circuit is used in oscillator.
• Resonator is combined with impedance transformation.
• It helps to couple energy out of tank without degrading the Q.
2
Converting Parallel RC to series:
𝑅2 𝑄22 + 1
𝑅2𝑆 = 2 𝐶2𝑆 = 𝐶2
𝑄2 + 1 𝑄22

Q2 is the Q of the parallel RC section.

The series resistor may also be viewed as the result of transforming Rin:
𝑅𝑖𝑛
𝑅𝑆 = 2
𝑄 +1
Equating the two expressions for Rs and solving for Q2 yields

𝑅2
𝑄2 = 𝑄2 + 1 − 1
𝑅𝑖𝑛

3
 𝑅2 2
𝑄2 𝑅𝑖𝑛 𝑄 + 1 − 1
𝐶2 = =
𝜔0 𝑅2 𝜔𝑜 𝑅2

Derivation of 𝐶1 : 𝐶1 𝐶2𝑠
𝐶𝑒𝑞 =
𝐶1 + 𝐶2𝑠
The network Q then can be expressed as
1 𝐶1 + 𝐶2𝑠
𝑄= =
𝜔𝑂 𝑅2𝑆 𝐶𝑒𝑞 𝜔𝑜 𝑅2𝑆 𝐶1 𝐶2𝑠
𝐶2 𝑄22 + 1
𝐶1 =
𝑄𝑄2 − 𝑄22
𝑅
The inductor L then can be expressed as: L= 𝑖𝑛
𝜔 𝑄
0

4
Example
𝑅𝑖𝑛 = 50, 𝑅2 = 5, 𝑄 = 40
𝑅𝑖𝑛
𝐿= ≈ 0.199 𝑛𝐻
𝜔0 𝑄
Next, we find the bottom capacitor, C2.
𝑅2
𝑄2 +1 −1
𝑄2 𝑅𝑖𝑛
𝐶2 = = = 401pF
𝜔0 𝑅2 𝜔𝑜 𝑅2

Finding the other capacitor's value:

𝐶2 𝑄22 +1
𝐶1 = ≈ 186𝑝𝐹
𝑄𝑄2 −𝑄22

5
TAPPED INDUCTOR MATCH

R2 must be less than Rin because, once again, we have a voltage divider
𝑄
𝑄 = 𝜔𝑂 𝑅𝑖𝑛 𝐶 𝐶=
𝜔𝑂 𝑅𝑖𝑛
𝑅2 𝑅2 𝑄𝑄2 − 𝑄22
𝐿2 = = 𝐿1 = 𝐿2
𝜔𝑜 𝑄2 𝑅 𝑄22 + 1
𝜔𝑜 𝑅 2 𝑄2 + 1 − 1
𝑖𝑛

6
DOUBLE-TAPPED RESONATOR

• This circuit boosts R2 to a larger effective parallel resistance across the whole tank
than in a standard tapped capacitor network, and then reduces this parallel resistance
by the tapped inductors to the desired value Rin.

• This technique therefore increases the required inductance and

simultaneously reduces the required capacitance, potentially
bringing both closer to comfortably realizable values.

7
Representing Q on smith-chart
For Series
𝑋𝑠
𝑅𝑠 + 𝑗𝑋𝑠 𝑄𝑛 =
𝑅𝑠
For Parallel
𝐵𝑃
𝐺𝑃 + 𝑗𝐵𝑃 𝑄𝑛 =
𝐺𝑃

1+ᴦ 1 − 𝛤𝑟 2 − 𝛤𝑖 2 2𝛤𝑟
𝑧 = 𝑟 + 𝑗𝑥 = = +𝑗
1−ᴦ 1 − 𝛤𝑟 2 + 𝛤𝑖 2 1 − 𝛤𝑟 2 + 𝛤𝑖 2

𝑥 2𝛤𝑟 2
𝑄𝑛 = = 2 1 1
𝑟 1 − 𝛤𝑟 2 − 𝛤𝑖 2 𝛤𝑟 + 𝛤𝑖 ±
𝑄𝑛
=1+ 2
𝑄𝑛

8
 2
2 1 1
𝛤𝑟 + 𝛤𝑖 ± =1+ 2
𝑄𝑛 𝑄𝑛

For x>0, the centre in the Γ plane is at (0,−1/𝑄𝑛 )

For x<0, the centre in the Γ plane is at (0,+1/𝑄𝑛 )
The radius of the circle is

1
1+
𝑄𝑛2

For 𝑄𝑛 = 5 contour, the upper and lower part of the contour are
simply one half of a circle cantered at (0,±0.2), with radius of
1.02

9
 𝑍1 = 𝑗𝑋1 𝑍3 = 𝑗𝑋3

𝑍2 = 𝑗𝑋2 𝑍𝐿𝑜𝑎𝑑

𝑍𝐼𝑁

𝑍2 = 𝑗𝑋2

𝑍1 = 𝑗𝑋1 𝑍3 = 𝑗𝑋3 𝑍𝐿𝑜𝑎𝑑

𝑍𝐼𝑁

Source:

10
 Q. Design two Tee networks to transform the load impedance 𝑍𝐿𝑜𝑎𝑑 = 50 Ω to the
input impedance 𝑍𝑖𝑛 = 10 − 𝑗15Ω 𝑤𝑖𝑡ℎ 𝑎 𝑄𝑛 𝑜𝑓 5.
𝑍𝐿2 = 𝑗35Ω 𝑍𝐿1 = 𝑗100Ω
(𝑍𝐿2 = 𝑗0.7) (𝑍𝐿1 = 𝑗2)

𝑍𝑐 = 𝑗36.7Ω
(𝑍𝑐 = 𝑗0.735)

𝑍𝑖𝑛 = 10 − 𝑗15Ω
𝑍𝑖𝑛 = 0.2 − 𝑗0.3

Source:

11
 Q. Design two Pi networks to transform the load impedance 𝑍𝐿𝑜𝑎𝑑 = 50 Ω to the
input impedance 𝑍𝑖𝑛 = 150Ω 𝑤𝑖𝑡ℎ 𝑎 𝑄𝑛 𝑜𝑓 5.
𝑍𝐿2 = 𝑗12Ω
(𝑍𝐿2 = 𝑗0.24)

𝑍𝐿1 = 𝑗17.25Ω
(𝑍𝐿1 = 𝑗0.345)
𝑍𝑐 = −𝑗28.55Ω 𝑍𝐿𝑜𝑎𝑑 = 50Ω
(𝑍𝑐 = 𝑗0.571) (𝑍𝐿𝑜𝑎𝑑 = 1)

𝑍𝑖𝑛 = 150Ω
(𝑍𝑖𝑛 = 3)

Source:

12
 RF Transceiver Design
Lecture 30
Passive Components & Impedance Matching – VI

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
RF Inductors
RF Circuits

Analog Circuits + Capacitors Inductors

Analog & Digital ICs

NMOS, PMOS, MOS Caps, Resistors, MIM

LNA
Mixer
Passive Inductors
VCOs
PA

2
3
Passive Inductors IC Options
▪ Bond wires
▪ Spiral Inductors
▪ Bond wires:

Source: https://www.fhr.fraunhofer.de/en/the-institute/core-competencies/High-
frequency-systems/High-Resolution-240-GHZ-Radar-with-SiGe-Chip.html

4
▪ Spiral Inductors:

5
Contd.

6
7
High-frequency Effects:
▪ Edge effects
▪ Substrate losses

8
9
Common geometries of Spiral Inductors

Square Hexagonal

Octagonal Circular
10
Modeling of Spiral Inductor ▪ Lumped element method
▪ Microstrip coupled line method
▪ Lumped element method:

11
 RF Transceiver Design
Lecture 31
Passive Components & Impedance Matching - VII

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
Modeling of Spiral Inductor ▪ Lumped element method
▪ Microstrip coupled line method
▪ Lumped element method:

2
 ▪ Quality Factor (Q)
Figure of Merit ▪ Self Resonating Frequency (fSR)
▪ Area
▪ Quality Factor (Q):

3
4
▪ Self Resonating Frequency (fSR):
• The frequency at which the inductance of a spiral inductor resonates with its
capacitive parasitics.
• Real inductors have capacitive parasitics.
• Real capacitors have inductive parasitics.
• Tank circuit has both L and C

5
Metal stack in Keysight ADS
Distan
Condu Thick ce from
ctor ness Min Min Substr
layer um Width Space ate(um)

ML 0.84 0.44 0.46

M5 0.54 0.28 0.28 6.46

M4 0.54 0.28 0.28 5.13

M3 0.54 0.28 0.28 3.77

M2 0.54 0.28 0.28 2.41

M1 0.54 0.23 0.23 1.05

Poly 0.2 0.18 0.25 0.38

Metal
Conductivity=5.8e7 S/m
Silicon Er=11.9, Doping=p-type
Silicon Resistivity=1200 ohm.cm

6
Design Specification: W=11 um, s=3 um, turns=2, area=300x300 um2

7
Planar Transformers - 1

8
Planar Transformers - 2

9
Vertical Transformer

P1 S1

P2 S2

10
Design Specification:
TurnsP=1,Turns_s=2, Line_width=10um , Line_spacing = 3um,
X Dim=350um , Y Dim=350um

11
12
 RF Transceiver Design
Lecture 32
Stability and Amplifier Design - I

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
Amplifier Design
• Given the S-parameters of a transistor how are we going to design the Amplifier?

• Important Considerations
➢ Stability
➢ Transducer Power Gain (GT)
➢ DC biasing
➢ Power added efficiency (PAE) (power amplifier)
➢ Bandwidth
➢ Impedance Matching
➢ Noise (Low Noise Amplifier)
➢ Output Power (power Amplifier)
➢ Linearity (LNA and Power Amplifier)

2
Signal Flow Graphs
Flow Graph techniques will provide us:
• An analysis technique applicable to S parameters
• The means to visualize the power flow in a circuit
• Each variable is designated as a node
• The S parameters and reflection coefficients are represented by branches

𝑎1 𝑏1 𝑎1 𝑆21 𝑏2
𝑆11 𝑆11 𝑆11
𝑍1 𝑍2 𝑆22
𝑆21 𝑆22
𝑏1 𝑆12 𝑎2
𝑏2 𝑎2

3
Mason Semantic
Path: a continuous succession of branches traversed in their indicated direction, no node
being encountered more than once.
Forward Path: Path connecting input to output nodes.
Input Node: A node having only out-going branches.
Output Node: A node having only in-going branches.
Path Gain: Product of the branch multiplier.
Loop: Path which originates and terminates at the same node,
no node being encountered more than once.
Loop Gain: Product of the branch multipliers around the loop.

4
 Mason’s Rule
• Select input and output nodes

• The gain T from input to output is then:

• T=(ΣkPkΔk)/Δ
➢ Pk -> path gain of the k-th forward path
➢ Δ and Δk given by:
Δ=1-(sum of all individual loop gains)
+ (sum of the loop gain products of all possible combinations of two non-touching loops)
- (sum of the loop gain products of all possible combinations of three non-touching loops)
+ (sum of the loop gain products of all possible combinations of four non-touching loops)
- …..

➢ Δk=value of Δ using loops not touching the k-th path

5
Application: Input Reflection Coefficient of a loaded 2-PortNetwork
ᴦ𝑖𝑛 𝑎
1 𝑏1 𝐼 𝑎1 𝑏2
ᴦ𝐿
𝐼1 𝑆11 𝑆22
𝑆11 𝑆12
𝑆21 𝑆22 Z0 𝑍𝐿
Z0 𝐼 𝑏1 𝑆12 𝑎2
𝑏2 𝑎2

• How many paths ?

• How many loops ?

6
Input Reflection Coefficient of a loaded 2-Port Network
The input reflection coefficient ᴦ𝐼𝑁 is defined as
ᴦ𝑖𝑛 𝑎 𝑏
1 1
𝑎1 𝑆21 𝑏2
𝐼1 𝑆11 𝑆12 ᴦ𝐿
𝑆21 𝑆22 Z0 𝑍𝐿 𝑆11 𝑆22
Z0
ᴦ𝐼𝑁 = 𝑏1 Τ𝑎1 𝑏1 𝑆12 𝑎2
𝑏2 𝑎2
𝑏 𝑃1 ∆1 +𝑃2 ∆2
ᴦ𝐼𝑁 =𝑎1 =
1 ∆
P𝑎𝑡ℎ1: 𝑃1 = 𝑆11 P𝑎𝑡ℎ2: 𝑃2 = 𝑆21 ᴦ𝐿 𝑆12
𝐷𝑒𝑡𝑒𝑟𝑚𝑖𝑛𝑎𝑛𝑡 ∶ ∆ = 1-𝑆22 ᴦ𝐿
𝐷𝑒𝑡𝑒𝑟𝑚𝑖𝑛𝑎𝑛𝑡 1: ∆1 = 1-𝑆22 ᴦ𝐿 𝐷𝑒𝑡𝑒𝑟𝑚𝑖𝑛𝑎𝑛𝑡 2: ∆2 = 1
S21 ᴦL S12
ᴦ𝐼𝑁 = 𝑆11 +
1 − S22 ᴦL
7
Stability of Amplifier
ᴦ𝑆 ᴦ𝐿

𝑍𝑆
𝑆11 𝑆12
𝑍𝐿
𝑆21 𝑆22

ᴦ𝑖𝑛 ᴦ𝑜𝑢𝑡

➢ Stability of Amplifier – It’s resistance to Oscillation

➢ Stability is analyzed by S-parameters, matching networks,
Termination.
Unconditionally Stable condition:
𝑅𝑒 𝑍𝑖𝑛 > 0, 𝑅𝑒 𝑍𝑜𝑢𝑡 > 0 𝑓𝑜𝑟 values of Zs/L
𝑅𝑒 𝑍𝑖𝑛 + 𝑍𝑠 > 0, 𝑅𝑒 𝑍𝑜𝑢𝑡 + 𝑍𝐿 > 0
8
Input Stability Circles
Stability Boundary:
Γ𝑂𝑢𝑡 Γ𝑠 = 1
𝑆12 Γ𝑆 𝑆21
𝑆22 + =1
1 − 𝑆11 Γ𝑆
∗ ∗
𝑆11 − ∆∗ 𝑆22 𝑆12 𝑆21 Where, Δ = 𝑆11 𝑆22 − 𝑆12 𝑆21
Γ𝑆 − =
𝑆11 2 − Δ 2 𝑆11 2 − Δ 2

Γ𝑆 −𝐶𝑆 = 𝑅𝑆

It defines theequation of a circle separating potentially unstable and

stable regions in the Γ𝑠 plane.
Note : Γ𝑜𝑢𝑡 Γ𝑠 = 1 defines the input stabilitycircle.
9
Output Stability Circles
Stability Boundary:
Γ𝑖𝑛 Γ𝐿 = 1
𝑆12 Γ𝐿 𝑆21
𝑆11 + =1
1 − 𝑆22 Γ𝐿
∗
𝑆22 − ∆∗ 𝑆11 𝑆12 𝑆21
Γ𝐿 − = Where, Δ = 𝑆11 𝑆22 − 𝑆12 𝑆21
𝑆22 2 − ∆ 2 𝑆22 2 − ∆ 2

Γ𝐿 −𝐶𝐿 = 𝑅𝐿

It defines theequation of a circle separating potentially unstable and

stable regions in the Γ𝐿 plane.
Note : Γ𝑖𝑛 Γ𝐿 = 1 defines the Output stabilitycircle.
10
 𝐼𝑚 ᴦ𝑠 𝐼𝑚 ᴦ𝑠
ᴦ𝑜𝑢𝑡 = 1

Potentially
Stable Unstable

ᴦ𝑜𝑢𝑡 = 1 Potentially
Unstable Stable
Re ᴦ𝑠 Re ᴦ𝑠
ᴦ𝑠 Plane ᴦ𝑠 Plane
𝑆22 > 1 𝑆22 < 1
For ᴦ𝑠 =0 we have ᴦ𝑜𝑢𝑡 =𝑆22
The point ᴦ𝑠 =0 is a stable point if 𝑆22 < 1
The point ᴦ𝑠 =0is a potentially unstable point if 𝑆22 > 1
11
Resistive loading can be used to make a transistor unconditionally stable:
New criteria for 2 Port Unconditional Stability
Potentially
Unstable
ᴦ𝑜𝑢𝑡 (ᴦ𝑠 ) = 1 RA
Potentially
Out In
Unstable Inductor
ᴦ𝑖𝑛 (ᴦ𝐿 ) = 1

In Out RB
Short Open

Capacitor

𝑅𝑒 𝑍𝑠 + 𝑍𝐼𝑁 > 0 𝑅𝑒 𝑍𝐼 + 𝑍𝑂𝑈𝑇 > 0

12
Only one resistance is sufficient
RA
Potentially ᴦ𝑜𝑢𝑡 (ᴦ𝑠 ) = 1
ᴦ𝑖𝑛 (ᴦ𝐿 ) = 1 Unstable
Out In
Potentially
Unstable
Inductance
OR

In Out RB
Short Open

Capacitance ᴦ𝑠Τ𝐿Plane

The stability circles pops out

13
Example Input stability
circle
Output stability
circle ᴦ > 1
𝑖𝑛
Four types of resistive loading to improve the
stability.
ᴦ𝑜𝑢𝑡 > 1

9Ω
1.04 0.45
71.5Ω

29Ω

500Ω

0.7
0.18(50)= 9Ω 0.58(50)=29 Ω = 14𝑚𝑆(𝑜𝑟 71.5Ω)
50 0.1
= 2𝑚𝑆(𝑜𝑟 50Ω)
50

14
 RF Transceiver Design
Lecture 33
Stability and Amplifier Design - II

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
Condition for stability
• Necessary and sufficient condition for unconditional stability:

𝑆11 2 − 𝑆22 2 + ∆ 2
𝐾= 2 𝑆12 𝑆21
K>1

∆= 𝑆11 𝑆22 -𝑆12 𝑆21 ∆ <1

• Mu Stability Test

1− 𝑆11 2
𝜇= ∗ +𝑆 𝑆
𝑆22 −∆𝑆11
>1
12 21

• The advantage of the µ test is that only a single parameter needs

to be evaluated. There are no auxiliary conditions like the K test
derivation earlier
2
Power Gain Equation Definitions
• How to select Γ𝑆 and Γ𝐿
ᴦ𝑆 ᴦ𝐿 at a given frequency to
design IMN and OMN
𝑍𝑆
𝑆11 𝑆12
𝑍𝐿
𝐸𝑆 𝑆21 𝑆22

ᴦ𝑖𝑛 ᴦ𝑜𝑢𝑡
ᴦ𝑖𝑛 ᴦ𝑜𝑢𝑡
𝑅𝑆 = 50Ω 𝑅𝐿 = 50Ω
Input Output
Matching Transistor Matching
Network Network

ᴦ𝑆 ᴦ𝐿

3
Application: Input Reflection Coefficient of a loaded 2-PortNetwork
ᴦ𝑖𝑛 𝑎
1 𝑏1 𝐼 𝑎1 𝑏2
ᴦ𝐿
𝐼1 𝑆11 𝑆22
𝑆11 𝑆12
𝑆21 𝑆22 Z0 𝑍𝐿
Z0 𝐼 𝑏1 𝑆12 𝑎2
𝑏2 𝑎2

• How many paths ?

• How many loops ?

4
Input Reflection Coefficient of a loaded 2-Port Network
The input reflection coefficient ᴦ𝐼𝑁 is defined as
ᴦ𝑖𝑛 𝑎 𝑏
1 2
𝑎1 𝑆21 𝑏2
𝐼1 𝑆11 𝑆12 ᴦ𝐿
𝑆21 𝑆22 Z0 𝑍𝐿 𝑆11 𝑆22
Z0
ᴦ𝐼𝑁 = 𝑏1 Τ𝑎1 𝑏1 𝑆12 𝑎2
𝑏1 𝑎2
𝑏 𝑃1 ∆1 +𝑃2 ∆2
ᴦ𝐼𝑁 =𝑎1 =
1 ∆
P𝑎𝑡ℎ1: 𝑃1 = 𝑆11 P𝑎𝑡ℎ2: 𝑃2 = 𝑆21 ᴦ𝐿 𝑆12
𝐷𝑒𝑡𝑒𝑟𝑚𝑖𝑛𝑎𝑛𝑡 ∶ ∆ = 1-𝑆22 ᴦ𝐿
𝐷𝑒𝑡𝑒𝑟𝑚𝑖𝑛𝑎𝑛𝑡 1: ∆1 = 1-𝑆22 ᴦ𝐿 𝐷𝑒𝑡𝑒𝑟𝑚𝑖𝑛𝑎𝑛𝑡 2: ∆2 = 1
S21 ᴦL S12
ᴦ𝐼𝑁 = 𝑆11 +
1 − S22 ᴦL
5
Amplifier Gainsᴦ ᴦ𝐿
𝑆

𝑍𝑆
𝑆11 𝑆12
𝑍𝐿
𝐸𝑆 𝑆21 𝑆22

ᴦ𝑖𝑛 ᴦ𝑂𝑢𝑡

Figures of merit to assist us in amplifier design:

𝑃𝑜𝑤𝑒𝑟 𝑑𝑒𝑙𝑖𝑣𝑒𝑟𝑒𝑑 𝑡𝑜 𝑡ℎ𝑒 𝐿𝑜𝑎𝑑 𝑃
𝐺𝑃 = 𝑃𝑜𝑤𝑒𝑟 𝑑𝑒𝑙𝑖𝑣𝑒𝑟𝑒𝑑 𝑡𝑜 𝑡ℎ𝑒 𝑁𝑒𝑡𝑤𝑜𝑟𝑘 = 𝑃 𝐿
𝑖𝑛
𝑃𝑜𝑤𝑒𝑟 𝐴𝑣𝑎𝑖𝑙𝑎𝑏𝑒 𝑓𝑟𝑜𝑚 𝑡ℎ𝑒 𝑁𝑒𝑡𝑤𝑜𝑟𝑘 𝑃𝐴𝑉𝑁
𝐺𝐴 = =𝑃
𝑃𝑜𝑤𝑒𝑟 𝐴𝑣𝑎𝑖𝑙𝑎𝑏𝑒 𝑓𝑟𝑜𝑚 𝑡ℎ𝑒 𝑆𝑜𝑢𝑟𝑐𝑒 𝐴𝑉𝑆
𝑃𝑜𝑤𝑒𝑟 𝑑𝑒𝑙𝑖𝑣𝑒𝑟𝑒𝑑 𝑡𝑜 𝑡ℎ𝑒 𝐿𝑜𝑎𝑑 𝑃𝐿
𝐺𝑇 = =
𝑃𝑜𝑤𝑒𝑟 𝐴𝑣𝑎𝑖𝑙𝑎𝑏𝑒 𝑓𝑟𝑜𝑚 𝑡ℎ𝑒 𝑆𝑜𝑢𝑟𝑐𝑒 𝑃𝐴𝑉𝑆

6
Transmission Coefficient of a loaded 2- Port Network
ᴦ𝑖𝑛

𝑆11 𝑆12 𝑆11 𝑆12

1 𝑆21 𝑆22 2 𝑍𝐿 𝑍𝑆
1 𝑆21 𝑆22 2

𝑏2 𝑃1 ∆1
𝑇21 = = ᴦ𝑂𝑈𝑇
𝑎1 ∆

Path 1: 𝑃1 = 𝑆21
𝐷𝑒𝑡𝑒𝑟𝑚𝑖𝑛𝑎𝑛𝑡 ∶ ∆ = 1-𝑆22 ᴦ𝐿

𝐷𝑒𝑡𝑒𝑟𝑚𝑖𝑛𝑎𝑛𝑡 1: ∆2 = 1
𝑏 𝑆
𝑇21 = 𝑎2 =1−S21 ᴦ
1 21 L

7
Power Gain ᴦ𝑖𝑛 ᴦ𝐿
𝑃𝑜𝑤𝑒𝑟 𝑑𝑒𝑙𝑖𝑣𝑒𝑟𝑒𝑑 𝑡𝑜 𝑡ℎ𝑒 𝑙𝑜𝑎𝑑 𝑎1 𝑏2
𝐺𝑝 =
𝑃𝑜𝑤𝑒𝑟 𝑑𝑒𝑙𝑖𝑣𝑒𝑟𝑒𝑑 𝑡𝑜 𝑡ℎ𝑒 𝑁𝑒𝑡𝑤𝑜𝑟𝑘 𝑆11 𝑆12
𝑃𝑖𝑛 𝑆21 𝑆22 𝑃𝐿 𝑍𝐿
𝑃 𝑏22− 2
𝑎2
𝐺𝑝 =𝑃 𝐿 =
𝑖𝑛 𝑎1 2 − 𝑏1 2 𝑎2
𝑏1
𝑎2 2
𝑏2
2 1− 2
𝑏2 1 − ᴦ𝐿 2
𝑏2
= =
𝑎1 𝑏1 2 𝑎1 1 − ᴦ𝑖𝑛 2
1− 𝑎
1

1 1 − ᴦ 2
2 𝐿
2
𝑆21
1 − ᴦ𝑖𝑛 1 − 𝑆22 ᴦ𝐿

8
Attributes of Power Gain ᴦ𝑖𝑛 ᴦ𝐿
𝑎1 𝑏2
For matched loads we have ᴦ𝐿 =0 and ᴦ𝑖𝑛 =𝑆11 𝑆11 𝑆12
𝑃𝑖𝑛 𝑃𝐿 𝑍𝐿
and the power gain is: 𝑆21 𝑆22

1 1 − ᴦ𝐿 2 𝑏1 𝑎2
𝐺𝑝 = 𝑆21 2
1 − ᴦ𝑖𝑛 2 1 − 𝑆22 ᴦ𝐿

𝑆21 2
= 2
1 − 𝑆11
For losslessdevice G P =1 and we have the power
conservation relation :
𝑆21 2 + 𝑆11 2 =1

9
Transducer Power Gain
ᴦ𝐿
𝑎1 𝑏2
𝑍𝑆
+ 𝑆11 𝑆12
𝐸𝑆 Z0 𝑉𝑔 𝑆21 𝑆22 Z0 𝑍𝐿

-
𝑏1 𝑎2
𝑃𝑜𝑤𝑒𝑟 𝑑𝑒𝑙𝑖𝑣𝑒𝑟𝑒𝑑 𝑡𝑜 𝑡ℎ𝑒 𝑙𝑜𝑎𝑑 𝑃𝐿
𝐺𝑇 = =
𝑃𝑜𝑤𝑒𝑟 𝐴𝑣𝑎𝑖𝑙𝑎𝑖𝑏𝑙𝑒 𝑓𝑟𝑜𝑚 𝑡ℎ𝑒 𝑠𝑜𝑢𝑟𝑐𝑒 𝑃𝐴𝑉𝑆
Power delivered to the load (rms)

𝑃𝐿 = 𝑏2 2 − 𝑎2 2 = 𝑏2 2 1 − ᴦ𝐿 2

How do we get the PowerAvailable from the source?

10
Available Power from the source and the resulting GT
𝑍𝑆
Flow graph solution : + 1 𝑎1 1 𝑎1
+ 𝑏𝑠
𝑏𝑠 𝐸𝑆 ∗
𝑉𝑔 𝑍𝑆
𝑎1 = - ᴦ𝑆 ᴦ𝑆 ∗
1 − ᴦ𝑆 2 -
2 2= 2 𝑏1 2 𝑎1 𝑏1
𝑃𝐴𝑉𝑆 = 𝑎1 − 𝑏1 𝑎1 1− 𝑏1
𝑎1 2

= 𝑎1 2 1 − ᴦ𝑆 2

|𝑏𝑠 |2 2 𝑏𝑠 2
= 1 − ᴦ𝑆 = since ᴦ𝑆 < 1
1− ᴦ𝑆 2 2 1− ᴦ𝑆 2

Transducer Power Gain :

𝑃𝐿 𝑏2 2 2 2
𝐺𝑇 = 𝑃 = 1 − ᴦ𝐿 1 − ᴦ𝑆
𝐴𝑉𝑆 𝑏𝑠

11
Signal Flow Graph for GT calculation
𝑎1 𝑏2 𝑏𝑠 1 𝑎1 𝑆21 𝑏2 𝑏2
𝑍𝑆
+
Z0
𝑆11 𝑆12
Z0 ᴦ𝑠 𝑆11 𝑆22 ᴦ𝐿
𝐸𝑆 𝑉𝑔 𝑆21 𝑆22 𝑍𝐿

- 𝑆12
𝑎2 𝑏1 𝑎2
𝑏1
𝑏2
We need to calculate
𝑏𝑠

• How many paths?

• How many loops?

12
 𝑏𝑠 1 𝑎1 𝑆21 𝑏2 𝑏2
ᴦ𝑠 𝑆11 𝑆22 ᴦ𝐿
𝑆12
𝑏1 𝑎2

𝑏2 𝑃1 ∆1 𝑆21
= =
𝑏𝑠 ∆ 1 − ᴦ𝑆 𝑆11 + 𝑆22 ᴦ𝐿 + ᴦ𝑆 𝑆21 𝑆12 ᴦ𝐿 + ᴦ𝑆 𝑆11 𝑆22 ᴦ𝐿

𝑏2 2 2 2 1− ᴦ𝑆 2 2 1− ᴦ𝐿 2
𝐺𝑇 = 1 − ᴦ𝐿 1 − ᴦ𝑆 = 𝑆21
𝑏𝑠 1−𝑆11 ᴦ𝑆 2 1−ᴦ𝑜𝑢𝑡 ᴦ𝐿 2

13
 𝑎1
Attributes of Transducer Power Gain 𝑍𝑆 𝑏1
ᴦ𝑆 ᴦ𝐿 = ᴦ𝑜𝑢𝑡 ∗ +
𝐸𝑆 𝑃𝐴𝑉𝑆 𝑍 ∗
𝑍𝑆 𝑆
𝑆11 𝑆12 𝑃𝐴𝑉𝑁 -
𝑍0 𝑆21 𝑆22 𝑍0 𝑍𝐿

𝐺𝑇 = 𝑃
𝑃𝐿
=
𝑏2 2
1 − ᴦ𝐿 2 (1 − ᴦ𝑠 2 ) 1 − ᴦ𝑠 2 2
1 − ᴦ𝐿 2
𝑏𝑠 2 𝐺𝑇 = 𝑆
𝐴𝑉𝑆
1 − 𝑆11 ᴦ𝑆 2 21 1 − 𝑆22 ᴦ𝐿 2
1 − ᴦ𝑠 2 2
1 − ᴦ𝐿 2
𝐺𝑇 = 𝑆
1 − 𝑆11 ᴦ𝑆 2 21 1 − ᴦ𝑂𝑢𝑡 ᴦ𝐿 2

Properties:
• G T ( S, S ,L ) functionof both sourceand load impedances

• G T = 𝑆21 2 for S = L = 0 (matched loads at input and output)

14
Available Power Gain ᴦ𝑆 ᴦ𝐿 = ᴦ𝑜𝑢𝑡 ∗
𝑎1 𝑏1
𝑍𝑆
𝑍𝑆
+
𝑃𝐴𝑉𝑆 𝑍 ∗ 𝑆11 𝑆12 𝑃𝐴𝑉𝑆
𝐸𝑆 𝑍0 𝑆21 𝑆22 𝑍0 𝑍𝐿
𝑆
-

𝑃𝑜𝑤𝑒𝑟 𝐴𝑣𝑎𝑖𝑙𝑎𝑏𝑒 𝑓𝑟𝑜𝑚 𝑡ℎ𝑒 𝑁𝑒𝑡𝑤𝑜𝑟𝑘 𝑃

𝐺𝐴 = 𝑃𝑜𝑤𝑒𝑟 𝐴𝑣𝑎𝑖𝑙𝑎𝑏𝑒 𝑓𝑟𝑜𝑚 𝑡ℎ𝑒 𝑆𝑜𝑢𝑟𝑐𝑒
= 𝑃𝐴𝑉𝑁
𝐴𝑉𝑆

1 − ᴦ𝑠 2 2
1
𝐺𝐴 = 𝑆
1 − 𝑆11 ᴦ𝑆 2 21 1 − ᴦ𝑂𝑢𝑡 2
Properties:
• G A (S, S ) finds applications in LNA design
• Assume a conjugate match at the output

15
 ᴦ𝑖𝑛 ᴦ𝑂𝑢𝑡
𝑅𝑆 = 50Ω

Input Output
Matching Transistor Matching 𝑅𝐿 = 50Ω
Network Network

ᴦ𝑆 ᴦ𝐿
𝑆12 ᴦ𝐿 𝑆21 𝑆12 ᴦ𝑆 𝑆21
ᴦ𝑖𝑛 = 𝑆11 + ᴦ𝑜𝑢𝑡 = 𝑆22 +
1−𝑆22 ᴦ𝐿 1 − 𝑆11 ᴦ𝑆
1 − ᴦ𝑠 2 2
1 − ᴦ𝐿 2
𝐺𝑇 = 𝑆
1 − 𝑆11 ᴦ𝑆 2 21 1 − ᴦ𝑂𝑢𝑡 ᴦ𝐿 2

1 − ᴦ𝑠 2 2
1
𝐺𝐴 = 𝑆
1 − 𝑆11 ᴦ𝑆 2 21 1 − ᴦ𝑂𝑢𝑡 2
1 2
1 − ᴦ𝐿 2
𝐺𝑃 = 𝑆
1 − ᴦ𝑖𝑛 2 21 1 − 𝑆22 ᴦ𝐿 2
16
Design Targets
How to select Γ𝑆 and Γ𝐿 at a given frequency ?

Our focus in this section will be on achieving a specific gain target

• Maximum gain GT
• Specific gain GT < GTmax

Other possible targets to be discussed are:

• Minimize noise (specific ΓS)
• Maximum output power P1dB (specific ΓL)
• Need to check that the device is stable for the Γ𝑆 and Γ𝐿 selected
How do we obtain the maximum gain?

17
 RF Transceiver Design
Lecture 34
Stability and Amplifier Design - III

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
Design Targets
How to select Γ𝑆 and Γ𝐿 at a given frequency ?

Our focus in this section will be on achieving a specific gain target

• Maximum gain GT
• Specific gain GT < GTmax

Other possible targets to be discussed are:

• Minimize noise (specific ΓS)
• Maximum output power P1dB (specific ΓL)
• Need to check that the device is stable for the Γ𝑆 and Γ𝐿 selected
How do we obtain the maximum gain?

2
Preliminary answer to maximum gain
ᴦ𝑆 ᴦ𝐿

𝑍𝑆
𝑆11 𝑆12
𝑍𝐿
𝐸𝑆 𝑆21 𝑆22

ᴦ𝑖𝑛 ᴦ𝑂𝑢𝑡

Maximum transducer power gain 𝐺𝑇 occurs when:

∗
𝑍𝑆 = 𝑍𝑖𝑛 ᴦ𝑆 = ᴦ∗𝑖𝑛
ቊ ∗ or ቊ
𝑍𝐿 = 𝑍𝑜𝑢𝑡 ᴦ𝐿 = ᴦ∗𝑜𝑢𝑡
assuming the device is stable for the Γ𝑆 and Γ𝐿 selected
3
Attributes of the Power Gains
• Which power gain to use?
𝐺𝑇 is the ultimate gain figure of merit that matters
• But we will find that:
𝐺𝑇 is easy to use with unilateral devices 𝑆12 = 0.
𝐺𝑇 is challenging to use with bilateral devices 𝑆12 ≠ 0.
• For bilateral transistors, we shall start the design of the amplifier
using 𝐺𝐴 or 𝐺𝑃 and make these power gains equal to 𝐺𝑇 by
appropriate matching:
∗
𝐺𝑇 Γ𝑆 = Γ𝑖𝑛 , Γ𝐿 = 𝐺𝑃 (Γ𝐿 )
∗
𝐺𝑇 Γ𝑆 , Γ𝐿 = Γ𝑜𝑢𝑡 = 𝐺𝐴 (Γ𝑆 )
• Note: 𝐺𝑇𝑚𝑎𝑥 = 𝐺𝐴𝑚𝑎𝑥 = 𝐺𝑃𝑚𝑎𝑥

4
Unilateral Case: S12=0
When 𝑆12 = 0 𝑛𝑜 𝑓𝑒𝑒𝑑𝑏𝑎𝑐𝑘 the device is stable if 𝑆11 < 1 𝑎𝑛𝑑 𝑆22 < 1
We have then ᴦ𝑖𝑛 = 𝑆11 and ᴦ𝑜𝑢𝑡 = 𝑆22 and the transducer power gain:
1 − ᴦ𝑠 2 1 − ᴦ 𝐿
2
𝐺𝑇 = 2 𝑆21 2
1 − 𝑆11 ᴦ𝑆 1 − 𝑆22 ᴦ𝐿 2
Becomes the unilateral transducer power gain:
1 − ᴦ𝑠 2 2
1 − ᴦ𝐿 2
𝐺𝑇𝑈 = × 𝑆21 ×
1 − 𝑆11 ᴦ𝑆 2 1 − 𝑆22 ᴦ𝐿 2

Mismatch gain Defined for 50 Ω Mismatch gain

𝐺𝑆 × 𝐺0 × 𝐺𝐿
𝐺𝑆 and 𝐺𝐿 Can be larger than 1. 𝑆21 which is 𝐺𝑇 for 𝑍𝑆 = 𝑍𝐿 = 50Ω
might not be optimal terminations

5
• The maximum unilateral gain 𝐺𝑇𝑈𝑚𝑎𝑥 is obtained for :
∗ ∗
Γ𝑆 = 𝑆11 and Γ𝐿 = 𝑆22
Which gives us:
1 2
1
𝐺𝑇𝑈 𝑚𝑎𝑥 = 2
× 𝑆21 × 2
1 + 𝑆11 1 + 𝑆22

Mismatch gain Mismatch gain

𝐺𝑆𝑚𝑎𝑥 × 𝐺0 × 𝐺𝐿𝑚𝑎𝑥
𝑆21
𝐺𝑇𝑈 𝑚𝑎𝑥 = 𝐾− 𝐾2 − 1
𝑆12
𝑆11 2 − 𝑆22 2 + ∆ 2
Where, 𝐾 = and ∆= 𝑆11 𝑆22 -𝑆12 𝑆21
2 𝑆12 𝑆21
If K≥1, than the maximum stable gain 𝐺𝑚𝑠𝑔 is given as:
𝑆21
𝐺𝑚𝑠𝑔 = 𝑆12

6
Bilateral case: 𝑺𝟏𝟐 ≠ 𝟎 ᴦ𝑂𝑢𝑡
ᴦ𝑖𝑛
𝑅𝑆 = 50Ω

Input Output
Matching Transistor Matching 𝑅𝐿 = 50Ω
Network Network

ᴦ𝑆 ᴦ𝐿
𝑆12 ᴦ𝐿 𝑆21 𝑆12 ᴦ𝑆 𝑆21
ᴦ𝑖𝑛 = 𝑆11 + ᴦ𝑜𝑢𝑡 = 𝑆22 +
1−𝑆22 ᴦ𝐿 1 − 𝑆11 ᴦ𝑆
Maximum transducer power gain 𝐺𝑇 occurs when:
∗
𝑍𝑆 = 𝑍𝑖𝑛 ᴦ𝑆 = ᴦ∗𝑖𝑛
ቊ or ቊ
∗
𝑍𝐿 = 𝑍𝑜𝑢𝑡 ᴦ𝐿 = ᴦ∗𝑜𝑢𝑡
𝑆12 𝑆21 ᴦ𝑆 𝑆12 𝑆21 ᴦ𝐿
ᴦ∗𝐿 =𝑆22 + ᴦ𝑆∗ = 𝑆11 +
1−𝑆11 ᴦ𝑆 1 − 𝑆22 ᴦ𝐿
7
We can solve for Γ𝑆 by first rewriting these equations as follows:

∗ 𝑆∗ 𝑆22 − ∆ᴦ𝑆
ᴦ𝑆 = ∗ 𝑆12 21
𝑆11 + 1Τᴦ∗ −𝑆 ᴦ∗𝐿 =
𝐿
∗
22
1 − 𝑆11 ᴦ𝑆

ᴦ𝑆 1 − 𝑆22 2
+ ᴦ𝑆2 ∆𝑆22
∗ ∗ ∗
− 𝑆11 = ᴦ𝑆 ∆𝑆11 ∗ ∗
𝑆22 − 𝑆11 2 − ∆𝑆12 𝑆21
∗ ∗ ∗
+ 𝑆11 1 − 𝑆22 2 + 𝑆12 𝑆21 𝑆22

∗ ∗ ∗ ∗
Using the result that ∆(𝑆11 𝑆22 − 𝑆12 𝑆21 ) allows this to be rewritten as a quadratic equation for Γ𝑆 :

∗
(𝑆11 − ∆𝑆22 )ᴦ𝑆2 + ∆ 2 − 𝑆11 2 + 𝑆22 2 ∗
− 1 ᴦ𝑆 + 𝑆11 − ∆∗ 𝑆22

8
 𝐵1 ± 𝐵12 −4 𝐶1 2
ᴦ𝑆 = 2𝐶1

Similarly, the solution for ᴦ𝐿 can be written as

𝐵1 ± 𝐵22 −4 𝐶2 2
ᴦ𝐿 = 2𝐶2
The variable 𝐵1 , 𝐶1 , 𝐵2 , 𝐶2 defined as
𝐵1 = 1 + 𝑆11 2 − 𝑆22 2 - ∆ 2
𝐵2 = 1 + 𝑆22 2 − 𝑆11 2 - ∆ 2
∗
𝐶1 = 𝑆11 - ∆𝑆22
∗
𝐶2 = 𝑆22 - ∆𝑆11
Solutions are only possible if the quantity within the square root is
positive, and it can be shown that this is equivalent to requiring K > 1.

9
Design an amplifier for maximum gain at 4 GHz using single-stub matching sections. Calculate
and plot the input return loss and the gain from 3 to 5 GHz. The transistor is a GaAs MESFET
with the following scattering parameters (Z0 = 50):

f(GHz) 𝑺𝟏𝟏 𝑺𝟏𝟐 𝑺𝟐𝟏 𝑺𝟐𝟐

3 0.8∟−89° 0.03∟56° 1.86∟99° 0.76∟−41°
4 0.72∟−116° 0.03∟57° 2.60∟76° 0.73∟−54°
5 0.66∟−142° 0.03∟62° 2.39∟54° 0.72∟−65°

Steps:
1) Find the stability condition.
2) Find the value of Γ𝑆 and Γ𝐿 .
3) Find the gain.
4) Design matching network.

10
 Stability: K ∆
F(GHz)
Find the value of Γ𝑆 and Γ𝐿 .
3 0.77 0.592

𝐵1 ± 𝐵22 −4 𝐶2 2
4 1.19 0.487
𝐵1 ± 𝐵12 −4 𝐶1 2
ᴦ𝑆 = = 0.872 < 123° ᴦ𝐿 = = 0.876 < 61° 5 1.53 0.418
2𝐶1 2𝐶2

Find the gain:

1
𝐺𝑆 = 1− ᴦ 2 = 4.14 = 6.20dB
𝑆

𝐺𝑂 = 𝑆21 2 = 6.76 = 8.30 dB

1 − ᴦ𝐿 2
𝐺𝐿 = = 1.67 = 2.22𝑑𝐵
1 − 𝑆22 ᴦ𝐿 2
𝐺𝑇𝑚𝑎𝑥 = 6.20 + 8.30 + 2.22 = 16.7 𝑑𝐵
11
Length of
Open-circuited
Stub 0.260λ

ᴦ𝑆
Stub
Length of
Series line
0.120λ

𝑦𝑠

12
 0.206λ
50Ω

50Ω 0.120λ 0.206λ

50Ω
50Ω

50Ω
0.206λ

20
10
𝐺𝑇 − 𝑅𝐿 (𝑑𝐵)

-10

-20

3.5 4 4.5 5
Frequency(GHz)

13
 RF Transceiver Design
Lecture 35
Stability and Amplifier Design - IV

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
Unilateral figure of merit
• For many transistors |S12| is small enough to be ignored, and the device can be assumed
to be unilateral.

• The error in the transducer gain caused by approximating |S12| as zero is given by the
ratio GT/GTU.
1 𝐺 1
< 𝐺 𝑇 < (1−𝑈)2
(1+𝑈)2 𝑇𝑈

• 𝑈 is defined as the unilateral figure of merit,

𝑆12 𝑆21 𝑆11 𝑆22

𝑈=
1 − 𝑆11 2 1 − 𝑆22 2

2
Expression for Gs and Gl
For Bilateral cases:
1 − ᴦ𝑆 2 1 − ᴦ𝐿 2
𝐺𝑆 = 𝐺𝑆 =
1 − 𝑆11 ᴦ𝑆 2 1 − 𝑆22 ᴦ𝐿 2
For Matched conditions:
1 1
𝐺𝑆𝑚𝑎𝑥 = 𝐺𝐿𝑚𝑎𝑥 =
1 − 𝑆11 2 1 − 𝑆22 2
Define normalized gain factors 𝑔𝑠 and 𝑔𝐿 as:
𝐺𝑆 1 − ᴦ𝑆 2
𝑔𝑆 = = 2
1 − 𝑆11 2
𝐺𝑆𝑚𝑎𝑥 1 − 𝑆11 ᴦ𝑆
𝐺𝐿 1 − ᴦ𝐿 2
𝑔𝐿 = = 2 1 − 𝑆22 2
𝐺𝐿𝑚𝑎𝑥 1 − 𝑆22 ᴦ𝐿

Then we have that 0 ≤ gS ≤ 1 and 0 ≤ gL ≤ 1.

3
 ∗
𝑔𝑆 𝑆11 1−𝑔𝑆 1− 𝑆11 2
ᴦ𝑆 − 1− 1−𝑔 𝑆 2 =
𝑆 11 1− 1−𝑔𝑆 𝑆11 2

Constant gain circles for input section:

∗
𝑔𝑆 𝑆11 1−𝑔𝑆 1− 𝑆11 2
𝐶𝑆 = 2 𝑅𝑆 =
1 − 1 − 𝑔𝑆 𝑆11 1− 1−𝑔𝑆 𝑆11 2

Constant gain circles for output section:

∗
𝑔𝐿 𝑆22
𝐶𝐿 = 1−𝑔𝐿 1− 𝑆22 2
1 − 1 − 𝑔𝐿 𝑆22 2 𝑅𝐿 = 1− 1−𝑔𝐿 𝑆22 2

4
Attributes
∗ ∗
• The Angle of circles are defined by 𝑆11 and 𝑆22

• when gS (or gL) = 1 (maximum gain)

-> The radius RS (or RL) = 0,
∗ ∗
-> The center reduces to 𝑆11 and 𝑆22

• The 0 dB gain circles will always pass through the center of the Smith chart.

• Example: Gain=11 dB, freq= 4.0 GHz,

• Plot constant-gain circles for 𝐺𝑆 = 2 and 3 dB, and 𝐺𝐿 = 0 and 1 dB.

5
 f(GHz) 𝑺𝟏𝟏 𝑺𝟏𝟐 𝑺𝟐𝟏 𝑺𝟐𝟐
3 0.8∟ −90° 0 2.8∟100° 0.66∟ − 50°
4 0.75∟ −120° 0 2.5∟80° 0.60∟ − 70°
5 0.71∟ −140° 0 2.3∟60° 0.58∟ − 85°

1) Find stability. K>1, Δ < 1,

2) Find Maximum gain
1 1
𝐺𝑆𝑚𝑎𝑥 = = 2.29 = 3.6dB 𝐺𝐿𝑚𝑎𝑥 = = 1.56 = 1.9dB
1− 𝑆11 2 1− 𝑆22 2

2
𝐺0 = 𝑆11 = 6.25 = 8 𝑑𝐵

𝐺𝑇𝑈𝑚𝑎𝑥 = 3.6 + 1.9 + 8 = 13.5𝑑𝐵

6
𝐺𝑆 = 3 𝑑𝐵 𝑔𝑆 = 0.875 𝐶𝑆 = 0.706∟120° 𝑅𝑆 = 0.166
𝐺𝑆 = 2 𝑑𝐵 𝑔𝑆 = 0.691 𝐶𝑆 = 0.627∟120° 𝑅𝑆 = 0.294
𝐺𝐿 = 1 𝑑𝐵 𝑔𝐿 = 0. 806 𝐶𝐿 = 0.520∟70° 𝑅𝐿 = 0.303
𝐺𝐿 = 0 𝑑𝐵 𝑔𝐿 = 0.640 𝐶𝐿 = 0.440∟70° 𝑅𝐿 = 0.440

7
8
We choose G S = 2 dB and G L = 1 dB, for an overall amplifier gain of 11 dB.

ᴦ𝑆 = 0.33∟120° 𝑎𝑛𝑑 ᴦ𝑆 = 0.22∟70°

0.045λ
50Ω

50Ω
50Ω 0.179λ 0.432λ

50Ω
50Ω

50Ω
0.100λ

9
Low noise amplifier design
NF of two-port amplifier can be expressed as:
+ 𝑉𝑛 -
Noiseless +
𝑖𝑠 𝑖𝑛 Two-port 𝑉2
𝑌𝑆 network
-

Total output noise power is proportional to the mean square of the short-circuit current
at the input port of noise free amplifier.
The noise power due to source alone is proportional to mean square
of source current.
2
𝑖𝑠𝑐
𝐹= 2
𝑠𝑖ഥ

10
 RF Transceiver Design
Lecture 36
Low Noise Amplifier Design - I

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
Low noise amplifier design
NF of two-port amplifier can be expressed as:
+ 𝑉𝑛 -
Noiseless +
𝑖𝑠 𝑖𝑛 Two-port 𝑉2
𝑌𝑆 network
-

Total output noise power is proportional to the mean square of the short-circuit current
at the input port of noise free amplifier.
The noise power due to source alone is proportional to mean square
of source current.
2
𝑖𝑠𝑐
𝐹= 2
𝑠𝑖ഥ

2
 𝑖𝑠𝑐 = −𝑖𝑠 + 𝑖𝑛 + 𝑣𝑛 𝑌𝑠

2 2
𝑖𝑠𝑐 = −𝑖𝑠 + 𝑖𝑛 + 𝑣𝑛 𝑌𝑠
Noise from the source and noise from two port are uncorrelated,
2
𝑖𝑠 (𝑖𝑛 + 𝑣𝑛 𝑌𝑠 )=0 𝑖𝑠𝑐 = 𝑖𝑠2 +(𝑖𝑛 + 𝑣𝑛 𝑌𝑠 )2

(𝑖𝑛 + 𝑣𝑛 𝑌𝑠 )2
𝐹 =1+
𝑣𝑛 𝑎𝑛𝑑 𝑖𝑛 𝑎𝑟𝑒 𝑐𝑜𝑟𝑟𝑒𝑙𝑎𝑡𝑒𝑑 𝑖𝑠2
Uncorrelated to 𝑣𝑛 (𝑖𝑛𝑢 )

𝑖𝑛
correlated to 𝑣𝑛 (𝑖𝑛𝑐 )

𝑖𝑛 = 𝑖𝑛𝑢 +𝑖𝑛𝑐
𝑖𝑛𝑐 = 𝑌𝑐 𝑣𝑛

3
After multiplying 𝑖𝑛 by 𝑣𝑛∗ ,
𝑣𝑛∗ 𝑖𝑛 = 𝑌𝑐 𝑣𝑛2

(𝑖𝑛𝑢 + 𝑣𝑛 (𝑌𝑐 + 𝑌𝑠 )2
𝐹 =1+
𝑖𝑠2
4𝑘𝑇𝑜 𝐺𝑢 𝐵 + 𝐺𝑠 + 𝑗𝐵𝑠 + 𝐺𝑐 + 𝑗𝐵𝑐 2 4𝑘𝑇𝑜 𝑅𝑛 𝐵
𝐹 = 1+
4𝑘𝑇𝑜 𝐺𝑠 𝐵
𝑌𝑐 = 𝐺𝑐 + 𝑗𝐵𝑐 and 𝑌𝑠 = 𝐺𝑠 +𝑗𝐵𝑠

The noise factor can be minimized by selecting 𝐵𝑠 = - 𝐵𝑐

𝐺 𝑅𝑛 2
𝐹|𝐵𝑠= − 𝐵𝑐 = 1 + 𝐺𝑢 + 𝐺𝑠 + 𝐺𝑐
𝑠 𝐺𝑠

𝑑𝐹|𝐵𝑠 = − 𝐵𝑐 𝐺𝑢 2𝐺𝑠 𝐺𝑠 +𝐺𝑐 − 𝐺𝑠 +𝐺𝑐 2

=- + 𝑅𝑛 =0
𝑑𝐺𝑠 𝐺𝑠2 𝐺𝑠2

4
 𝐺𝑢
𝐺𝑠 = 𝐺𝑐2 +
𝑅𝑛
Value of 𝐺𝑠 𝑎𝑛𝑑 𝐵𝑠 gives source admittance (𝑌𝑜𝑝𝑡 ), which results in minimum noise figure.
𝐺𝑢 𝑅𝑛 2
𝐹𝑚𝑖𝑛 = 𝐹|𝑌𝑠 =𝑌𝑜𝑝𝑡 = 1 + + 𝐺 + 𝐺𝑐
𝐺𝑜𝑝𝑡 𝐺𝑜𝑝𝑡 𝑜𝑝𝑡
𝑅𝑛 2 2
𝐹 = 𝐹𝑚𝑖𝑛 + 𝐺𝑠 − 𝐺𝑜𝑝𝑡 + 𝐵𝑠 − 𝐵𝑜𝑝𝑡
𝐺𝑠

𝑟 2
𝐹 = 𝐹𝑚𝑖𝑛 + 𝑔𝑛 𝑦𝑠 − 𝑦𝑜𝑝𝑡
𝑠

𝑌 𝐺𝑠 +𝑗𝐵𝑠
𝑦𝑠 = 𝑌𝑠 = 𝑌𝑜
= 𝑔𝑠 + 𝑗𝑏𝑠
𝑜

𝑌𝑜𝑝𝑡 𝐺𝑜𝑝𝑡 +𝑗𝐵𝑜𝑝𝑡

𝑦𝑜𝑝𝑡 = = = 𝑔𝑜𝑝𝑡 + 𝑗𝑏𝑜𝑝𝑡
𝑌𝑜 𝑌𝑜

5
Converting admittance to reflection coefficient.

1 1 − ᴦ𝑆 1 1 − ᴦ𝑜𝑝𝑡
𝑌𝑆 = 𝑌𝑜𝑝𝑡 =
𝑍𝑜 1 + ᴦ𝑆 𝑍𝑜 1 + ᴦ𝑜𝑝𝑡

2
2 4 ᴦ𝑆 − ᴦ𝑜𝑝𝑡
𝑌𝑆 − 𝑌𝑜𝑝𝑡 = 2 2 2
𝑍𝑜 1 + ᴦ 1 + ᴦ𝑜𝑝𝑡
𝑜𝑝𝑡

1 1−ᴦ𝑆 1−ᴦ𝑆 ∗ 1 1− ᴦ𝑆 2
𝐺𝑠 = 𝑅𝑒 𝑌𝑠 = + 1+ᴦ ∗ =
2𝑍𝑜 1+ᴦ𝑆 𝑆 𝑍𝑜 1+ᴦ𝑆 2

2
4𝑅𝑁 ᴦ𝑆 − ᴦ𝑜𝑝𝑡
𝐹 = 𝐹𝑚𝑖𝑛 + 2
𝑍𝑜 1 − ᴦ 2 1 + ᴦ
𝑆 𝑜𝑝𝑡

6
For the fixed value of the NF,this equation will represent the circles in 𝝘S plane.

Noise figure parameter N is given by:

2
ᴦ𝑆 −ᴦ𝑜𝑝𝑡 𝐹−𝐹𝑚𝑖𝑛 2
𝑁= = 4𝑅 1 + ᴦ𝑜𝑝𝑡
1− ᴦ𝑆 2 𝑁 Τ𝑍0

The circle equation is given by:

2
ᴦ𝑜𝑝𝑡 𝑁(𝑁+1− ᴦ𝑜𝑝𝑡 )
ᴦ𝑆 − 𝑁+1 = (𝑁+1)

ᴦ𝑜𝑝𝑡
𝐶𝐹 =
𝑁+1
2
𝑁(𝑁 + 1 − ᴦ𝑜𝑝𝑡 )
𝑅𝐹 =
(𝑁 + 1)
7
Examples
S-parameters at 4 GHz.
𝑆11 = 0.6∟ − 60 𝑆12 = 0.05∟26

𝑆21 = 1.9∟81 𝑆22 = 0.5 ∟ − 60

𝐹𝑚𝑖𝑛 = 1.6𝑑𝐵 ᴦ𝑜𝑝𝑡 = 0.62∟100 and RN = 20

Assume device is unilateral, find error in GT.

Design an amplifier with 2 dB of NF.
1) Find stability. K = 2.78 and Δ = 0.37
2) Calculate Unilateral Figure of merit
𝑆12 𝑆21 𝑆11 𝑆22
𝑈= = 0.059
1− 𝑆11 2 1− 𝑆22 2

8
 1 𝐺𝑇 1
2
< < 2
1+𝑈 𝐺𝑇𝑈 1−𝑈

𝐺𝑇
0.891 < <1.130
𝐺𝑇𝑈

0.891 < 𝐺𝑇 − 𝐺𝑇𝑈 <1.130

𝐹−𝐹𝑚𝑖𝑛 2 1.58−1.445 2
N = 4𝑅 1 + ᴦ𝑜𝑝𝑡 = 1 + 0.62∟100°
𝑁 Τ𝑍0 4(20Τ50)

ᴦ𝑜𝑝𝑡
𝐶𝐹 = = 0.56∟100°
𝑁+1
2
𝑁(𝑁+1− ᴦ𝑜𝑝𝑡 )
𝑅𝐹 = = 0.24
(𝑁+1)

9
 −0.50 < 𝐺𝑇 − 𝐺𝑇𝑈 < 0.53 𝑑𝐵

𝐹 − 𝐹𝑚𝑖𝑛 2 1.58 − 1.445 2

𝑁= 1 + ᴦ𝑜𝑝𝑡 = 1 + 0.62∟100° = 0.0986
4𝑅𝑁 Τ𝑍𝑜 4 20Τ50
ᴦ𝑜𝑝𝑡
𝐶𝐹 = 𝑁+1 =0.56∟100°

2
𝑁(𝑁+1− ᴦ𝑜𝑝𝑡 )
𝑅𝐹 = (𝑁+1)
=0.24

𝑮𝒔 (𝒅𝑩) 𝒈𝒔 𝑪𝑺 𝑹𝑺
1 0.805 0.52∟60° 0.3
1.5 0.904 0.56∟60° 0.205
1.7 0.946 0.58∟60° 0.150

10
 Noise figure
circle Gain circle

1
𝐺𝐿 = 1− 𝑆 2 = 1.25dB
22
2 𝐹 = 2.0 𝑑𝐵
𝐺𝑜 = 𝑆21 = 5.58𝑑𝐵 𝐺𝑆 = 1.7𝑑𝐵
ᴦ𝑜𝑝𝑡
𝐹 = 1.6𝑑𝐵 𝐺𝑆 = 1.5𝑑𝐵
𝐺𝑇𝑈 = 𝐺𝑆 + 𝐺𝑜 + 𝐺𝐿 = 8.53 𝑑𝐵 𝐺𝑆 = 1.0𝑑𝐵

ΓS =0.53<75◦

11
 RF Transceiver Design
Lecture 37
Low Noise Amplifier Design - II

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
MOSFET Two –Port Noise Parameter
The MOSFET is comprised of two sources.

Drain Current noise Gate Current noise

2 2
𝑖𝑛𝑑 = 4𝑘𝑇𝛾𝑔𝑑𝑜 ∆𝑓 𝑖𝑛𝑔 = 4𝑘𝑇𝛾𝑔𝑔 ∆𝑓

𝜔2 𝐶𝑔𝑠
2
𝑔𝑔 =
5𝑔𝑑𝑜
Gate noise is correlated with the drain noise with
correlation coefficient c.
∗
𝑖𝑛𝑔 .𝑖𝑛𝑑
c=
2 𝑖2
𝑖𝑛𝑔 𝑛𝑑

2
Two fundamental MOSFET noise sources back to the input port:
1. Voltage
2. Current
Drain Current noise back to the input as noise voltage:
2
𝑖𝑛𝑑 4𝐾𝑇𝛾𝑔𝑑0 ∆𝑓
𝑒𝑛2 = 𝑔2 = 2
𝑚 𝑔𝑚

𝑒𝑛2 𝛾𝑔𝑑0
𝑅𝑛 = = 2
4𝐾𝑇∆𝑓 𝑔𝑚
Noisy drain current also flows when the input is open circuited
2 𝑗𝜔𝐶 2
2 𝑖𝑛𝑑 𝑔𝑠 2
𝑖𝑛1 = 2 = 𝑒𝑛2 𝑗𝜔𝐶𝑔𝑠
𝑔𝑚

Total input current noise = reflected drain noise +

induced gate current noise
3
 correlated with drain current noise
Induced gate noise current
uncorrelated with drain current noise

𝑖𝑛1 +𝑖𝑛𝑔𝑐 𝑖𝑛𝑔𝑐 𝑖𝑛𝑔𝑐

Correlation admittance(𝑌𝑐 ) = = 𝑗𝜔𝐶𝑔𝑠 + = 𝑗𝜔𝐶𝑔𝑠 +𝑔𝑚
𝑒𝑛 𝑒𝑛 𝑖𝑛𝑑

∗
𝑖𝑛𝑔 𝑖𝑛𝑑 2
𝑖𝑛𝑔
𝑌𝑐 = 𝑗𝜔𝐶𝑔𝑠 + 𝑔𝑚 2 = 𝑗𝜔𝐶𝑔𝑠 + 𝑔𝑚 .c 2
𝑖𝑛𝑑 𝑖𝑛𝑑

𝑔𝑚 𝛿
𝑌𝑐 = 𝑗𝜔𝐶𝑔𝑠 + .𝑐 .𝜔𝐶𝑔𝑠
𝑔𝑑𝑜 5𝛾

Assume c to be purely imaginary,

𝛿
𝑌𝑐 = 𝑗𝜔𝐶𝑔𝑠 1 − 𝛼 𝑐
5𝛾

4
 𝑔𝑚 𝑇ℎ𝑒 𝑝𝑎𝑟𝑎𝑚𝑒𝑡𝑒𝑟 𝛼 𝑒𝑥ℎ𝑖𝑏𝑖𝑡𝑠 𝑎 𝑣𝑎𝑙𝑢𝑒 𝑜𝑓 1 𝑓𝑜𝑟 𝑙𝑜𝑛𝑔 𝑐ℎ𝑎𝑛𝑛𝑒𝑙 𝑑𝑒𝑣𝑖𝑐𝑒𝑠,
𝛼=
𝑔𝑑0 𝑤ℎ𝑒𝑟𝑒𝑎𝑠 𝑖𝑡 𝑔𝑟𝑎𝑑𝑢𝑎𝑙𝑙𝑦 𝑑𝑖𝑚𝑖𝑛𝑖𝑠ℎ𝑒𝑠 𝑎𝑠 𝑡ℎ𝑒 𝑐ℎ𝑎𝑛𝑛𝑒𝑙 𝑠𝑖𝑧𝑒 𝑑𝑒𝑐𝑟𝑒𝑎𝑠𝑒𝑠.

Parameter Expression
𝐺𝑡 0
𝐵𝑡 𝛿
𝜔𝐶𝑔𝑠 1 − 𝛼 𝑐
5𝛾

𝑅𝑛 𝛾𝑔𝑑𝑜 𝛾 1
2 = 𝛼 .𝑔
𝑔𝑚 𝑚

𝐺𝑢 𝛿𝜔2 𝐶𝑔𝑠 2 (1 − 𝑐 2 )
5𝑔𝑑𝑜

5
 𝐺𝑢 𝛿
𝐺𝑜𝑝𝑡 = + 𝐺𝑐2 = 𝛼𝜔𝐶𝑔𝑠 1− 𝑐 2
𝑅𝑛 5𝛾

2 𝜔 2
𝐹𝑚𝑖𝑛 = 1 + 2𝑅𝑛 𝐺𝑜𝑝𝑡 + 𝐺𝑐 = 1 + 𝛾𝛿 1 − 𝑐
5 𝜔𝑇

𝜔 𝐹𝑚𝑖𝑛 (dB)
𝜔𝑇
20 0.5
15 0.6
10 5
5 1.6

𝐹𝑚𝑖𝑛 𝛾 = 2, 𝛿 = 4

6
Noise optimization with power constraints
𝑅𝑛 2 2
𝐹 = 𝐹𝑚𝑖𝑛 + 𝐺𝑠 − 𝐺𝑜𝑝𝑡 + 𝐵𝑠 − 𝐵𝑜𝑝𝑡
𝐺𝑠

Assume 𝐵𝑠 −
෥ 𝐵𝑜𝑝𝑡
𝑅𝑛 2
𝐹 = 𝐹𝑚𝑖𝑛 + 𝐺𝑠 − 𝐺𝑜𝑝𝑡
𝐺𝑠

𝐺𝑜𝑝𝑡 can be rearranged in terms of quality factor

𝐺𝑜𝑝𝑡 𝛿 2
𝑄𝑜𝑝𝑡 = =𝛼 1− 𝑐
𝜔𝐶𝑔𝑠 5𝛾

1
𝑄𝑠 =
𝜔𝐶𝑔𝑠 𝑅𝑆

7
 2
𝛾 𝑄𝑜𝑝𝑡
𝐹 = 𝐹𝑚𝑖𝑛 + 1−
𝛼𝑔𝑚 𝑅𝑆 𝑄𝑆
𝜇𝑛 𝐶𝑜𝑥 𝑊
Drain current : 𝐼𝐷 = 𝑉𝑔𝑠 − 𝑉𝑡 𝑉𝑔𝑠 − 𝑉𝑡 || 𝐿𝐸𝑠𝑎𝑡
2 𝐿
𝐼𝐷 𝑚𝑎𝑦 𝑏𝑒 𝑟𝑒𝑤𝑟𝑖𝑡𝑡𝑒𝑛 𝑎𝑠 ∶
𝜌2
𝐼𝐷 = 𝑊𝐿𝐶𝑜𝑥 𝑉𝑠𝑎𝑡 𝐸𝑠𝑎𝑡
1+𝜌
𝑉𝑜𝑑
𝜌=
𝐿𝐸𝑠𝑎𝑡
Power dissipation can be written as:
𝜌2
𝑃𝐷 = 𝑉𝐷𝐷 𝐼𝐷 = 𝑉𝐷𝐷 WL𝐶𝑜𝑥 𝑉𝑠𝑎𝑡 𝐸𝑠𝑎𝑡 1+𝜌
𝑔𝑚 = 𝛼𝑔𝑑𝑜

8
Optimum Width:
3 1
𝑊𝑜𝑝𝑡 𝑃 =
2 𝜔𝐿𝐶𝑜𝑥 𝑅𝑠
With device width 𝑊𝑜𝑝𝑡,𝑃 the noise figure can be obtained:
𝛾 𝜔 𝜔
𝐹𝑚𝑖𝑛,𝑃 ≈ 1 + 2.4 𝐹𝑚𝑖𝑛 = 1 + 2.3
𝛼 𝜔𝑇 𝜔𝑇
𝝎𝑻 Τ𝝎 𝑭𝒎𝒊𝒏 (𝒅𝑩) 𝐹𝑚𝑖𝑛,𝑃 (dB)
20 0.5 1.1
15 0.6 1.4
10 0.9 1.9
5 1.6 3.3
𝛾 = 2, 𝛿 = 4, 𝛼 = 0.85
9
Low Noise Amplifier(LNA) used to amplify signal received by antenna without degrading its
signal to noise ratio.

Basic Parameter:
1. NOISE FIGURE
𝐼𝑛𝑝𝑢𝑡 𝑆𝑁𝑅
F=𝑂𝑢𝑡𝑝𝑢𝑡 𝑆𝑁𝑅

𝑁𝐹 = 10𝑙𝑜𝑔𝐹
2. GAIN
𝑉𝑜𝑢𝑡
Voltage 𝑔𝑎𝑖𝑛 = 10log
𝑉𝑖𝑛
10
3. Input Matching
4. Linearity:

5. Stability
4 𝛼1
𝐴𝐼𝐼𝑃3 =
3 𝛼3

11
• LNA design requirement
➢ Broad-band input matching to minimize the return loss.
➢ Sufficient gain to suppress the noise of mixer.
➢ Low noise figure to enhance receiver sensitivity.
➢ Low power consumption to increase battery life.
➢ Small die area to reduce cost.

12
 RF Transceiver Design
Lecture 38
Low Noise Amplifier Design - III

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
• LNA design requirement
➢ Broad-band input matching to minimize the return loss.
➢ Sufficient gain to suppress the noise of mixer.
➢ Low noise figure to enhance receiver sensitivity.
➢ Low power consumption to increase battery life.
➢ Small die area to reduce cost.

2
Classification of LNA Based on Topology
Inductor less Noise
CS LNA CG LNA
LNA Cancelling

• Resistive • Cascode CG • CS LNA with • Resistive

Terminated • CG with active feedback. feedback noise
• Resistive feedback • CG LNA with gm cancelling
• Feedback • CG with boosting or noise • CG/CS noise
• Inductive Source. feedforward(gm cancelling. cancelling LNA
degeneration. boosting LNA) • Inductorless LNA
• Cascode CS LNA with local
with inductive feedback.
degeneration. • Inductorless LNA
with voltage
combiner.
• Inverter based
inductorless
LNA.

3
CS LNA with Resistive Load

4
5
6
 RF Transceiver Design
Lecture 39
Low Noise Amplifier Design - IV

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
2
3
4
 1 𝑔𝑚 𝑍𝑠
𝑍𝑖𝑛 = 𝑍𝑠 + +
𝑆𝐶𝑔𝑠 𝑆𝐶𝑔𝑠
1. 𝑍𝑠 = 𝑅𝑠
1 𝑔𝑚 𝑅𝑠
𝑍𝑖𝑛 = 𝑅𝑠 + +
𝑆𝐶𝑔𝑠 𝑆𝐶𝑔𝑠
𝑔 𝑅𝑠
𝑚
𝑅𝑠 + 𝑆𝐶
𝑔𝑠
1
2. 𝑍𝑠 =
𝑆𝐶𝑆
1 1 𝑔𝑚
𝑍𝑖𝑛 = + + 2
𝑆𝐶𝑠 𝑆𝐶𝑔𝑠 𝑆 𝐶𝑔𝑠 𝐶𝑠

-Ve Resistance Unstability

5
3. 𝑍𝑆 = 𝑆𝐿𝑆 = 𝑗𝜔𝐿𝑆
1 𝑔𝑚 𝐿𝑠
𝑍𝑖𝑛 = 𝑗𝜔𝐶 + 𝑗𝜔𝐿𝑠 +
𝑔𝑠 𝐶𝑔𝑠

1
𝑓0 =
𝐶𝑔𝑠 𝐿𝑔 + 𝐿𝑆

𝜔𝑂 𝐿 𝜔𝑂 𝐿𝑔 +𝐿𝑆
𝑄𝑖𝑛 = =
𝑅 𝑅𝑆 + 𝜔 𝑇 𝐿𝑆
Effective 𝑔𝑚 at 𝑓0

𝑉𝐶 = 𝑉𝐿 = 𝑄 𝑉𝑖𝑛
𝑉𝑔𝑠 = 𝑄𝑖𝑛 𝑉𝑠

6
 𝜔𝑇 𝐿𝑆 𝑣𝑠
𝑉𝑖𝑛 = 𝑅 =
𝑆 +𝜔𝑇 𝐿𝑆 2

𝑣𝑠 = 2𝑉𝑖𝑛
𝑣𝑔𝑠 = 2𝑄𝑖𝑛 𝑉𝑖𝑛
𝑖𝑑 = 𝑔𝑚 𝑉𝑔𝑠 = 2𝑄𝑖𝑛 𝑔𝑚 𝑉𝑖𝑛
𝑖𝑑
𝐺𝑚 = = 2𝑄𝑖𝑛 𝑔𝑚
𝑉𝑖𝑛
𝐿𝐷
𝑅𝑃 = 𝑄
𝐶𝐷

𝐴𝑉 = 2𝑄𝑖𝑛 𝑔𝑚 𝑅𝑃
1
𝑓𝑜 =
2𝜋 𝐿𝐷 𝐶𝐷

7
 𝑖𝑜𝑢𝑡 = 𝑔𝑚 𝑣𝑔𝑠 + 𝐼𝑛

𝑣𝑖𝑛 = 𝑅𝑠 + 𝐿𝐺 𝑠 𝑉𝑔𝑠 𝐶𝑔𝑠 𝑠 + 𝑉𝑔𝑠 + 𝐿𝑠 𝑠 𝐼𝑜𝑢𝑡 + 𝑣𝑔𝑠 𝐶𝑔𝑠 𝑠

𝑗𝑅𝑠 𝐶𝑔𝑠1 𝜔0 𝑗𝑅𝑠 𝐶𝑔𝑠 𝜔0

𝑣𝑖𝑛 = 𝐼𝑜𝑢𝑡 𝑗𝐿𝑠 𝜔𝑜 + − 𝐼𝑛
𝑔𝑚 𝑔𝑚

𝐼𝑜𝑢𝑡 1
= 𝐺𝑚𝑜𝑢𝑡 =
𝑣𝑖𝑛 𝑅𝑠 𝐶𝑔𝑠
𝜔0 𝐿𝑠 +
𝑔𝑚

𝜔𝑇
𝐺𝑜𝑢𝑡 = . 1/𝑅𝑠
2𝜔0

8
 𝐼𝑛1
𝐼𝑛,𝑜𝑢𝑡 =
𝑀 2
2
𝐼𝑛,𝑜𝑢𝑡 = 𝑘𝑇𝛾𝑔𝑚

2
𝐼𝑛,𝑜𝑢𝑡
𝑁𝐹 = 1 + 2
4kTR s Gmout

2
𝜔𝑜
𝑁𝐹 = 1 + 𝑔𝑚 𝑅𝑠 𝛾
𝜔𝑇

9
 RF Transceiver Design
Lecture 40
Low Noise Amplifier Design - V

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
CS LNA with Inductive Source Degeneration

Cascode CS LNA with Inductive Degeneration

• Input matching same as CS LNA.
• High Gain
• Better reverse isolation.
• Same NF as CS LNA.
• An inductive load introduces a negative resistance due to the
feedback through 𝐶𝐺𝐷 → Cascode
• Suffers from non-linearity.
2
CS LNA with Inductive Source Degeneration
Design Procedure
• Identify the specification and Technology.
• Find width of MOSFET using
• power match equation,
• gm/ID plot
• Gm/ID vs ID/(W/L) method
2
𝐶𝐺𝑆
• Find value of Ls by using𝑅𝑆 = 𝐶 +𝐶 𝐿𝑆 𝜔 𝑇 .
𝐺𝑆 𝑝𝑎𝑑
1
• Find value of LG → 𝜔02 = 𝐿 +𝐿 𝐶 +𝐶 .
𝐺 𝑆 𝐺𝑆 𝑝𝑎𝑑
1
• Find value of 𝐿𝐷 → 𝜔02 = 𝐿 𝐶 +𝐶 +𝐶
𝐷 𝐺𝐷 𝐷𝐵 𝑜𝑢𝑡

3
CG with feedforward LNA
• Input impedance reduced by factor of (1+A).
• Gain increased by factor of (1+A).
• Noise reduced by (1+A).
1
𝑍𝑖𝑛 =
𝑔𝑚 (1 + 𝐴)
𝛾 4𝑅𝑠
𝐹 =1+ +
1 + 𝐴 𝑅1 CG with feedforward LNA
CG with feedback LNA
CG LNA with Feedback
• Decouple input impedance and noise factor.
• NF same as CG LNA .
2
𝛾 𝑅𝑆 1
𝑁𝐹 = 1 + + 1+
𝑔𝑚 𝑅𝑆 𝑅1 𝑔𝑚 𝑅𝑆

4
Resistive feedback Noise Cancelling LNA

• Aim to nullify noise due to transistor

• Signal should be of different sign and noise having
same.
• By increasing RF -> gain became high.
• Noise factor is minimum.

5
Balun-LNA

Why Balun?

6
Passive vs. Active Balun
• It used to implement single to differential.
• lossy and narrowband.
• Leading to higher cost.

Significance of Active Balun

• Low loss and small area.

• High power gain
• Low noise over wideband .

7
CG-CS Balun LNA.
• All noise and distortion generated by CG transistor can be cancelled.
• Overall linearity of complete LNA determined by CS LNA.
• Final noise determined by R_Cg and CS stage.
𝐺𝑎𝑖𝑛𝐶𝐺 = 𝐺𝑎𝑖𝑛𝐶𝑆

• Overall linearity of complete LNA determined by CS LNA.

• Final noise determined by R_Cg and CS stage.
Drawback:
• Noise generated by the CS stage is significant because of
• its low transconductance.
• Trans conductance of CS amplifier need to be scaled by n.
8
Practical CG_CS topology.
• Gm_CG=N*Gm_CS
• R_CS=R_CG/N
• Noise contribution of CS decrease with a factor 1/n for increasing n.
• Voltage gain remain constant.

Drawback:
• Gain and phase imbalance at differential output
• Symmetrical load
• Current bleeding technique.
• Above technique imbalance is sensitive to PVT.

9
CG_CS Balun LNA employing Current Bleeding
• Id_CS = I
• IBLD = (N-1)I
• Symmetric load because current flowing through R_CG is equal
to R_CS.

Drawback:

• Balanced output at cost of worse noise figure.

• Noise figure is more than practical CG_CS topology.

10
Modified Current Bleeding Circuit
Noise contribution of MB greatly reduce.
Advantage:
Achieve performance improvement in both NF
and output balance.

11
Inductor less LNA?

12
• Traditional LNAs with on-chip inductor occupy large area.
• Counters benefit brought by scaled digital CMOS.
• Lack of inductor modelling :
• Complicates circuit design.
• Off chip inductor have high Q than on chip inductor :

increase cost.
reduce yield.

13
CS LNA with Active Feedback
Inductors are substituted with resistor required extra voltage drop.
Non linear transistor Mfb degrades linearity of LNA.

CG LNA with gm boosting or noise

cancellation
• Used to boost gm of CG transistor.
• Voltage gain still restricted by input
matching condition.

14
Voltage Combiner:
• Used for combining differential output of single to differential converter.
• provide excellent IIP2 performance by differential mode operation.

+ =
Disadvantage of CS with diode connected load:
Shows poor third order harmonics distortion
performance
Disadvantage of source follower:
Second order and third harmonics distortion is reduced
by a factor of large loop gain.

15
Inductorless LNA with Voltage Combiner.
• Achieved more power efficient NF
and high voltage gain.
• Provides linear feedback operation ,
HD2fn and HD3fn equal to 0.

• Off chip low noise and bulky inductor can be

used to reduce noise contribution.
• advantage of inductorless is discounted.

16
Inverter based Inductorless LNA
• Shunt feedback that achieve self bias and input impedance matching simultaneously.

𝑅𝑜𝑢𝑡 + 𝑅𝐹
𝑅𝑖𝑛 =
1 + 𝐺𝑚 𝑅𝑜𝑢𝑡

𝑤ℎ𝑒𝑟𝑒 𝑅𝑜𝑢𝑡 = 𝑟𝑜1||ro2 and 𝐺𝑚 = 𝑔𝑚1 + 𝑔𝑚2

𝑉𝑜𝑢𝑡 𝑅𝑜𝑢𝑡(1−𝐺𝑚 𝑅𝐹 )
Voltage gain= =
𝑉𝑖𝑛 2𝑅 (1+𝐺 𝑅 )
𝑠 𝑚 𝑜𝑢𝑡

𝑣 𝑅𝑠
Noise Factor=1+ +
𝐺𝑚 𝑅𝑠 𝑅𝐹

17
Classification of LNA Based on Application

1. GPS

3.Bluetooth low Energy (BLE)

5.IOT

6.Satellite

7. mm- Wave

18
 RF Transceiver Design
Lecture 41
Low Noise Amplifier Design - VI

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
Non-Linearity Calculation

2
Non-Linearity Calculation
For a non-linear system:

𝑦 𝑡 = 𝛼0 + 𝛼1 𝑥1 𝑡 + 𝛼2 𝑥22 𝑡 + 𝛼3 𝑥32 𝑡

𝜕𝑦
𝛼1 = |
𝜕𝑥 𝑥=0
1 𝜕2 𝑦
𝛼2 = |
2 𝜕2 𝑥 𝑥=0

1 𝜕3 𝑦
𝛼3 = |
6 𝜕3 𝑥 𝑥=0

X = 0 corresponds to the bias point of the circuit with no input

3
Degenerated CS Stage
𝐼𝐷 = 𝐾(𝑉𝐺𝑆 − 𝑉𝑇𝐻 )2

Where 𝑉𝐺𝑆 = 𝑉𝑖𝑛 − 𝑅𝑆 𝐼𝐷

𝜕𝐼𝐷 𝜕𝐼𝐷
= 2𝐾 𝑉𝑖𝑛 − 𝑅𝑆 𝐼𝐷 − 𝑉𝑇𝐻 1 − 𝑅𝑆
𝜕𝑉𝑖𝑛 𝜕𝑉𝑖𝑛
𝑔𝑚 = 2𝐾 𝑉𝑖𝑛𝑂 − 𝑅𝑆 𝐼𝐷𝑂 − 𝑉𝑇𝐻

Where 𝑉𝑖𝑛𝑂 = 𝑉𝑏 𝑎𝑛𝑑 𝐼𝐷𝑂 𝑑𝑒𝑛𝑜𝑡𝑒𝑠 𝑡ℎ𝑒 𝑏𝑖𝑎𝑠 𝑣𝑎𝑙𝑢𝑒.

𝜕𝐼𝐷 𝑔
| = 𝛼1 = 1+𝑔𝑚 𝑅
𝜕𝑉𝑖𝑛 𝑉𝑖𝑛𝑂 𝑚 𝑆
2
𝜕 2 𝐼𝐷 𝜕𝐼𝐷 𝜕 2 𝐼𝐷
= 2𝐾 1 − 𝑅𝑆 + 2𝐾 𝑉𝑖𝑛 − 𝑅𝑆 𝐼𝐷 − 𝑉𝑇𝐻 −𝑅𝑆 2
𝜕 2 𝑉𝑖𝑛 𝜕𝑉𝑖𝑛 𝜕 𝑉𝑖𝑛

4
 𝜕2 𝐼𝐷 2𝐾
| = 2𝛼2 =
𝜕2 𝑉𝑖𝑛 𝑉𝑖𝑛𝑂 1+𝑔𝑚 𝑅𝑆 3

𝜕3 𝐼𝐷 −12𝐾2 𝑅𝑆
| = 6𝛼3 = 𝛼3 = 0 , if 𝑅𝑆 = 0
𝜕3 𝑉𝑖𝑛 𝑉𝑖𝑛𝑂 1+𝑔𝑚 𝑅𝑆 5

𝛼1 𝑎𝑛𝑑 𝛼3 ℎ𝑎𝑣𝑒 𝑜𝑝𝑝𝑜𝑠𝑖𝑡𝑒 𝑠𝑖𝑔𝑛𝑠 , 𝑖𝑚𝑝𝑙𝑦𝑖𝑛𝑔 𝑎 𝑐𝑜𝑚𝑝𝑟𝑒𝑠𝑠𝑖𝑣𝑒 𝑐ℎ𝑎𝑟𝑎𝑐𝑡𝑒𝑟𝑖𝑠𝑡𝑖𝑐𝑠.

4 𝛼1
𝐴𝐼𝐼𝑃3 =
3 𝛼3

2
2𝑔𝑚 1 + 𝑔𝑚 𝑅𝑆
3𝑅𝑆 𝐾

5
Common – Gate Stage
𝑉𝐺𝑆 = 𝑉𝑏 − 𝑉𝑖𝑛 − 𝑅𝑆 𝐼𝐷
𝜕𝐼𝐷 𝜕𝐼𝐷
= 2𝐾 𝑉𝑏 − 𝑉𝑖𝑛 − 𝑅𝑆 𝐼𝐷 − 𝑉𝑇𝐻 1 − 𝑅𝑆
𝜕𝑉𝑖𝑛 𝜕𝑉𝑖𝑛
𝜕𝐼𝐷 𝑔𝑚 𝑔𝑚 𝑓𝑜𝑟 𝑉𝑖𝑛 =0
|𝑉𝑖𝑛0 = −
𝜕𝑉𝑖𝑛 1 + 𝑔𝑚 𝑅𝑆

𝜕2 𝐼𝐷 2𝐾
| =
𝜕2 𝑉𝑖𝑛 𝑉𝑖𝑛0 1+𝑔𝑚 𝑅𝑆 3

𝜕3 𝐼𝐷 12𝐾2 𝑅𝑆
| =
𝜕3 𝑉𝑖𝑛 𝑉𝑖𝑛𝑂 1+𝑔𝑚 𝑅𝑆 5

2 2 2
𝐴𝐼𝐼𝑃3 = 𝑔 =4 𝑉𝐺𝑆0 − 𝑉𝑇𝐻
𝐾 3 𝑚 3

6
Classification of LNA Based on Application

1. GPS

3.Bluetooth low Energy (BLE)

5.IOT

6.Satellite

7. mm- Wave

7
GPS Application.
• Used in cellular hand set.
• Operates in L-band frequency band.
• use of narrowband technique to reduce
power consumption.

Implementation of LNA for GPS using

Folded Cascode:
• Conventional cascode is not suitable for low voltage
application due to its stacking configuration.

8
Bluetooth Low Energy
• Freq: 2.45GHz (S Band)
• Low power, short range and low cost.
• Used in IOT sensor device
• Implementation :
• Technique1:
• IMD technique is used to improve non-linearity.
1
𝑁𝐹 ∝ = 𝜔𝑜 𝑔𝑚 𝐿𝑠
𝑄2

9
 Technique2
Quadrature Low Noise Amplifier
• Gaenerate quadrature signal without any
additional power consumption.
• No need of additional VCO.
Quadrature Transconductor based on CS amplifier with capacitive degeneration
𝑗𝜔𝑜 𝐶𝑜 𝑔𝑚𝑜
𝐼𝑖𝑛 =
1 + 𝑗𝜔𝐶𝑜 𝑔𝑚𝑜
𝜔𝐶𝑜 𝑔𝑚𝑜
𝐼𝑄 = 𝑉
1 + 𝑗𝜔𝑜 𝑔𝑚𝑜 𝑖𝑛
𝐼1 𝐼1
= 1 < = 90
𝐼𝑄 𝐼𝑄
10
IOT Application:
➢Long distance
➢Low power
➢Large capacity
• used for smart IOT in smart cities and
devices such as smoke sensors, smart street
lights form a wireless IOT.

Sub – GHz low noise amplifier for IOT application:

Low power and low voltage meets the IOT application
requirement of smart cities.

11
Ultra Low Voltage , Ultra Low Power, Wideband LNA For
IOT Application:
Trade-off in voltage gain, NF ,and input matching.
Voltage drop for cascode transistor make it impractical at
low supply voltage.

Advantage of inductive Peaking:

Inductive peaking in feedback loop is exploited to cancel Cgs and

Cgd ,used to extend input matching and bandwidth.

12
mm-Wave application:
Freq > 30GHz.
Application:
For mm wave band :
Increase chip size, NF and power consumption.

Circuit topology:
Device size should be smaller for lower noise
figure and power consumption.
Circuit will be unstable at high frequency.

13
14
 RF Transceiver Design
Lecture 42
Mixer Design - I

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
Mixer Fundamental
• RF signal spectrum - A typical RF spectrum centers around the carrier frequency (fC).
• Asymmetry in Practical RF Signals- Practical RF signals often deviate from symmetry
with respect to the carrier frequency.
• Frequency Shifting: When signal is multiplied by 𝑒 −𝑗2𝜋𝑓0𝑡 , it undergoes a frequency shift
to the left.
• Intermediate Frequency (IF): A wideband lowpass filter is typically applied to process
the down-converted spectrum at fC - f0 (the intermediate frequency or IF).

𝑒 −𝑗2𝜋𝑓0𝑡
-fc 0 fc f
1

-f0 0 f
-fc–f0 0 fc–f0 f

2
Plot of I+jQ
• 𝐼 + 𝑗𝑄 = 𝐴𝑐𝑜𝑠𝜔0 𝑡 + 𝑗𝐴𝑠𝑖𝑛𝜔0 𝑡 = 𝐴𝑒 −𝑗𝜔0𝑡

Im
Im
+j A/2

-ω0 Re
-A/2 -ω0 Re
-A/2
+ω0 A
+ω0
-ω
-ω
-j A/2

3
Challenges in Realizing Frequency Shifting for RF Signals: A Practical
Perspective:
• Introduction to Frequency Shifting Challenge: The main challenge is the practical
realization of the non-real signal 𝑒 −𝑗2𝜋𝑓0𝑡
• Euler Identity Transformation: To address the non-real nature of 𝑒 −𝑗2𝜋𝑓0𝑡 , the Euler identity
is introduced, breaking down the shifting signal into real components: cos(2πf0t) and
sin(2πf0t).
• Multiplication with Sine and Cosine Functions: Fig. (next slide) illustrates the RF signal
multiplied in the time domain by individual sine and cosine functions.
• Impulse Characteristics: The resulting signals consist of two
impulses at ±f0, with half the magnitude (signal loss and potential
performance degradation).

4
 • Complications Near DC: Around DC, a
folded replica of the shifted RF spectrum
forms a mirror image. If fC - f0 is small
cos(2𝜋f0t) compared to the signal bandwidth, the two
-fc 0 fc f
1/2 1/2 replicas overlap and become
½ ½ ½ ½
-f0 0 f0
indistinguishable.
-fc–f0 –fc+f0 0 fc–f0 fc+f0
• Solution: In-Phase and Quadrature (I/Q)
Approach: The generated I and Q signals
are passed through a Hilbert transform
sin(2𝜋f0t)
setup to extract either the high or low side
-fc 0 fc f of the shifted signal spectrum.
+j/2
+j/2 +j/2 +j/2 +j/2 f0
-f0 0
-fc–f0 –fc+f0 0 fc–f0 fc+f0 -j/2

5
Hilbert Transform for Symmetric Frequency Shifting
• Introduction to Hilbert Transform:

• This transform multiplies the positive frequency components of the spectrum by -j and
the negative components by +j.

• Addition and Subtraction Outcomes:

➢ Addition results -> High-frequency side of the shifted spectrum with respect to the
carrier frequency (fC),
➢ Subtraction Results -> the low-frequency side.

• Image-Reject Receiver:

6
Mixer Basic Operation
• Frequency Translation
– RF -> IF or BB
– BB & IF -> RF
• Creative use of nonlinearity or time-variance
• Used together with appropriate filtering

7
An ideal mixer
𝑥(𝑡)
𝑹𝑭 𝑰𝑭
𝑥(𝑡) = 𝐴 sin 𝜔1𝑡
y(𝑡) = 𝐵 cos 𝜔2𝑡
LO
𝐴𝐵 𝐴𝐵
y(𝑡)
𝑥(𝑡)y 𝑡 = cos(𝜔1- 𝜔2)t + cos(𝜔1+ 𝜔2)t
2 2

𝜔1 𝑎𝑛𝑑 𝜔2
supressed 𝑁𝑜 ℎ𝑎𝑟𝑚𝑜𝑛𝑖𝑐𝑠

𝜔1- 𝜔2 𝜔1+ 𝜔2 𝜔

8
Understanding Mixer Behaviour in RF Circuits
• Mixer Behaviour in Square-Law Devices:

• LO Amplitude Dependence: Mixer gain can depend on the amplitude of the LO signal, which is
undesirable in some cases. Proper design of the LO port can eliminate this amplitude dependence.

𝑅𝐿
𝑥(𝑡) 𝑥(𝑡)y(𝑡) 𝑉0
𝑹𝑭 𝑰𝑭
𝑉2 𝑡 =
𝐴2 cos(𝜔2t)
𝑉𝐷𝐶
LO 𝑉1(𝑡) =
y(𝑡) 𝐴1 cos(𝜔1t)

9
Switching Operation of the Mixer

4 1 1
𝑉𝐿𝑂(𝑡) = [cos(𝜔𝐿𝑂t) - cos(3𝜔𝐿𝑂t)+ cos(5𝜔𝐿𝑂t)]
𝜋 3 5

𝑉𝑅𝐹 𝑡 = 𝐴𝑅𝐹 cos(𝜔𝑅𝐹t)

𝑉𝐼𝐹 (𝑡) = 𝑉𝑅𝐹 (𝑡) 𝑉𝐿𝑂(𝑡)
2 1
𝑉𝐼𝐹 (𝑡) = 𝐴𝑅𝐹 (cos(𝜔𝐿𝑂- 𝜔𝑅𝐹 )t + cos 3(𝜔𝐿𝑂- 𝜔𝑅𝐹 )t)
𝜋 3

10
Types of Mixers
Current to Voltage
𝑰𝑭 𝒐𝒖𝒕𝒑𝒖𝒕
▪ Square Law Device Converter

▪ Based on Switching
𝑳𝑶 𝑰𝒏𝒑𝒖𝒕 LO Current Switch

RF Voltage to
𝑹𝑭 𝑰𝒏𝒑𝒖𝒕 Current Converter
IF
Diplexer
Filter

11
 Spectrum at X
NF of mixer Signal Image
RS Band
X Y
▪ SSB NF Band

Thermal
Vin + Noise
-
𝜔𝐿𝑂 𝜔
𝜔𝐿𝑂

▪ DSB NF Spectrum at Y

Spectrum at X Signal
Band
𝜔𝐼𝐹 𝜔
RS Thermal
X Y
Noise

+ 𝜔𝐿𝑂 𝜔
Vin
-

𝜔𝐿𝑂 Spectrum at Y

0 𝜔
12
Port to Port Isolation
1. LO-to-IF: Some unwanted LO signal appears at the IF 𝑹𝑭 𝑰𝑭
port which can desensitize the IF output. It can be removed
by a baseband filter.
LO
2. LO-to-RF: Unwanted radiation from LNA. It Modulate
Output of RF.

3. RF-to-IF: It can cause even-order intermodulation in the

incoming stage of the receiver.

4. RF-to-LO: it can cause injection pulling, and change the

oscillation frequency, and introduce phase noise.

13
 RF Transceiver Design
Lecture 43
Mixer Design - II

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
Conversion Gain
▪ Conversion gain or loss is the ratio of the desired IF output (voltage or
power) to the RF input signal value ( voltage or power)
▪ Gain Conversion voltage = IF(r.m.s) / RF(r.m.s)
▪ Gain Conversion power = IF output power/ RF input power
▪ IF impedance at load and input matched then Voltage gain = Power gain

2
Input Intermodulation product(IIP3)
Pout (dBm)
Magnitude
OIP3 𝑹𝑭𝟏 − 𝑳𝑶 𝑹𝑭𝟐 − 𝑳𝑶
IP3 𝑳𝑶

𝟐𝑹𝑭𝟏 − 𝑹𝑭𝟐 − 𝑳𝑶 𝟐𝑹𝑭𝟐 − 𝑹𝑭𝟏 − 𝑳𝑶 𝑹𝑭𝟏 𝑹𝑭𝟐

Freq.

IIP3 Pin (dBm)

𝚫
𝑰𝑰𝑷𝟑 𝒅𝑩𝒎 = 𝑷𝒊𝒏(𝒅𝑩𝒎)) + (𝒅𝑩)
𝟐

𝚫 = 𝐏 𝐟𝐢𝐫𝐬𝐭 𝐨𝐫𝐝𝐞𝐫 − 𝐏 𝟑𝐫𝐝 𝐨𝐫𝐝𝐞𝐫

𝑶𝑰𝑷𝟑 𝒅𝑩𝒎 = 𝑰𝑰𝑷𝟑 𝒅𝑩𝒎 + 𝒈𝒂𝒊𝒏(𝒅𝑩)

3
Conversion Gain
▪ Conversion gain -> lowers noise impact of following stages
▪ Noise Figure -> impacts receiver sensitivity
▪ Port isolation -> To minimize feed through between the
RF, IF, and LO ports
▪ Linearity (IIP3) -> impacts receiver blocking performance
▪ Power match -> want max voltage gain rather than
power match for integrated designs
▪ Power -> want low power dissipation
▪ Sensitivity to need to make it manufactures in
process/temp -> high volume
variations

4
Evolution of Mixers: From Tube-Based Diode Rings to FET-Based
Linear Mixers:
• Diode-Ring Mixer Structure: This employs Schottky diodes as fast switches. Input
and output signals connect to transformers linked to the ring, while a differential LO
signal is applied to the center tap of the transformers.
• Switching Operation: During one half-cycle of the LO signal, specific diodes are on,
while others are off. This results in the output being equal to the input. During the
next half-cycle, the polarity of the input and output reverses, leading to output
multiplication by a function P(t).
4 1 1
𝑃(𝑡) = π (𝑠𝑖𝑛𝜔𝐿𝑂𝑡 − 3 𝑠𝑖𝑛3𝜔𝐿𝑂𝑡 + 5 𝑠𝑖𝑛5𝜔𝐿𝑂𝑡-…..)

5
• LO Amplitude Requirement: To ensure proper diode switching, the LO
signal's minimum required amplitude equals the diode's VON (turn-on
voltage).
2
• Mixer output is: π 𝐴 𝑐𝑜𝑠 (𝜔𝑅𝐹 - 𝜔𝐿𝑂)t
• LO Signal Characteristics: The LO signal need not be a square wave; it can be
a smoothly transitioning signal, provided it switches the diodes effectively.
• Transition to FET-Based Mixers: In 1968, researchers at MIT proposed using
FETs as switches, marking a transition from diode-based mixers. FETs provide
better switching capabilities and result in more linear mixers.

6
Single-Ended Diode Mixer
𝑇ℎ𝑒 𝑠𝑚𝑎𝑙𝑙 𝑠𝑖𝑔𝑛𝑎𝑙 𝑑𝑖𝑜𝑑𝑒 𝑐𝑢𝑟𝑟𝑒𝑛𝑡 𝑖𝑠 𝑔𝑖𝑣𝑒𝑛 𝑏𝑦:
𝑣𝑅𝐹 𝑡 = 𝑉𝑅𝐹 cos(𝜔𝑅𝐹 t)
𝑣𝐿𝑂 𝑡 = 𝑉𝐿𝑂 cos(𝜔𝐿𝑂t) 𝐺𝑑1 2
𝑖 𝑡 = 𝑖0 + 𝐺𝑑 𝑣𝑅𝐹 𝑡 + 𝑣𝐿𝑂 𝑡 + 𝑣 𝑡 + 𝑣𝐿𝑂 𝑡
2 𝑅𝐹

+𝑫𝑪
bias
𝑫𝑪 LPF
Diplexer 𝑫𝑪
𝒃𝒍𝒐𝒄𝒌 𝒃𝒍𝒐𝒄𝒌
𝑹𝑭 𝑰𝒏𝒑𝒖𝒕
𝑰𝑭 𝒐𝒖𝒕𝒑𝒖𝒕
𝑫𝒊𝒐𝒅𝒆
𝑳𝑶 𝑰𝒏𝒑𝒖𝒕

i0
+
𝑉𝑅𝐹 𝑡
+
-
𝑣
+ -
𝑉𝐿𝑂 𝑡
𝐺𝑑1 -
𝑖𝐼𝐹 𝑡 = 𝑉 𝑡 𝑣𝐿𝑂 𝑡 cos 𝜔𝐼𝐹t
2 𝑅𝐹

7
Single-Ended FET Mixer
RF choke +DC bias

RF input IF
RF/LO output
diplexer
LO LPF
LO input And
matching bypass
RF
choke

-DC bias

8
 2
𝑉𝐷𝐼𝐹 𝑅𝐿
2
𝑃𝐼𝐹𝑎𝑣𝑎𝑖𝑙 𝑍𝐿 2 4𝑅𝑔 𝑅𝐿 𝑉𝐷𝐼𝐹
𝐺𝑐 = = 2 =
𝑃𝑅𝐹𝑎𝑣𝑎𝑖𝑙 𝑉𝑅𝐹 𝑍𝐿 2 𝑉𝑅𝐹
4𝑅𝑔
𝑔𝑚 𝑡 𝑣𝑐𝑅𝐹 𝑡 = 𝑔0 𝑉𝑐𝑅𝐹 𝑐𝑜𝑠𝜔𝑅𝐹 𝑡 + 2𝑔1 𝑉𝑐𝑅𝐹 𝑐𝑜𝑠𝜔𝑅𝐹 𝑡 𝑐𝑜𝑠𝜔𝐿𝑂 𝑡 + ⋯ .

𝑔𝑚 𝑡 𝑣𝑐𝑅𝐹 𝑡 ቚ = 𝑔1 𝑉𝑐𝑅𝐹 𝑐𝑜𝑠𝜔𝐼𝐹 𝑡

𝜔𝑅𝐹

R d ZL 𝑔1 VRF R d ZL
𝑉𝐷𝐼𝐹 𝑡 = −𝑔1 𝑉𝑐𝑅𝐹 =−
R d + ZL 1 + j𝜔𝑅𝐹 𝐶𝑔𝑠 𝑅𝑖 + 𝑍𝑔 R d + ZL
2
2𝑔1 𝑅𝑑 𝑅𝑔 𝑅𝐿
𝐺𝑐 ቚ =
𝑛𝑜𝑡
𝑚𝑎𝑡𝑐ℎ𝑒𝑑
𝜔𝑅𝐹 𝐶𝑔𝑠 2 1
2
(𝑅𝑑 +𝑅𝐿 2 + 𝑋𝐿2 ]
𝑅𝑖 + 𝑅𝑔 + 𝑋𝑔 −
𝜔𝑅𝐹 Cgs

𝑔12 𝑅𝑑
𝐺𝑐 = 2 2
4𝜔𝑅𝐹 𝐶𝑔𝑠 𝑅𝑖

9
Example: A single-ended FET mixer is to be designed for a wireless local area network receiver
operating at 2.4 GHz. The parameters of the FET are
Rd = 300 ohms, Ri = 10 ohm, Cgs = 0.3 pF, and g1 =10 mS. Calculate the maximum possible
conversion gain.
Solution
This is a straightforward application of the formula for conversion gain given in prev. slide

𝑔12 𝑅𝑑
𝐺𝑐 = 4𝜔𝑅𝐹2 2
𝐶𝑔𝑠 𝑅𝑖
= 36.6 = 15.6 dB

Note: that this value does not include losses due to the necessary impedance match-
ing networks.

10
 RF Transceiver Design
Lecture 44
Mixer Design - III

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
Balanced Mixer
• RF input matching RF 𝟎𝒐
1
• RF-LO isolation
input 𝟏 𝟐 𝑉𝛤
𝑉𝛤𝑅𝐹 𝑖1
IF
𝑉𝛤𝐿𝑂 𝑖2 Output
𝟒 𝟑 LPF
LO o
𝑉𝛤2
3 dB 90
input
Hybrid coupler
−𝟗𝟎𝒐

RF −𝟗𝟎𝒐
1
input 𝟏 𝟐 𝑉𝛤
𝑉𝛤𝑅𝐹 𝑖1
IF
𝑉𝛤𝐿𝑂 𝑖2 Output
𝟒 𝟑 LPF
LO 𝑉𝛤2
3 dB 180o
input
Hybrid coupler +𝟗𝟎𝒐

2
90 degree hybrid coupler RF 𝟎𝒐
1
input 𝟏 𝟐 𝑉𝛤
𝑉𝑅𝐹 𝑡 = 𝑉𝑅𝐹 cos(𝜔𝑅𝐹t)
𝑉𝛤𝑅𝐹 +𝑣1 - 𝑖1
𝑉𝐿𝑂 𝑡 = 𝑉𝐿𝑂 cos(𝜔𝐿𝑂t) IF
𝑉𝛤𝐿𝑂 +𝑣2 - 𝑖2
Output
𝟒 𝟑 2 LPF
LO 𝑉𝛤
3 dB 90o
input
Hybrid coupler
−𝟗𝟎𝒐

1
𝑣1 𝑡 = [𝑉 𝑐𝑜𝑠 𝜔𝑅𝐹 𝑡 − 90𝑜 + 𝑉𝐿𝑂 cos 𝜔𝐿𝑂 𝑡 − 180𝑜 ]
2 𝑅𝐹
1
= (𝑉𝑅𝐹 𝑠𝑖𝑛 𝜔𝑅𝐹 𝑡 + 𝑉𝐿𝑂 cos 𝜔𝐿𝑂 𝑡 )
2
1
𝑣2 𝑡 = [𝑉 𝑐𝑜𝑠 𝜔𝑅𝐹 𝑡 − 180𝑜 + 𝑉𝐿𝑂 cos 𝜔𝐿𝑂 𝑡 − 90𝑜 ]
2 𝑅𝐹
1
= (−𝑉𝑅𝐹 𝑐𝑜𝑠 𝜔𝑅𝐹 𝑡 + 𝑉𝐿𝑂 sin 𝜔𝐿𝑂 𝑡 )
2

3
 𝐾 2
𝑖1 𝑡 = 𝐾𝑣12 = [𝑉𝑅𝐹
2
sin2 𝜔𝑅𝐹 𝑡 −2𝑉𝑅𝐹 𝑉𝐿𝑂 sin 𝜔𝑅𝐹 𝑡 cos 𝜔𝐿𝑂 𝑡 + 𝑉𝐿𝑂 cos2 𝜔𝐿𝑂 𝑡 ]
2
−𝐾 2
𝑖2 𝑡 = −𝐾𝑣22 = 2
[𝑉𝑅𝐹 cos2 𝜔𝑅𝐹 𝑡 −2𝑉𝑅𝐹 𝑉𝐿𝑂 cos 𝜔𝑅𝐹 𝑡 sin 𝜔𝐿𝑂 𝑡 + 𝑉𝐿𝑂 sin2 𝜔𝐿𝑂 𝑡 ]
2
−𝐾 2 2
𝑖1 𝑡 + 𝑖2 𝑡 = [𝑉𝑅𝐹 𝑐𝑜𝑠 2𝜔𝑅𝐹 𝑡 +2𝑉𝑅𝐹 𝑉𝐿𝑂 sin 𝜔𝐼𝐹 𝑡 − 𝑉𝐿𝑂 𝑐𝑜𝑠 2𝜔𝐿𝑂 𝑡 ]
2

𝑖𝐼𝐹 (𝑡) = −𝐾𝑉𝑅𝐹 𝑉𝐿𝑂 sin 𝜔𝐼𝐹 𝑡

𝑗𝛤𝑉𝑅𝐹
𝑉𝛤1 = 𝛤𝑉1 = −
2
𝛤𝑉𝑅𝐹
𝑉𝛤2 = 𝛤𝑉2 = −
2
𝑅𝐹
𝑗𝑉𝛤1 𝑉𝛤2 1 1
𝑉𝛤 = − − = − 𝛤𝑉𝑅𝐹 + 𝛤𝑉𝑅𝐹 = 0
2 2 2 2

𝑉𝛤2 𝑉𝛤1 1 1
𝑉𝛤𝐿𝑂 = − −𝑗 = 𝑗𝛤𝑉𝑅𝐹 + 𝑗𝛤𝑉𝑅𝐹 = 𝑗𝛤𝑉𝑅𝐹
2 2 2 2

4
Image Reject Mixer
LPF 𝟗𝟎𝒐
A C
RF sin(𝜔𝐿𝑂t) IF
input cos(𝜔𝐿𝑂 t) Output
B
LPF

LPF 𝐴
𝑣𝐼𝐹
𝐴
𝑣𝑅𝐹 𝑣1
𝟏 𝟐 𝟏 𝟐 LSB
RF
input LO
input

𝟒 𝟑 𝟒 𝟑 USB
90o 𝐵
𝑣𝑅𝐹
𝐵
𝑣𝐼𝐹 90o 𝑣2
Z0 RF Hybrid RF Hybrid
LPF

5
𝑣𝑅𝐹 𝑡 = 𝑉𝑈 𝑐𝑜𝑠 𝜔𝐿𝑂 + 𝜔𝐼𝐹 𝑡 + 𝑉𝐿 cos 𝜔𝐿𝑂 − 𝜔𝐼𝐹 𝑡
1
𝑣𝐴 𝑡 = [𝑉 𝑐𝑜𝑠 𝜔𝐿𝑂 𝑡 − 𝜔𝑅𝐹 𝑡 − 90𝑜 + 𝑉𝐿 cos 𝜔𝐿𝑂 𝑡 − 𝜔𝐼𝐹 𝑡 − 90𝑜 ]
2 𝑈
1
= [𝑉 𝑠𝑖𝑛 𝜔𝐿𝑂 + 𝜔𝐼𝐹 𝑡 + 𝑉𝐿 sin 𝜔𝐿𝑂 − 𝜔𝐼𝐹 𝑡]
2 𝑈

1
𝑣𝐴 𝑡 = [𝑉 𝑐𝑜𝑠 𝜔𝐿𝑂 𝑡 + 𝜔𝐼𝐹 𝑡 − 180𝑜 + 𝑉𝐿 cos 𝜔𝐿𝑂 𝑡 − 𝜔𝐼𝐹 𝑡 − 180𝑜 ]
2 𝑈
−1
= [𝑉 𝑐𝑜𝑠 𝜔𝐿𝑂 + 𝜔𝐼𝐹 𝑡 + 𝑉𝐿 cos 𝜔𝐿𝑂 − 𝜔𝐼𝐹 𝑡]
2 𝑈

𝐴
𝑗𝐾𝑉𝐿𝑂
𝑉𝐼𝐹 =− 𝑉𝑈 − 𝑉𝐿 𝑠𝑖𝑛𝜔𝐼𝐹 𝑡
2 2

𝐵
𝐾𝑉𝐿𝑂
𝑉𝐼𝐹 =− 𝑉𝑈 + 𝑉𝐿 𝜔𝐼𝐹 𝑡
2 2

6
 𝐴
𝑗𝐾𝑉𝐿𝑂
𝑉𝐼𝐹 =− (𝑉𝑈 − 𝑉𝐿 )
2 2

𝐵
𝐾𝑉𝐿𝑂
𝑉𝐼𝐹 =− (𝑉𝑈 + 𝑉𝐿 )
2 2

7
 RF Transceiver Design
Lecture 45
Mixer Design - IV

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
Gilbert Multiplier: A Precise Four-Quadrant Analog Multiplier and Its Application in
1 + 𝑦 𝐼𝐸
Mixers
2
• Barrie Gilbert's Landmark Paper: In 1968, Barrie
Gilbert published a ground-breaking paper 1 + 𝑥 𝐼𝐸 𝑄3 𝐼0 𝑄4 1 − 𝑥 𝐼𝐸
2 2
introducing a precise four-quadrant analog
multiplier.
• The analysis assumes that the devices involved are 𝑄1 𝑄2
𝑄5 𝑄6
perfectly matched, possess ideal exponential 𝑉𝑥 + 𝑉𝑥 −
characteristics, and have a high β (common-emitter 1 − 𝑦 𝐼𝐸
current gain). 2
• Applying the KVL equation: 𝑉𝐵𝐸1 − 𝑉𝐵𝐸2 = 𝑉𝐵𝐸3 − 𝑉𝐵𝐸4 = 𝑉𝐵𝐸5 − 𝑉𝐵𝐸6
• The voltage VBE for each transistor is expressed as:
𝐾𝑇 𝐼𝐸
• The current ratios for the transistors: 𝑉𝐵𝐸 = ln( )
𝑞 𝐼𝑠
𝐼𝐸1 𝐼𝐸3 𝐼𝐸5 1 + 𝑥
= = =
𝐼𝐸2 𝐼𝐸4 𝐼𝐸6 1 − 𝑥

2
• KCL is applied to the circuit,
1 − 𝑦 𝐼𝐸 1 + 𝑦 𝐼𝐸
𝐼𝐸1 + 𝐼𝐸2 = 𝐼𝐸1 + 𝐼𝐸2 =
2 2
• The final expressions of the transistor currents:
1±𝑥 1−𝑦 𝐼𝐸 1±𝑥 1+𝑦 𝐼𝐸
𝐼𝐸1,2 = , 𝐼𝐸3,4 =
4 4
• The output current Io: 𝐼𝐸 = (𝐼𝐸2 +𝐼𝐸3 )- (𝐼𝐸1 +𝐼𝐸4 )
• Normalized Output Current: Normalizing the output current Io by dividing it by IE, results
in the equation: Z=x*y
• If x and y are the RF and the LO signals, the output z after
lowpass filtering will be the IF signal.

3
Active Mixer Operation and Characteristics
• Introduction: Active mixers are based on the concept of current switching.
Rearrangement of the Gilbert multiplier is shown in fig.
• Square-Wave Signal Application: A square-wave-like signal is applied to the core
transistors (nodes VX+ and VX-) to steer the emitter current abruptly between the
𝑉
devices at each zero crossing. 𝐼0 = 𝐼𝐸𝐸 tanh(− 2𝑉𝑋 )
𝑇

𝐼0 ≫ 2𝑉𝑇 𝑉𝑥
𝐼0 𝐼𝐸𝐸

𝑉𝑋
2𝑉𝑇

𝑄1 𝑄2 𝑄3 𝑄4 −𝐼𝐸𝐸
𝑉𝑥 + 𝑉𝑥 −

𝑉𝑋 ≫ 2𝑉
1 − 𝑦 𝐼𝐸 1 + 𝑦 𝐼𝐸
2 2

4
• Emitter-Coupled Pair I-V Characteristics: Fig. illustrates an emitter-coupled pair with I-V
characteristics. When |VX| > 2VT, most of the current is rapidly switched between the
devices due to the sharp tanh transition, resulting in an almost square-wave current at the
output.
• The output current (Io) can be expressed as a series of sine terms, with its fundamental
component being 4/π times the RF input (y) modulated by the LO frequency ωLO.
4 1 1
𝐼0 = π 𝐼𝐸𝐸 (𝑠𝑖𝑛𝜔𝐿𝑂𝑡 − 3 𝑠𝑖𝑛3𝜔𝐿𝑂𝑡 + 5 𝑠𝑖𝑛5𝜔𝐿𝑂𝑡-…..)

• The emitter current (IEE) consists of a large DC component and a small AC component due
to the RF input voltage.
1 − 𝑦 𝐼𝐸 1 − 𝐴𝑐𝑜𝑠𝜔𝑅𝐹𝑡 𝐼𝐸
𝐼𝐸𝐸 = =
4
2 2
1−y IE
• The total output is given by: 𝐼 = π
0 𝑠𝑖𝑛𝜔 𝑡
𝐿𝑂
2

5
• Fully Differential Circuit: The second pair (Q3-Q4) is added to create a fully
differential circuit. This results in the cancellation of LO terms and the addition
of RF input terms in the output.
𝐼 4 2
𝑍 = 𝐼0 = π 𝑦 sin 𝜔𝐿𝑂 𝑡 = π 𝑦 [cos(𝜔𝑅𝐹 - 𝜔𝐿𝑂)t]
𝐸

• Double-Balanced Mixer: The mixer is considered double-balanced, as neither

the LO nor the RF inputs feed through to the output.
• Feedthrough Considerations: In practical situations, small feed-throughs may
occur if the transistor pairs are not perfectly matched or if the input is not
perfectly differential.

6
MOS Gilbert Mixer Operation and Considerations
• An MOS version of the Gilbert mixer is based on the same principle.
• The mixer's output current (Io) for a MOS differential pair is expressed as:
1 𝑊 4𝐼𝑠
𝑉𝐷𝐷 𝐼0 = 2 𝜇𝐶𝑜𝑥 𝑉𝑋 𝑊 − 𝑉𝑋2
𝐿 𝜇𝐶𝑜𝑥 𝐿

I-V
+ 𝑣 −

𝐿𝑂 + 𝐿𝑂 − Switching
𝑀3 𝑀4 𝑀5 𝑀6

+𝑉𝑖𝑛/2 𝑀1 𝑀2 −𝑉𝑖𝑛/2
V-I

7
• Current Steering Condition: Complete current steering from one device to
the other occurs when
2𝐼𝑠
𝑉𝑋 = 𝑊 = 2 Veff
𝜇𝐶𝑜𝑥
𝐿

• The conversion gain is given by for given condition

2
π 𝑔𝑚 𝑅𝐿 , 𝑉𝑋 > 2 Veff

• where gm represents the transconductance of the input pair (M1-M2), and

RL is the load resistance.

8
Mixer Functions:
• The mixer operation can be broken down into three functions:
• Input V-I converter, often implemented using a pseudo-differential
pair for simplicity and a balance between headroom, noise, and
linearity.
• Switching quad (devices M3-M6) that commutates the RF current.
• Load, responsible for I-V conversion. It can be either active or
passive.
• Single-Ended Antenna Considerations: Most antennas are single-
ended, requiring additional components like transformers for
differential RF voltage generation. In such cases,
a single-balanced mixer may be a choice.

9
Balanced Topology
❖ Single-ended RF input:𝐼𝐷𝐶 + 𝐼𝑅𝐹 (where 𝐼𝑅𝐹 = 𝑔𝑚 ∗ 𝑉𝑅𝐹 𝑐𝑜𝑠(𝜔𝑅𝐹 𝑡))
❖ Differential LO Signal:

4 1
𝑉𝐿𝑂 𝑐𝑜𝑠 𝜔𝐿𝑂 𝑡 − 𝑐𝑜𝑠 3𝜔𝐿𝑂 𝑡 +. .
𝜋 3

❖ Differential output:
2
𝑉𝐼𝐹 = 𝑔𝑚 𝑅𝐿 𝑐𝑜𝑠 𝜔𝑅𝐹 − 𝜔𝐿𝑜 + 𝑐𝑜𝑠 𝜔𝑅𝐹 + 𝜔𝐿𝑂
𝜋
2
❖ Active Mixer 𝐺𝑎𝑖𝑛 = 𝜋 𝑔𝑚 𝑅𝐿

❖ IIP3 of mixer Aiip3 ∝ 𝑉𝑜𝑣

10
Single Balanced

❖ Single-ended input
❖ Differential LO
❖ Differential output
❖ RF transistor provide
❖ Gain=2/𝞹 gm RL

11
• Single-Balanced Mixer Operation: The single-balanced mixer
eliminates RF feedthrough under perfect matching conditions
but introduces LO feedthrough at the output. The LO
feedthrough is independent of the LO frequency and can only be
removed through IF filtering.
4
𝑅 𝐼 sin 𝜔𝐿𝑂 𝑡
π 𝐿0
• Noise and Interference: In a single-
balanced scheme, any noise or interference
at the LO port appears at the output,
making it important to consider potential
noise sources.

12
Linearity and IIP3 Considerations in Active Mixers
• In this context, the load, if designed properly and
𝑍𝐿
especially if it's resistive, typically does not 𝑀𝑢𝑠𝑡 𝑟𝑒𝑚𝑎𝑖𝑛 𝑖𝑛 𝑠𝑎𝑡.
contribute significantly to nonlinearity.
𝐿𝑂 + 𝑀3 𝑟0 𝑀4 𝐿𝑂 −
• Switching Components: The switches used in the
mixer also have a limited impact on overall
nonlinearity. 𝐼0
𝑀1 𝐶𝑃
• It's crucial to select appropriate DC biases for both
the output and LO signals to ensure that switches 𝑀𝑖𝑛𝑖𝑚𝑖𝑧𝑒𝑑
remain in saturation during the half-cycle they are
active.
• This helps in isolating lower transconductance
devices from the mixer's output.

13
• Minimizing Parasitic Capacitance: The parasitic capacitance at the common source of
each switching pair Cp must be minimized. In modern nanometer CMOS processes, this
condition is generally met comfortably for most GHz RF applications.
𝒈𝒎𝟑,𝟒
≫ 𝜔𝐿𝑂
𝑪 𝒑
• Transconductance Stage Impact: The transconductance stage appears to be a critical
factor influencing linearity.
• Challenges in Multi-Stage Mixers: Active mixers usually consist of multiple stages stacked
together, which can pose challenges in maintaining headroom and preventing unwanted
distortion.
• Achieving IIP3: Despite the challenges, achieving an IIP3
better than 1V (or 10dBm) is possible. Some literature reports
success in achieving this level of linearity for active mixers
operating at supply voltages as low as 1.2V.

14
 RF Transceiver Design
Lecture 46
Mixer Design - V

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
 Passive Mixer

4 1 1
𝑉𝐿𝑂(𝑡) = [cos(𝜔𝐿𝑂t) - cos(3𝜔𝐿𝑂t)+ cos(5𝜔𝐿𝑂t)]
𝜋 3 5

𝑉𝑅𝐹 𝑡 = 𝐴𝑅𝐹 cos(𝜔𝑅𝐹t)

𝑉𝐼𝐹 (𝑡) = 𝑉𝑅𝐹 (𝑡) 𝑉𝐿𝑂(𝑡)
2 1
𝑉𝐼𝐹 (𝑡) = 𝐴𝑅𝐹 (cos(𝜔𝐿𝑂- 𝜔𝑅𝐹 )t + cos 3(𝜔𝐿𝑂- 𝜔𝑅𝐹 )t)
𝜋 3

2
3
4
5
6
7
8
 RF Transceiver Design
Lecture 47
Mixer Design - VI

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
Flicker Noise Analysis in Active Mixer

2
Flicker Noise Analysis in Active Mixer

3
Flicker Noise Analysis in Active Mixer

4
Flicker Noise Analysis in Active Mixer
• Load Section Noise: Noise in the output load section is critical, especially in mixers, as it
doesn't undergo frequency translation and directly competes with the desired signal.
Reduction Strategies for Load Noise:
• PMOS Active Load: When a PMOS active load is employed, the device's channel length
should be carefully chosen to ensure that the 1/f noise corner frequency is below the
frequency of interest. This prevents excessive noise at the output.
• Polysilicon Resistors: Alternatively, mixer designers can choose to load the mixer with
polysilicon resistors. These resistors are advantageous as they are free from flicker noise.
However, this approach may require sacrificing some voltage headroom.
• Input FET noise: Noise in the lower transconductance FETs is
present alongside the RF input signal and undergoes
frequency translation, just like the RF signal itself.

5
• Flicker Noise Upconversion: Flicker noise in these FETs gets upconverted to ωLO
(LO frequency) and other odd harmonics during the frequency translation
process.
• White Noise Translation: Conversely, white noise at ωLO and other odd
harmonics is translated to DC during this process.
• Impact on Zero IF Output: When the output frequency of interest lies at or
around zero Intermediate Frequency (IF), the transconductance FETs primarily
contribute white noise after frequency translation. This is because the flicker
corner of these devices is usually much lower than the LO frequency.

6
• Switches – The noise transfer function to the output is linear (but time-variant), and the
superposition holds. Thus, it is sufficient to analyze the noise of one switch and simply
multiply the result by four as all the noise sources are uncorrelated.
• The switching noise Vn causes the skew in the switching instant that modulates the
differential current waveform at the mixer output. The height of the square-wave signal at
the output remains constant, but noise modulates its zero-crossing by Δt = vn/ S , where S
is the slope of the LO signal at zero-crossing. The waveform at the mixer output then
consists of a train of pulses with a width of Δt and amplitude of 2I and a frequency of 2ωLO.

• The low-frequency noise at the gate of a switch, vn, is directly transferred to the output
and will compete with a signal downconverted to zero IF.
2 𝑣𝑛 𝐼
𝑖𝑜𝑛 = 𝑇 2𝐼 ∗ Δt = 4𝐼 , 𝑖𝑜𝑛 = 𝜋𝐴 𝑣𝑛
𝑆𝑇

7
• If such a mixer is used for upconversion, then switches will have no flicker noise
contribution, but the flicker noise of transconductance stage will be directly
upconverted and appear at ωLO.
• The flicker noise component of input FET appearing at the output is:
𝑉𝑂𝑆 𝑉𝑂𝑆
𝑖𝑜𝑛 = 4𝐼 = 4𝑔𝑚 𝑣𝑛𝑖
𝑆𝑇 𝑆𝑇
𝐼 𝑉𝑂𝑆
= 𝜋𝐴 𝑣𝑛𝑖 , 𝑤ℎ𝑒𝑟𝑒 𝑆 = 2𝐴ωLO
𝑉𝑒𝑓𝑓

8
Active Mixers White Noise Analysis
• Mixer output thermal noise density is given by:
𝐼
𝑆𝑖𝑜𝑛 = 2 × 4𝐾𝑇𝛾𝑔𝑚 + 4 × 4𝐾𝑇𝛾 + 2 × 4𝐾𝑇/𝑅𝐿
𝜋𝐴

switch Input FETs Load

• The mixer is loaded with a resistance of 𝑅𝐿

2
• The current conversion gain is 𝜋 𝑔𝑚, the noise figure
• with respect to a source resistance of RS is:
𝜋2
4 2𝛾 𝐼 𝐼
𝐹 =1+ 𝛾+ +
𝑔𝑚 𝑅𝑆 𝑔𝑚 𝜋𝐴 𝑔𝑚 𝑅𝐿

9
Active Mixers 2nd-Order Distortion
𝐴𝑠𝑖𝑛 𝜔𝐿𝑂 𝑡 −𝐴𝑠𝑖𝑛 𝜔𝐿𝑂 𝑡
• The potential contributors for second order
distortion:
➢ Input FETs 𝛼𝑉𝑖𝑛 −𝛼𝑉𝑖𝑛
➢ Switches 𝐼𝑜 + 𝑔𝑚 𝑉𝑖𝑛 𝑉𝑖𝑛
➢ Feedthrough

RF Self-mixing

10
Active Mixers 2nd-Order Distortion
𝐴𝑠𝑖𝑛 𝜔𝐿𝑂 𝑡 −𝐴𝑠𝑖𝑛 𝜔𝐿𝑂 𝑡
• The potential contributors for second order
distortion:
➢ Input FETs 𝛼𝑉𝑖𝑛 −𝛼𝑉𝑖𝑛
➢ Switches 𝐼𝑜 + 𝑔𝑚 𝑉𝑖𝑛 𝑉𝑖𝑛
➢ Feedthrough

• The 2nd order coefficient is given by:

4𝛼 2𝑇𝑠 8𝛼 RF Self-mixing
𝑎2 = 𝑔 = 𝑔
∆𝑉 𝑚 𝑇 𝑆×𝑇 𝑚

• The fundamental coefficient is a1 = 2 π/gm

𝑎1 𝑇
𝐼𝐼𝑃2 = =𝑆×
𝑎2 4𝜋𝛼

11
Input FET 2nd-Order Nonlinearity
1 2
• The square-law FET creates a 2nd-order component, 2 𝛽𝑣𝑖𝑛
𝑉𝑂𝑆
• The 2nd-order coefficient is a2 = 2𝛽
𝑆×𝑇

𝑉𝑒𝑓𝑓 𝑆×𝑇
• IIP2 is given by: 𝐼𝐼𝑃2 = 𝑉𝑂𝑆 𝜋
where Veff is the input FET overdrive voltage.
• Switching quad -The switches contribute mainly due to the
parasitic capacitances at their common source and in the presence
of mismatches. So their contribution is dominant only at high
frequencies, and can be improved by reducing the parasitic
capacitances at the common source of each pair.

12
 RF Transceiver Design
Lecture 48
Mixer Design - VII

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
Design Considerations for Passive Mixers
• Passive mixers rely on power-efficient on/off switches.
• Sharp rail-to-rail waveforms are needed for improved
performance, increasing power consumption in LO 𝐿𝑂 +
delivery circuits compared to active mixers.
𝑀3
𝐼−𝑉
𝑀4
𝑉−𝐼 𝐼−𝑉
𝐿𝑂 + 𝐿𝑂 − 𝐿𝑂 − Passive Mixer
𝑀3 𝑀4 𝑀5 𝑀6
𝐿𝑂 − 𝑀5
𝑉−𝐼
𝑀6

Active Mixer 𝐿𝑂 −
2
Drawbacks of Active Mixers
• linearity Due to device stacking
• Poor 1/f noise.
Passive mixer:
• Cascading the stages resolves these issues and can include a
blocking capacitor for zero DC bias and reduced flicker noise.
• The fundamental difference between the active and passive mixers
is that the latter commutates the AC signal (whether it is a current
or voltage) only.
• The blocking capacitor can be removed, and common-mode
feedback (CMFB) circuitry added for equalizing DC levels on both
sides of switches and eliminating DC current.

3
Current Mode Passive Mixers
• A TIA is essential for converting input current to voltage and
providing low input impedance to mixer switches.

Voltage-Mode Passive Mixers

• In voltage-mode passive mixers, the buffer following the
mixer should present a high-impedance circuit to ensure
voltage-mode operation.

4
Current Mode Mixer and LO Duty Cycle
• Operation with Overlapping Clocks
• During the period T/2 < t < T/2 + τ, both switches turn on.
• Result: RF current is split equally and appears at both output
branches.
• In differential measurement, this results in no net output
current.
Negative Overlap Positive Overlap
LO1
Effective LO LO2

5
• Operation with Non-overlapping LO Signals
• In the case of non-overlapping LO signals, there is a negative overlap time
duration τ where both switches are off.
• Result: No current appears at the output during this duration.
Output Current Calculation
• The output current (io) is equal to the source RF current (is) multiplied by the
effective LO waveform.
• The effective LO signal's fundamental frequency is determined by a simple
Fourier analysis.
4
π cos(𝜔𝐿𝑂 𝜏/2) sin(𝜔𝐿𝑂𝑡 − 𝜔𝐿𝑂 𝜏/2)

6
 2
• Mixer conversion current gain (AI) is given by A𝐼 = π cos(𝜔𝐿𝑂 𝜏/2)
• AI is maximum when τ is zero, indicating zero overlap or a 50% duty cycle for the
LO signal.
• Deviations from a 50% duty cycle result in either no RF current output

Quadrature Mixers and LO Signal Overlap

LO Waveforms in Quadrature Mixers

• LO waveforms shown in Figure are shifted by T/4 or π/2.

• LO1–3 represent differential LO signals, while LO2–4 represent
• differential Q LO signals.

7
 Effect of Negative Overlap (τ < 0)
• Negative overlap results in a period where all four switches are off.
• Mixer conversion gain is expected to decrease in this case.
Analysis of Positive Overlap (τ > 0)
• For τ < t < T/4, only LO1 is active, directing RF current to the TIA.
• From t = T/4 to t = T/4 + τ, both I+ and Q+ switches are active, splitting RF
current.
• At t = T/4 + τ, the I switch turns off, and no current appears at the output.
• A similar situation occurs for the I– branch.
• Fourier series analysis results in a fundamental LO signal.
2 2 𝜋
cos(𝜔𝐿𝑂 𝜏/2) cos(𝜔𝐿𝑂𝑡 − 𝜔𝐿𝑂 𝜏 − )
π 2 4

8
 Practical LO Ideal LO

Effective LO LO4 LO3 LO2 LO1

Overlapping LO signals

Effective LO LO4 LO3 LO2 LO1

Ideal LO waveforms

Conversion Gain
Duty Cycle, %

9
 2
• Currrent conversion gain is given by: cos(𝜔𝐿𝑂 𝜏/2)
π
• Maximum conversion gain is achieved with τ = 0 or a 25%
duty cycle LO signal.
• Simulation Results
• Figure shows a simulation of a 40nm passive mixer for
various cases.
• The simulation findings align closely with the analysis,
except for cases with less than 25% duty cycle LO signals.
• During no overlap time, the RF current source charges this
capacitance almost linearly, and once any of the switches
are turned back on, this charge is delivered to the output,
retrieving some of the signal loss.

10
• Preference for Non-overlapping Clocks
• Non-overlapping clocks are preferred in
practice for passive mixers. LO1

• Overlapping LO signals introduce cross-talk

LO2
and degrade mixer noise and linearity.
÷2
LO3

LO4

• Methods for generating 25% quadrature LO signals, including

the use of AND gates and shift registers.
• Shift registers are advantageous for phase error and jitter.

11
Managing Overlap
• Choosing the size of inverter buffers to minimize overlap, considering
process and temperature variations.
• Small no-overlap periods are generally acceptable.
• Overlapping must be avoided to prevent cross-talk and image issues.

TIA I
∆𝑣 = 𝜏 × 𝑖𝑠 /𝐶𝑝 (Zin=0)

TIA Q
(Zin=0)

12
8-Phase Mixers • 2 phase mixer: Two-point sampling
2
• Conversion gain=
π
• 4-phase mixer: four-point sampling
2 2
• Conversion gain=
π
• 8-phase mixer: Eight-point sampling
Actual LO waveforms
LO1 VDD • Employing an 8-phase LO in mixer design offers advantages in harmonic
rejection, noise aliasing reduction, and immunity to harmonic blockers.
LO2
• Rejection of harmonics up to the 7th order.
LO3 • This leads to a more fundamental gain, reducing unwanted harmonic
components in the mixer's output.
LO4
• To generate the required 8-phase LO signals,
LO5 the fundamental LO frequency is set at four
LO6 times the LO frequency. Signal generation
involves using a divide-by-4 circuit along
LO7
with AND gates
LO8

13
M-Phase Mixers
• Fourier series representation for each of the LO signals driving the branches:
𝑗𝑘𝑛2𝜋
− 𝑀
𝑆𝑘 𝑡 = σ∞
𝑛=−∞ 𝑎𝑛 𝑒 𝑒 𝑗𝑛𝜔𝐿𝑂𝑡

• where Sk is the effective LO switching the kth branch, k = 1, ..., M, and

𝑗𝑘𝑛2𝜋
𝑒 𝑀 𝑛
𝐿𝑂1 𝑎𝑛 = 𝑠𝑖𝑛𝑐 ( )
𝑀 𝑀

𝐿𝑂2 𝐿𝑂1

𝑖𝑅𝐹 𝐿𝑂2
𝑉1
+
𝑉𝑅𝐹
𝐿𝑂𝑀 𝐿𝑂𝑀

14
• It is obvious that the effective LO signals are identical, but shifted only by T/M with
respect to each other. Now the net effective LO, S(t), consists of the effective LO signals
𝑘−1 2𝜋
of each branch, scaled by cos( ) and added together:
𝑀
𝑗𝑛2𝜋
𝑘−1 2𝜋 2𝜋
S 𝑡 = σ𝑀
𝑘=1 cos 𝑆𝑘 𝑡 = σ∞
𝑛=−∞ 𝑎𝑛 𝑒 𝑀 𝑒 𝑗𝑛𝜔𝐿𝑂𝑡 σ𝑀−1
𝑘=0 cos 𝑘 𝑆𝑘 𝑡
𝑀 𝑀
• For the main harmonic then, n = 1, and the effective LO for say the output v1 becomes:
𝑗𝑛2𝜋
2𝜋 𝑀
σ𝑀−1
𝑘=0 cos 𝑘𝑀 𝑒 𝑀 = 2
1
sinc cos(𝜔𝐿𝑂 𝑡 − 𝜋/𝑀)
M

15
• Implications of Increasing the Number of Phases in Mixer

𝐸𝑓𝑓𝑒𝑐𝑡𝑖𝑣𝑒 𝐿𝑂 𝐴𝑚𝑝𝑙𝑖𝑡𝑢𝑑𝑒, 𝑑𝐵
Design:
• As the number of phases (M) in mixer design approaches infinity,
the effective LO signal closely approximates an ideal cosine
waveform.
• Despite the switches being driven by square-wave signals, the
effective LO amplitude approaches unity, resulting in minimal
harmonic downconversion.
• While larger M values require more complex clock generation, M
= 8 is considered an optimum choice, balancing gain/noise 𝑁𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑃ℎ𝑎𝑠𝑒𝑠(𝑀)
considerations.
8 𝜋
• In the case of 8-phase, the effective LO amplitude is sin( ) ≈ 0.97
𝜋 8
• 4-phase mixers are the most popular choice for narrowband receivers
due to the complexity and LO generation overhead for higher values of
M.

16
 RF Transceiver Design
Lecture 49
Mixer Design - VIII

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
Operation of Passive Mixers LO1

• Each TIA has a single-ended input impedance denoted as ZBB.

• The effective LO signals, denoted as S1(t), S2(t), ..., are similar to LO1,
LO2, ... but toggle between 0 and 1.
• The Fourier series representation of the effective LO signals vRF LO2

𝑆1 𝑡 = σ∞ 𝑗𝑛𝜔𝐿𝑂𝑡 LO3
𝑛=−∞ 𝑎𝑛 𝑒

𝑗𝑛𝜋
iRF
−
𝑆2 𝑡 = σ∞
𝑛=−∞ 𝑎𝑛 𝑒 2 𝑒^(𝑗𝑛𝜔𝐿𝑂 𝑡)

𝑆3 𝑡 = σ∞
𝑛=−∞ 𝑎𝑛 𝑎𝑛 𝑒
−𝑗𝑛𝜋 𝑗𝑛𝜔𝐿𝑂𝑡
𝑒 LO1 LO4
𝑗𝑛𝜋
𝑆4 𝑡 = σ∞
𝑛=−∞ 𝑎𝑛 𝑒 2 𝑒^(𝑗𝑛𝜔𝐿𝑂 𝑡) LO2
𝑗𝑛𝜋
𝑒− 4 𝑛 LO3
𝑎𝑛 = 𝑠𝑖𝑛𝑐( )
4 4
LO4

2
• Since a given switch is on only at one-quarter of a cycle, for the corresponding branch, the
I switch toggled by LO1, 𝑖𝐵𝐵𝐼+ = 𝑆1 𝑡 𝑖𝑅𝐹 (𝑡)
• This baseband current in turn creates a voltage across the input of the TIA.
• This baseband voltage is only transparent to the RF input when S1 is 1, and thus is
effectively multiplied by S1 when monitoring the RF voltage.
• Considering all the four branches and switch resistance, 𝑣𝐵𝐵𝐼+ = [𝑆1 𝑡 𝑖𝑅𝐹 (𝑡)] ∗ 𝑧𝐵𝐵(𝑡)
• The Fourier transform of Sk(t) X {[Sk(t)iRF(t)] ∗ zBB(t)} is:

vRF t = 𝑅𝑆𝑊 𝑖𝑅𝐹 𝑡 + σ4𝑘=1 𝑆𝑘 𝑡 × {𝑣𝐵𝐵𝐼+ + [𝑆1 𝑡 𝑖𝑅𝐹 (𝑡)] ∗ 𝑍𝐵𝐵(𝑡)}

𝑗 𝑛+𝑚 𝑘−1 𝜋
−
σ∞ ∞
𝑚=−∞ σ𝑛=−∞ 𝑒 2 𝑎𝑛 𝑎𝑚 𝐼𝑅𝐹 𝜔 − 𝑛 + 𝑚 𝜔𝐿𝑂 𝑍𝐵𝐵 (𝜔 − 𝜔𝐿𝑂)

3
• The RF voltage can be written as:
∞
vRF t = 𝑅𝑆𝑊 𝐼𝑅𝐹 𝜔 + ෍ 𝑎𝑛 𝑎𝑚 𝐼𝑅𝐹 𝜔 − 𝑛 + 𝑚 𝜔𝐿𝑂 𝑍𝐵𝐵 (𝜔 − 𝑛𝜔𝐿 )
𝑚,𝑛=−∞
• If the RF current is a sinusoid at a frequency of ωLO + ωm, then the RF voltage has its main
component at ωLO + ωm, receiver provides some modest filtering, then, n + m = 0, and we have:
• The impedance seen at the RF input node as:
vRF 𝜔 = 𝑅𝑆𝑊 𝐼𝑅𝐹 𝜔 + 4 σ∞ 2
𝑛=−∞ 𝑎𝑛 𝐼𝑅𝐹 (𝜔) 𝑍𝐵𝐵 (𝜔 − 𝑛𝜔𝐿)}
• Which indicates that the TIA input impedance appears at RF, at around the LO frequency and its
harmonics.

𝑍𝐵𝐵

0 −𝑓𝐿𝑂 0 + 𝑓𝐿𝑂

4
• In the vicinity of ωLO, we have
2
Z𝐼𝑁 𝜔 ≈ 𝑅𝑆𝑊 + ( 2)[𝑍𝐵𝐵 (𝜔 + 𝜔𝐿𝑂) + 𝑍𝐵𝐵(𝜔 + 𝜔𝐿𝑂)]
𝜋
• The baseband impedance is transformed to the input around ωLO.
• Accordingly, if the baseband impedance is lowpass, the corresponding RF input
sees a bandpass impedance, whose center frequency is precisely set by the LO.
• This property may be utilized to create low-noise narrowband filters, often
called N-path filters.

5
Noise Considerations in Passive Mixers
Minimal Noise with Non-overlapping LO Signals
• Passive mixers with non-overlapping LO signals have minimal noise contributions.
• Switches in the Triode region with zero bias current have negligible 1/f noise
contribution.
• Well-designed passive mixers typically exhibit negligible 1/f noise.
Understanding Thermal Noise Contribution
• At any given time, only one switch is active, and its resistance and noise are in
series with the current from the gm cell.
• This noise voltage's spectral density is 4KTRSW (RSW is the switch
resistance).
• The current noise spectral density is 4KTRSW/|ZL|^2.
• If the gm cell is ideal (𝑍𝐿 is infinite), switches contribute almost no
noise.
6
Impact of Switch Mismatches
• Mismatches between switches can lead to leakage of flicker noise of the gm stage to the output.
2 𝑉𝑂𝑆
• The leakage gain is , Where OS is the input-referred offset voltage, and S X T is the normalized
𝑆×𝑇
slope of LO signals.
• High-pass filtering, such as a blocking capacitor can suppress this noise.

gm
ZL

7
Linearity in Current-Mode Passive Mixers
• Superior Linearity Compared to Active Mixers
• Passive mixers in the current domain, with impedance transformation properties, offer
superior linearity compared to active mixers.
• Fig. demonstrates the scenario of a small desired signal with a large blocker.

ZBB
gm
ZBB

8
Impedance Transformation and Small Input Impedance
• If the TIA presents a very small input impedance to the switches and switch resistance is
low, the gm cell sees a small impedance at its output.
• This ensures a small swing at the gm cell output.
• A large capacitance at the TIA input creates a bandpass filter that suppresses the blocker.
• Downconversion shifts the signal to DC, while the blocker remains at a higher frequency.
• Lowpass filtering easily suppresses the blocker.
• Ensuring the filtering does not affect the desired signal is typically feasible due to the
large ratio of blocker offset to signal bandwidth (5–10 times).

9
Trade-offs and Design Considerations
• Larger switch size leads to more blocker suppression however, mixer buffer
power consumption is increased.
• Designing the TIA is critical, particularly for maintaining a low input impedance.
• Blocker tolerance is substantially enhanced compared to traditional voltage-
mode receivers.

10
Second-Order Distortion in Passive Mixers
• Passive mixers exhibit second-order distortion mechanisms similar to active mixers.
• These mechanisms include:
• Direct leakage of IM2 components due to mismatches among the mixer switches (leakage gain:
2 VOS /( S*T)).
• RF-to-LO coupling in the downconversion mixer (leading to IIP2 = 2 * S * T / πα) where α is the
leakage gain.
• Nonlinearity of the mixer switches caused by β and threshold voltage mismatches.
• Attenuation of IM2 Components
• Series capacitors between the LNA/RF gm cell and the switches
attenuate IM2 components generated inside the LNA, preventing
their contribution to receiver IIP2.
• IM2 sources may contribute to IIP2 by modulating the resistance
of the mixer switches and affecting their on/off timing.

11
Modulation of Switch Resistance vs. Timing
• Modulating the resistance of switches has a more significant impact on IM2 products
than modulating the switch timing.
• Passive mixer switches are clocked by rail-to-rail signals with fast rise and fall times,
minimizing timing-related distortions.
Conclusion
• A properly designed passive mixer with 25% clocking is expected to have a reasonably
small contribution to IIP2 from the mixer switches.

12
TIA Design Choices for Passive Mixers
Drawbacks of Simple TIA Configuration
• A basic TIA configuration with a pair of resistors (RBB) suffers from a fundamental trade-
off.
• The mixer’s overall gain and TIA input impedance are both determined by RBB.
• High gain and low input impedance cannot be simultaneously achieved.
𝑅𝐿 2
• The mixer total conversion gain is 𝑔𝑚 2 𝑅𝐵𝐵
𝑅𝐿 + 𝑅𝐵𝐵 𝜋
LO1 𝜋2
2
𝜋

LO2
RF gm
13
• Overcoming the Trade-Off
• To break the trade-off, two alternatives are considered:
• Common-gate amplifier.
• Opamp in feedback configuration.
• Both choices offer an input resistance of approximately 1/gmBB, where gmBB is the input device
transconductance.
• Large input capacitance keeps TIA input impedance low at the blocker offset frequency.
2CF
CF RF
RF
+ +
- -
CF

Resistor

14
• Gain Independence and Linearity
• The gain is now set independently by the load or feedback
resistor (RF).
𝑅𝐿 2
• Mixer gain expression: 𝑔𝑚 𝑅𝐹
2 𝜋
𝑅𝐿 + 𝑔
𝜋 2 𝑚𝐵𝐵

• Gain and input impedance can be adjusted independently.

• Feedback capacitor sets TIA bandwidth, acting as a single-
pole RC filter.

15
• Comparing Common-Gate and Opamp Configurations
• The common-gate (CG) structure tends to be smaller since it requires four times
less differential load capacitance for the same bandwidth.
• Opamp-based design may offer superior linearity.
• CG structure may introduce noise from the current source, which can be
replaced with a resistor or large devices to mitigate flicker noise.
• Opamp choice can be a two-stage or complementary single-stage structure,
However, Opamp must have sufficient bandwidth to ensure good linearity for
all blocker frequencies.

16
 RF Transceiver Design
Lecture 50
Mixer Design - IX

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
Voltage-Mode Passive Mixers
𝐿𝑂 + 𝑩𝑼𝑭
• Similarity with RF Amplifiers
• Voltage-mode passive mixers commutate
RF AC voltage.
• The RF amplifier driving the mixer is not
fundamentally different from current-
𝑹𝑭 𝑨𝒎𝒑
mode mixers.
𝑍𝑖𝑛 ≫ 1
𝐿𝑂 −

𝐿𝑂 − 𝑩𝑼𝑭

2
Distinguishing Factor: Following Circuitry
• The key difference is the circuit that follows the switches.
• Voltage-mode mixers drive a voltage buffer with infinite input
impedance.
• Current-mode mixers have a TIA with ideally zero input impedance.
• The RF amplifier preceding the switches operates similarly in both
modes.
Operation, Noise, and Linearity
• Mixer operation, noise characteristics, and linearity trade-offs are
similar between voltage-mode and current-mode passive mixers.
• Current-mode mixers are superior in terms of switch noise and
distortion.

3
LO Drive Requirements
• Active mixers can efficiently use CML logic to generate sinusoidal LO signals up to one-
third of technology transit frequency (fT).
• Passive mixers require non-overlapping clocks with <50% duty cycle, limiting their use of
sinusoidal LOs.
• In the 40 nm CMOS process, the rise and fall time are on the order of 10 ps. Therefore,
50% and 25 % duty cycle LO design is limited to 12.5 GHz, and, 6.25 GHz respectively.
• Passive mixers are mainly suitable for radio frequencies due to LO limitations.

4
Blocker-Tolerant Receivers
Introduction
• In many receiver architectures, the presence of RF filters is crucial to mitigate large out-of-band
blockers.
• For example, in GSM, powerful blockers (0dBm) can compress the receiver and desensitize it.
• Recent research efforts aim to relax or eliminate the need for RF filtering.
• Various topologies have been developed to achieve this goal.
Importance of RF Filtering
• RF filters are essential for traditional receivers to prevent strong out-of-band signals from interfering
with the desired signal before downconversion.
Arbitrary Choice of IF
• The choice of Intermediate Frequency (IF), whether zero or not, is
arbitrary in these architectures. All of them rely on quadrature
downconversion.

5
Current-Mode Receivers
• Current-mode receivers rely on a low-noise transconductance amplifier (LNTA) followed
by passive mixers operating in the current domain.

TIA

gm

TIA

6
Impedance Transformation Properties
• Passive mixers in current-mode receivers exploit impedance transformation
properties.
• Two key features:
➢ Low TIA input impedance is driven by mixer switches with low resistance results
in minimal swing at the LNTA output.
➢ Lowpass roll-off in the TIA creates a high-Q bandpass filter at the LNTA output.
• Good linearity at the RF front end and progressive filtering of the blockers along the
receive chain.
• A large capacitor at the TIA input helps attenuate the blocker, given that the TIA
input impedance tends to increase at higher frequencies

7
Mixer first receivers
External Filtering in Current Mode Receivers
➢ Current mode receivers significantly improve linearity.
➢ Despite improvements, external filtering (directly or through a duplexer) may
still be necessary to tolerate the 0dBm GSM blocker.
Removing the Low-Noise Amplifier (LNA)
➢ An alternative proposal to enhance receiver linearity and
eliminate RF filters is to eliminate the LNA.
➢ Such a receiver configuration improves linearity but may
suffer in noise figure.
➢ The receiver noise figure may be expressed as

8
 2
𝑅 𝑣𝑏𝑏
𝑓 ≈ [1 + 𝑆𝑊 + ]
𝑅𝑠 4𝑀𝐾𝑇𝑅𝑠
Harmonic
combination

where RSW is the mixer switch resistance, Rs is the

source resistance, vbb2 is the TIA input noise voltage
referred to each single-ended switch, and K captures
the noise folding.

9
• Even for an 8-phase design, the noise figure
reaches 3dB or higher once input matching
conditions are met.
• In practice, the noise figure can be even worse
due to parasitic elements.
Applications
• The mixer-first receiver with a somewhat
worse noise figure may be acceptable for low-
power applications like Bluetooth or low-
power WLAN.
• In more demanding applications such as
cellular, the higher noise figure is typically
unacceptable.
10
Noise-Cancelling Receivers
• Mixer-first receivers can be considered as using explicit 50Ω
resistance for matching.
• These receivers are linear and wideband but have poor noise
RA
+
figures. gm
-
Rs
Noise-Cancelling Receiver Implementation
• The main path provides a current measurement, and
matching is adjusted using the mixer switch and TIA input -
RM
resistance. +
• The voltage gain is RM/Rs.
• An auxiliary path provides a voltage measurement using a
current-mode receiver with low-noise transconductance 2
𝑅𝑆𝑊 + 𝑅 ≈ 𝑅𝑠
stages and current-mode mixers. 𝜋 2 𝐵𝐵
• The total gain of this path is gmRA.
• Noise cancellation is achieved by adjusting the feedback
resistors of each TIA based on the condition gmRA = RM/Rs.

11
Case Study - Noise-Canceling Receiver
• A complete noise-canceling receiver designed for wideband
applications.
• It uses 8-phase mixers for harmonic rejection and noise
cancellation.
• The low-noise transconductor linearity is critical, therefore, a
complementary structure is chosen.
• The receiver NF is1 + γ/(gmRs), with noise contribution of TIAs in
the auxiliary path suppressed by the RF gm cell gain.
• Measured NFs demonstrate sub-2dB NF with noise cancellation
enabled.
• The receiver combined the current-mode receiver concept, noise
cancellation, and mixer-first receiver idea for improved NF and
linearity.

12
13
14
References:

1) Darabi, Hooman. Radio frequency integrated circuits and systems.

Cambridge University Press, 2015.
2) Razavi Behzad. RF microelectronics. Vol. 2. New York: Prentice hall, 2012.
3) Pozar, David M. Microwave engineering. John wiley & sons, 2011.

15
 RF Transceiver Design
Lecture 51
Oscillator Design - I

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
Performance Parameters
• Frequency Range
• Output Voltage Swing (Power)
• Drive Capability
• Phase Noise
• Output Waveform (Duty Cycle)
• Supply Sensitivity
• Power Dissipation
11aTRX

11b/g TRX

5.2-5.8 GHZ

𝑓𝐿𝑂
÷2
2.40-2.48 GHz

2
Oscillator
180°
Type Type
+ +
𝑋 +
equation 𝐻(𝑠) 𝑌 𝑋 +
equation 𝐻(𝑠) 𝑌
− − A
here. here.
360°

•A negative-feedback circuit may oscillate at ω0 if it satisfies:

𝐻(𝑠 = 𝑗𝜔1 ) =1
< 𝐻(𝑠 = 𝑗𝜔1 ) = 180°

•“Barkhausen criteria.” (necessary but not sufficient.)

• May state 2nd criterion as a total phase shift of 360.
• Loop gain typically chosen to be at least 2 or 3 times the required
value.

3
2nd Barkhausen Criterion
• Equivalent in terms of the second Barkhausen criterion:

Type 𝐻(𝑗𝜔)
Type 𝐻(𝑗𝜔) Type 𝐻(𝑗𝜔)
+ + +
+
equation +
equation +
equation
− + +
here. here. here.
180° 360° 0°

• Frequency-dependent phase shift = 180(arrow),

dc phase shift = 180
• Total phase shift at ω0 = 360.
• No phase shift at ω0 is provided.

4
Example
Explain why a single common-source stage does not oscillate if it is placed in a unity-gain loop?
Solution:
• Open-loop circuit of a single CS stage contains only one pole.
• Maximum frequency-dependent phase shift = 90 (at a frequency
of infinity).
• DC phase shift = 180°.
• Maximum total phase shift = 270(<360).
Fail to sustain oscillation growth.

5
Two-Pole Feedback System

• Two significant poles appear in the signal path ➔ frequency-

dependent phase shift can approach 180°.
• Signal inversion through each common-source stage ➔
positive feedback!
• It simply “latches up” rather than oscillates.

6
Additional Signal Inversion

• This provides negative feedback near zero frequency &

eliminates “latch-up”.
• Two poles: One at E and another at F.
• Does this circuit oscillate?

7
Two-Pole System: Loop Gain Characteristics
20𝑙𝑜𝑔 𝐻(𝜔)
• Frequency-dependent phase shift reaches
180° but at ω = infinity.
• Loop gain vanishes at very high frequencies
➔ the circuit does not satisfy both
0 𝜔𝑝,𝐸 = 𝜔𝑝,𝐹 𝜔(log 𝑎𝑥𝑖𝑠) Barkhausen criteria at the same frequency.
0 𝜔(log 𝑎𝑥𝑖𝑠)
• It fails to oscillate!

−90°

−180°
< 𝐻(𝜔)

8
Three-Stage Ring Oscillator

•If three stages are identical, total phase shift around the loop
(ϕ) = -135° at ω = ωp,E(= ωp,F = ωp,G) and -270 at ω = ∞.
•ϕ = 180 at ω < ∞, where the loop gain can be still ≥ 1.

9
Minimum Voltage Gain Per Stage
•For the three-stage ring oscillator, denote the transfer function of each stage by –A0/(1+s/ω0)
and the loop gain is:
𝐴30
𝐻 𝑆 =− 3
𝑆
1+𝜔
𝑜

•The circuit oscillates if each stage contributes 60:

𝜔𝑜𝑠𝑐
𝑡𝑎𝑛−1 = 60° 𝜔𝑜𝑠𝑐 = 3𝜔0
𝜔0
•Minimum voltage gain per stage (A0) is such that the magnitude of the loop gain at ωOSC
is unity:
𝐴30
𝜔 2 =1 𝐴0 = 2
1+ 𝑂𝑆𝐶
𝜔0

10
Waveforms of Three-Stage Ring Oscillator
•Each stage contributes a
𝑽𝑬
frequency-dependent shift of 60°
and a dc signal inversion.
•Thus the waveform at each node is
𝑽𝑭 240 (or 120) out of phase with
respect to its neighboring nodes.

𝑽𝑮

11
One-Port View of Oscillators 𝑰𝟎
𝑪𝟏

𝐼0
0 𝑡
0 𝑡
𝑰𝟎
𝑪𝟏
𝐼0

0 𝑡
0 𝑡

12
 −𝑔𝑚 −𝑔𝑚
𝐶1 𝐶2 𝜔 2 𝐶1 𝐶2 𝜔 2

𝐿1

𝐶1 𝐶2 𝑅𝑆 𝐶1 𝐶2
𝐶1 + 𝐶2 𝐶1 + 𝐶2

𝐼𝑋 𝑔𝑚 1 𝑔𝑚
− + 𝑉𝑋 = 𝐼𝑋 + 𝐼𝑋 𝑅𝑆 =
𝐶1 𝑆 𝐶1 𝑆 𝐶2 𝑆 𝐶1 𝐶2 𝜔 2
𝑉𝑋 1 1 𝑔𝑚 1
𝑆 = + + 𝜔𝑜𝑠𝑐 =
𝐼𝑋 𝐶1 𝑆 𝐶2 𝑆 𝐶1 𝐶2 𝑆 2
𝐶𝐶
𝐿1 𝐶 1+ 2𝐶
𝑉𝑋 1 1 𝑔𝑚 1 2
𝑗𝜔 = + −
𝐼𝑋 𝑗𝐶1 𝜔 𝑗𝐶2 𝜔 𝐶1 𝐶2 𝜔 2

13
Tuned Oscillator 𝑉𝑜𝑢𝑡
𝑉𝑖𝑛

0 𝜔𝑜 𝜔
0 𝜔
−90°
−180°
At Low Freq, L dominates: −270°
𝑉𝑜𝑢𝑡 𝑉𝑜𝑢𝑡
≈ −𝑔𝑚 𝐿1 𝑠 <
𝑉𝑖𝑛
𝑉𝑖𝑛
At High Freq, C dominates: At Resonance:
𝑉𝑜𝑢𝑡 1 𝑉𝑜𝑢𝑡
≈ −𝑔𝑚 ≈ −𝑔𝑚 𝑅𝑝
𝑉𝑖𝑛 𝐶1 𝑠 𝑉𝑖𝑛

14
Cascade of Two Tuned Amplifiers in Feedback Loop

𝑉𝑋
𝑉𝐷𝐷

𝑉𝑌

2
𝑔𝑚 𝑅𝑃 ≥1

15
Cross-Coupled Oscillator

+
+
−
−

1
𝜔𝑜𝑠𝑐 =
𝐿1 (𝐶𝐺𝑆2 + 𝐶𝐷𝐵1 + 4𝐶𝐺𝐷 + 𝐶1

4
𝑉𝑋𝑌 ≈ 𝐼 𝑅
𝜋 𝑆𝑆 𝑃

16
One-Port View of Cross-Coupled Oscillator
𝐶 1
2
𝐼𝑋 = −𝑔𝑚1 𝑉1 = 𝑔𝑚2 𝑉2

𝑉𝑋 1 1
=− +
𝐼𝑋 𝑔𝑚1 𝑔𝑚2

For gm1 = gm2 =gm

For oscillation to occur, the negative resistance must cancel the loss of the
tank:
2
≤ 2𝑅𝑃 ⇒ 𝑔𝑚 𝑅𝑃 ≥ 1
𝑔𝑚

17
 RF Transceiver Design
Lecture 52
Oscillator Design - II

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
Three-Point Oscillators
• Three different oscillator topologies can be obtained by grounding each of the transistor terminals.

If C1 = C2, transistor must provide sufficient transconductance to satisfy

𝑔𝑚 𝑅𝑃 ≥ 4
Drawback:
• Requirement of High Q Inductor
• Single Ended output
2
Voltage-Controlled Oscillators:
𝜔𝑜𝑢𝑡 = 𝐾𝑉𝐶𝑂 𝑉𝑐𝑜𝑛𝑡 + 𝜔0

VCO

• The output frequency varies from ω1 to ω2 (the required tuning

range) as the control voltage, Vcont, goes from V1 to V2.
• The slope of the characteristic, KVCO, is called the “gain” or
“sensitivity” of the VCO and expressed in rad/Hz/V.

3
VCO Using MOS Varactors

1
𝜔𝑜𝑠𝑐 =
𝐿1 (𝐶1 + 𝐶𝑉𝑎𝑟 )

• Since it is difficult to vary the inductance electronically, we only

vary the capacitance by means of a varactor.
• MOS varactors are more commonly used than pn junctions,
especially in low-voltage design.

4
LC VCOs with Wide Tuning Range: VCOs with Continuous Tuning

• The CM level is simply given by the gate-source voltage of a diode-

connected transistor carrying a current of IDD/2.
𝐼𝐷𝐷
𝑉𝐺𝑆1,2 = + 𝑉𝑇𝐻
𝑊
𝜇𝑛 𝐶𝑜𝑥
𝐿

5
VCO Using Capacitor Coupling to Varactors

• To avoid varactor modulation due to the noise of the bias current source,
we return to the tail-biased topology but employ ac coupling between the
varactors and the core so as to allow positive and negative voltages across
the varactors.
• The principal drawback of the above circuit stems from the parasitics of
the coupling capacitors

6
VCO Using Capacitor Coupling to Varactors: Parasitic Capacitances to
the Substrate
• The choice of CS = 10Cmax reduces the capacitance range by 10% but introduces substantial
parasitic capacitances at X and Y or at P and Q because integrated capacitors suffer from
parasitic capacitances to the substrate.

Cb/CAB typically exceeds 5%

Substrate

7
Discrete Tuning

• In applications where a substantially wider tuning range is necessary, “discrete tuning”

may be added to the VCO so as to achieve a capacitance range well beyond Cmax/Cmin
of varactors.
• The lowest frequency is obtained if all of the capacitors are switched in
1
and the varactor is at its maximum value, 𝜔𝑚𝑖𝑛 =
𝐿1 (𝐶1 + 𝐶𝑚𝑎𝑥 + 𝑛𝑐𝑢 )
• The highest frequency occurs if the unit capacitors are switched out
1
and the varactor is at its minimum value, 𝜔𝑚𝑎𝑥 =
𝐿1 (𝐶1 + 𝐶𝑚𝑖𝑛 )

8
Discrete Tuning: Variation of Fine Tuning Range
• We expect Δωosc1 to be greater than Δ𝜔𝑜𝑠𝑐2
because, with nCu switched into the tanks, the
varactor sees a larger constant capacitance
1 𝐶𝑚𝑎𝑥 − 𝐶𝑚𝑖𝑛
∆𝜔𝑜𝑠𝑐1 =
𝐿1 𝐶1 2𝐶1
1 𝐶𝑚𝑎𝑥 − 𝐶𝑚𝑖𝑛
∆𝜔𝑜𝑠𝑐2 =
𝐿1 (𝐶1 + 𝑛𝐶𝑢 ) 2(𝐶1 + 𝑛𝐶𝑢 )
3
∆𝜔𝑜𝑠𝑐1 𝑛𝐶𝑢 2
= 1+
∆𝜔𝑜𝑠𝑐2 𝐶1
This variation in KVCO proves undesirable in PLL
design.

9
Issue of Discrete Tuning: Blind Zone

• The oscillator fails to cover the range between ω2 and ω3 for any
combination of fine and coarse controls.
• To avoid blind zones, each of the two consecutive tuning
characteristics must have some overlap.
• This precaution translates to smaller unit capacitors but a larger
number of them and hence a complex layout.
10
 Collector/
drain 𝑉
4
+
𝑌1 𝐺𝑖 𝐺𝑜
𝑌3 − 𝑔𝑚 𝑉1 − 𝑉2
𝑉2
Emitter/
𝑌2 Source

Feedback network BJT or FET

𝑌1 + 𝑌3 + 𝐺𝑖 − 𝑌1 + 𝐺𝑖 −𝑌3 0 𝑉1
− 𝑌1 + 𝑔𝑚 + 𝐺𝑖 𝑌1 + 𝑌2 + 𝐺𝑖 + 𝐺𝑜 + 𝑔𝑚 −𝑌2 −𝐺𝑜 𝑉2
=0
−𝑌3 −𝑌2 𝑌2 + 𝑌3 0 𝑉3
𝑔𝑚 − 𝐺𝑜 + 𝑔𝑚 0 𝐺𝑜 𝑉4

11
Oscillators Using a Common Emitter BJT
CE Configuration: 𝑉2 = 0
Feedback: V3 = V4
Output Admittance is Go=0
𝑌1 + 𝑌3 + 𝐺𝑖 −𝑌3 𝑉1
=0
𝑔𝑚 −𝑌3 𝑌2 + 𝑌3 𝑉
𝑌1 = 𝑗𝐵1, 𝑌2 = 𝑗𝐵2, and 𝑌3 = 𝑗𝐵3,
𝐺𝑖 + 𝑗 𝐵1 + 𝐵2 −𝑗𝐵3
=0
𝑔𝑚 − 𝑗𝐵3 −𝑗 𝐵2 + 𝐵3
1 1 1
+ + =0 𝑋1 + 𝑋2 + 𝑋3 = 0
𝐵1 𝐵2 𝐵3
𝑔𝑚
1 𝑔𝑚 1 𝑋1 = 𝑋
+ 1+ =0 𝐺𝑖 2
𝐵3 𝐺𝑖 𝐵2

12
Colpitts Oscillator
𝑉𝑐𝑐
1 1 𝐶1
𝑋1 = − ,𝑋 = − , 𝑎𝑛𝑑 𝑋3 = 𝜔0 𝐿3 𝑉𝑐𝑐
𝜔0 𝐶1 2 𝜔0 𝐶1 𝐿3
𝐶2
1 1 1
− + + 𝜔0 𝐿 3 = 0
𝜔0 𝐶1 𝐶2

1 𝐶1 + 𝐶2 𝐶2 𝑔𝑚
𝜔0 = , =
𝐿3 𝐶1 𝐶2 𝐶1 𝐺𝑖

13
Hartley Oscillator 𝑉𝑐𝑐
1 𝐿1 𝑉𝑐𝑐
𝑋1 = 𝜔0 𝐿1 , 𝑋2 = 𝜔0 𝐿2 , 𝑎𝑛𝑑 𝑋3 = − 𝐶3
𝜔0 𝐶3
𝐿2
1
𝜔0 𝐿1 + 𝐿2 − =0
𝜔0 𝐶3

1 1 𝐿1 𝑔𝑚
𝜔0 = , =
𝐶3 𝐿1 + 𝐿2 𝐿2 𝐺𝑖

14
Oscillators Using a Common Gate FET
• V1 = 0, and again V3 = V4
𝑌1 + 𝑌3 + 𝑔𝑚 + 𝐺𝑜 −(𝑌2 + 𝐺𝑜 ) 𝑉1
• Gi = 0 − 𝐺𝑜 + 𝑔𝑚 +𝑌2 𝑌2 + 𝑌3 + 𝐺𝑜 𝑉
=0

𝑔𝑚 + 𝐺𝑜 + 𝑗 𝐵1 + 𝐵2 𝐺𝑜 − 𝑗𝐵2
=0
−(𝐺𝑜 + 𝑔𝑚 ) − 𝑗𝐵3 𝐺𝑜 + 𝑗 𝐵2 + 𝐵3
1 1 1
+ + =0
𝐵1 𝐵2 𝐵3 𝑋1 + 𝑋2 + 𝑋3 = 0
𝐺𝑜 𝑔𝑚 𝐺𝑜 𝑋2 𝑔𝑚
+ + =0 =
𝐵3 𝐵1 𝐵1 𝑋1 𝐺0

1 𝐶1 + 𝐶2 𝐶1 𝑔𝑚
• For Colpitts Oscillator 𝜔0 = , =
𝐿3 𝐶1 𝐶2 𝐶2 𝐺𝑜

1 1 𝐿2 𝑔𝑚
• For Hartley Oscillator 𝜔0 =
𝐶3 𝐿1 + 𝐿2
, =
𝐿1 𝐺𝑜
15
Practical Considerations
Z3 = 1/Y3 = R + jωL3

1 1 1 𝐺𝑖 𝑅 1 1 1
𝜔0 = + + = + ,
𝐿3 𝐶1 𝐶2 𝐶1 𝐿3 𝐶1′ 𝐶2

𝑔𝑚
𝐶1 𝑅 1 + 𝐿3
𝐺𝑖
𝐶1′ = , = −
1 + 𝑅𝐺𝑖 𝐺𝑖 𝜔02 𝐶2 𝐶2 𝐶1

16
Microwave Oscillator
Noise
- e(t) + Noise
𝑎𝐿

𝑎𝐼𝑁
𝛤𝐼𝑁 𝛤𝐿
𝑎𝐿

Resonator Active device 𝑎𝐼𝑁

𝑍𝐿 𝑍𝐼𝑁

• Feedback Oscillator system

• Negative resistance oscillator

17
Oscillator Models

Input
Terminating
matching Transistor network
network

18
Negative resistance model
𝑖𝐿 𝑖𝐼𝑁
i(t) +
-
+ 𝑣𝐼𝑁
𝒀𝑳 (𝝎) 𝑉(𝑡) 𝒀𝑰𝑵 (𝑨)

𝒁𝑳 (𝝎) 𝒁𝑰𝑵 (𝑨) 𝑣𝐼𝑁

-
+ Passive circuit Active device
- Resonator 𝛤 𝛤𝐼𝑁 (negative resistance)
Passive circuit Active device 𝐿
Resonator 𝛤 𝛤𝐼𝑁 (negative resistance)
𝐿

𝑣𝐿 𝑡 + 𝑣𝐼𝑁 𝑡 = 𝑣𝑇 = 0 𝑖𝐿 𝑡 + 𝑖𝐼𝑁 𝑡 = 𝑖 𝑇 = 0

19
Feedback Model Gain block
Noise
- e(t) + Noise
𝑎𝐿

𝐴𝑣
𝑎𝐼𝑁
𝛤𝐼𝑁 𝛤𝐿
𝑎𝐿
Β(jω)

Freq selective network Resonator Active device 𝑎𝐼𝑁

𝑍𝐿 𝑍𝐼𝑁
• Transfer function : 𝑉𝑜𝑢𝑡 𝐴𝑣 (𝑗ω, 𝐴) 𝑎𝐿 𝛤𝐼𝑁 (ω, 𝐴)
= 𝑜𝑟 =
𝑉𝑖𝑛 (1 − 𝛽 𝑗ω)𝐴𝑣 𝑗ω, 𝐴 𝑎𝐼𝑁 (1 − 𝛤𝐿 ω)𝛤𝐼𝑁 ω, 𝐴

• In the absence of any input signal, for the

oscillation to sustain itself, the denominator
should be zero.
(𝛽 𝑗ω)𝐴𝑣 𝑗ω, 𝐴 = 0
• This is equivalent to the expression: (1 − 𝛤𝐿 ω)𝛤𝐼𝑁 ω, 𝐴 =0

20
Condition of oscillation
• The two conditions mentioned above can be satisfied only when ZIN (A0) = -ZL (𝜔0 )
where A and ∞ are the steady state amplitude and frequency
respectively.
• This can be further reduced to (𝛤𝐿 ω0)𝛤𝐼𝑁 ω0, 𝐴0 =1

• Note: However that for A <A0, i.e when amplitude is less than stable amplitude,
gain has to provides and so 𝑅𝑖𝑛 ω, 𝐴 > |𝑅𝐿 ω |

• Hence at startup when A = 0, 𝑅𝑖𝑛 ω, 0 > |𝑅𝐿 ω |

• Similarly for A > A0, the amplitude is more than the stable
amplitude and so attenuation has to be provided
so 𝑅𝑖𝑛 ω, 𝐴 < |𝑅𝐿 ω |

21
Graphical Analysis Im(Z)

• The intersecting angle measured clockwise

from the device line arrow direction (set by -
Zin (A ) for increasing A) to the line
impedance locus arrow direction (set by -
𝑍𝐿 (𝜔) for increasing 𝜔) must be less than
Re(Z)
180 for a stable point.

22
 RF Transceiver Design
Lecture 53
Oscillator Design - III

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
One Port Oscillator design

Input
Terminating
matching Transistor
network
network

Noise
- e(t) +
Noise
𝑎𝐿

𝑎𝐼𝑁

𝑎𝐿 𝛤𝐼𝑁 𝛤𝐿

Resonator Active device

𝑍𝐿 𝑍𝐼𝑁 𝑎𝐼𝑁

2
Power considerations: Series resonator
𝑅𝑖𝑛
+ 𝐿 0 𝐴𝑀
𝐴
0
𝑅𝐼𝑁 (𝐴) 𝑣𝐼𝑁
R
-
C
−𝑅

Establish:
• Condition for max oscillator power
• Operating point 𝐴𝑜 , ω0
• Stability of operating point
• Condition for starting oscillation

3
Condition for maximum power
𝑅𝑖𝑛 2𝐴𝑀
+ 𝐿 0 3 𝐴𝑀
𝐴
0
𝑅𝐼𝑁 (𝐴) 𝑣𝐼𝑁
R 𝑅
−
3
-
C
−𝑅

4
Operating point and stability
• Operating Point:
𝐴0 𝑅𝑜
𝑅𝐿 + 𝑅𝐼𝑁 𝐴𝑜 = 0 ⇒ 𝑅𝐿 = 𝑅0 1 − ⇒ 𝑅𝐿 =
𝐴𝑀 3
1 1
𝑋𝐿 𝜔0 + 𝑋𝐼𝑁 𝐴0 = 0 ⇒ 𝜔0 𝐿 − = 0 ⇒ 𝜔0 =
𝜔0 𝐶 𝐿𝐶
• The stability of the operating point for series resonator requires:
∂𝑅𝑖𝑛 (𝐴𝑜 ) ∂𝑋𝐿 (𝜔0 ) ∂𝑋𝑖𝑛 𝐴𝑜 ∂𝑅𝐿 𝜔0 ∂𝑅𝑖𝑛 𝐴𝑜 ∂𝑋𝐿 𝜔0
− =
∂A ∂𝜔 ∂A ∂𝜔 ∂A ∂𝜔
∂𝑅𝑖𝑛 (𝐴𝑜 ) 𝑅𝑜
= >0
∂A 𝐴𝑀
1
∂𝑋𝐿 𝜔0 ∂ 𝐿𝜔 − 1
𝜔𝐶
= |𝜔0 = 𝐿 + = 2𝐿 > 0
∂𝜔 ∂𝜔 𝜔02 𝐶

• Hence the operating point is stable

5
Design Methodology:
1. Use a potential unstable
Input
transistor at the freq. of matching Transistor
Terminating
oscillation. network
network
2. Design the termination network
to make |Γin|>1. Series or shunt
feedback can be used to increase
|Γin|
3. Design the load network to
resonate; that is let:
𝑋𝐿 𝜔0 = −𝑋𝐼𝑁 𝐴 = 0, 𝜔0
𝑅𝐿 𝜔0 = |𝑅𝐼𝑁 𝐴 = 0, 𝜔0 |/3

6
 Input
Terminating
matching Transistor
network
network

• At steady state we have 𝛤𝐿 𝛤𝐼𝑁 = 1 𝑎𝑛𝑑 𝑡ℎ𝑒𝑟𝑒𝑓𝑜𝑟𝑒 𝛤𝐿

1 𝑆21𝛤𝑇 𝑆12 −1 1−𝑆22 𝛤𝑇
𝛤𝐿 = = 𝑆11 + =
𝛤𝐼𝑁 1−𝑆22𝛤𝑇 𝑆11 −𝛥𝛤𝑇
Where,𝛥 = 𝑆11 𝑆22 − 𝑆12 𝑆21
1−𝑆11 𝛤𝐿
• Solving for 𝛤𝑇 : 𝛤𝑇 = 𝑆 −𝛥𝛤 =1/𝛤𝑜𝑢𝑡 => This implies 𝛤𝐿 𝛤𝑜𝑢𝑡 = 1
22 𝐿
• Which prove that i/p and terminating networks are equivalent
and oscillating simultaneously.

7
Example 2

• Convert S parameter

• Find the Output stability circle

8
• Find unstable Γ𝐿 :

• Find Γ𝑖𝑛

• Find Zs:

9
10
Phase Noise
Noiseless Magic Box

vn2 2
𝛥f 2kT 𝜔𝑜
𝐿 𝛥𝜔 = 10. log 2 = 10. log .
vsig Psig 2𝑄𝛥𝜔
2kT 𝐹 𝜔𝑜 2 Δ𝜔1/𝑓3
= 10. log . 1+ 1+
Psig 2𝑄𝛥𝜔 Δ𝜔

11
12
 RF Transceiver Design
Lecture 54
Oscillator Design - IV

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
Phase Noise

Noiseless Magic Box

vn2 2
𝛥f 2kT 𝜔𝑜
𝐿 𝛥𝜔 = 10. log 2 = 10. log .
vsig Psig 2𝑄𝛥𝜔

2
3
Phase Noise
Noiseless Magic Box

vn2 2
𝛥f 2kT 𝜔𝑜
𝐿 𝛥𝜔 = 10. log 2 = 10. log .
vsig Psig 2𝑄𝛥𝜔
2kT 𝐹 𝜔𝑜 2 Δ𝜔1/𝑓3
= 10. log . 1+ 1+
Psig 2𝑄𝛥𝜔 Δ𝜔

4
Issues with Lessons Model
• Increase in Q -> Reduces the phase noise
• F-> empirical Parameter is not defined
• Improvement in Q with Active components leads to increase in F
• Invalid Assumption in the Model

𝑑𝐵𝑚 2kT 𝐹 𝜔𝑜 2 Δ𝜔1/𝑓3

ℒ = 10. log . 1+ 1+
𝐻𝑧 Psig 2𝑄𝛥𝜔 Δ𝜔

5
Roles Of Linearity And Time Variation In Phase Noise
• Nonlinearity is clearly a fundamental property of all real oscillators, as it is necessary for amplitude
limiting.
• This results in a single-frequency sinusoidal disturbance injected into an oscillator, giving rise to two
equal-amplitude sidebands that are symmetrically disposed about the carrier
• LTI systems cannot perform frequency translation, however, nonlinear systems can do.
• Hence, nonlinear mixing has often been proposed to explain phase noise.
• An important insight is that disturbances are perturbations superimposed on the main oscillation. They
will always be much smaller in magnitude than the carrier.
• Doubling the disturbance can double the phase disturbance.
• Linearity would therefore appear to be a reasonable assumption
regarding the noise-to-phase transfer function.
• In contrast with linearity, the assumption of time invariance is less
obviously defensible.
• We can demonstrate that oscillators are fundamentally time-varying
systems.

6
Effect of Impulse Current on LC Tank
∆V = ∆Q/C
∆V
∆V

• The amount of phase disturbance for a given injected impulse depends on

when the injection occurs; time invariance thus fails to hold.
• An oscillator is a linear yet (periodically) time-varying (LTV) system.

7
• linearity -> noise-to-phase conversion

• LTI impulse response is function of two arguments,

▪ observation time t
▪ excitation time τ.
• The impulse response may be written as:
𝛤 𝜔𝑜 𝜏
ℎ∅ 𝑡, 𝜏 = 𝑢 𝑡−𝜏 .
𝑞𝑚𝑎𝑥
• Where, u(t) – unit step function, LC Oscillator Ring Oscillator
qmax – The max charge displacement across the capacitor,
𝛤 𝑥 – Impulsive Sensitivity Function (ISF).
• The ISF encodes information about the sensitivity of the oscillator to an
impulse injected at phase ω0t.
• In the LC oscillator, 𝛤 𝑥 → maximum value near the zero crossings
𝛤 𝑥 → zero value at the maxima of the oscillation
waveform.

8
• The excess phase due to an arbitrary noise
signal through the superposition integral.
X
+∞ 𝑡
1
∅ 𝑡 =න ℎ∅ 𝑡, 𝜏 𝑖 𝜏 𝑑𝜏 = න ᴦ 𝜔0 𝜏 𝑖 𝜏 𝑑𝜏
−∞ 𝑞𝑚𝑎𝑥 −∞
X

X
• The ISF is periodic and therefore expressible as
a Fourier series:
X

∞
𝑐𝑜
ᴦ 𝜔0 𝜏 = + ෍ 𝑐𝑛 cos(𝑛𝜔0 𝜏 + 𝜃𝑛 )
2
𝑛=1
1 𝑐𝑜 𝑡 𝑡
∅ 𝑡 = ‫𝑖 ׬‬ 𝜏 𝑑𝜏 + σ∞
𝑛=1 ‫׬‬−∞ 𝑖(𝜏) cos 𝑛𝜔𝑜 𝜏 𝑑𝜏
𝑞𝑚𝑎𝑥 2 −∞

9
• A sinusoidal current
𝑖 𝑡 = 𝐼𝑚 𝑐𝑜𝑠 𝑚𝜔𝑜 + ∆𝜔 𝑡
𝑤ℎ𝑒𝑟𝑒 ∆ ≪ 𝜔𝑜
𝐼𝑚 𝑐𝑚 sin(∆𝜔𝑡)
∅ 𝑡 ≈
2𝑞𝑚𝑎𝑥 ∆𝜔

• A phase-to-voltage converter;
𝑣𝑜𝑢𝑡 = 𝑐𝑜𝑠 𝜔𝑜 𝑡 + ∅ 𝑡
• Performing this phase-to-voltage conversion and assuming “small” amplitude disturbances,
we find that the single-tone injection results in two equal-power sidebands symmetrically
disposed about the carrier:
2
𝐼𝑚 𝑐𝑚
𝑃𝑆𝐵𝐶 ∆𝜔 ≈ 10. log
4𝑞𝑚𝑎𝑥 ∆𝜔
• This result may be extended to the general case of a white noise
source: 𝑖ഥ𝑛2 ∞ 2
σ 𝑐
∆𝑓 𝑚=0 𝑚
𝑃𝑆𝐵𝐶 (∆𝜔) ≈ 10. 𝑙𝑜𝑔 2
4𝑞𝑚𝑎𝑥 ∆𝜔 2
10
 • Components of noise near integer multiples of the
carrier frequency all fold into noise near the carrier
itself.
• It is clear from Figure that minimizing the various
coefficients cn (by minimizing the ISF) will minimize
the phase noise.
• By using Parseval’s theorem :
1 2𝜋
σ∞ 2
𝑚=0 𝑐𝑚 =𝜋 ‫׬‬0 ᴦ(𝑥) 2
𝑑𝑥 = 2ᴦ2𝑟𝑚𝑠

• The spectrum in the 1/𝑓 2 region may be expressed

as:

𝑖2
𝑛 ᴦ2
∆𝑓 𝑟𝑚𝑠
L ∆𝜔 = 10𝑙𝑜𝑔 2
2𝑞𝑚𝑎𝑥 ∆𝜔2

11
• The upconversion of 1/f noise into close-in phase noise.
• Noise near the carrier is particularly important in communication systems with narrow channel spacings.
• The allowable channel spacings are frequently constrained by the achievable phase noise.
• Unfortunately, it is impossible to predict close-in phase noise correctly with LTI models.
• This problem disappears if the new model is used. Specifically, assume that the current noise behaves
as follows in the 1/f region:
2 2 𝜔1Τ𝑓
𝑖𝑛, 1 Τ𝑓 = 𝑖 𝑛 . ∆𝜔
Where 𝜔1Τ𝑓 is the 1/f corner frequency . Using Eqn.27, we obtain the following expression for noise in
the 1ൗ𝑓3 region
𝑖2
𝑛 𝑐2
∆𝑓 0 𝜔1Τ𝑓
L ∆𝜔 = 10. 𝑙𝑜𝑔 2
8𝑞𝑚𝑎𝑥 ∆𝜔2
.
∆𝜔

1
ൗ𝑓3 corner frequency is then

𝑐02 ᴦ𝑑𝑐 2
∆𝜔1ൗ = 𝜔1Τ𝑓 . 4ᴦ2 = 𝜔1Τ𝑓 .
𝑓3 𝑟𝑚𝑠 ᴦ𝑟𝑚𝑠

12
Reciprocal Mixing
The maximum allowable phase noise in order to achieve an adjacent channel rejection (or
selectivity) of S dB (S ≥ 0) is given by
𝑑𝐵𝑐
𝐿 𝑓𝑚 = 𝐶 𝑑𝐵𝑚 − 𝑆 𝑑𝐵 − 𝐼 𝑑𝐵𝑚 − 10 log 𝐵 ,
𝐻𝑧

Desired
Desired LO
signal
Unwanted Phase
signal noise
Noisy LO
f
IF IF
IF f0

13
ℒ 𝑓𝑚 = 𝐶 𝑑𝐵𝑚 − 𝑆 𝑑𝐵 − 𝐼 𝑑𝐵𝑚 − 10 log 𝐵
= −99 𝑑𝐵𝑚 − 9 𝑑𝐵 − 𝐼 𝑑𝐵𝑚 − 10log(2 × 105 )

Freq Offset Interfering Signal Phase noise

𝒇𝒎 (𝑴𝑯𝒛) (dBm) (dBc/Hz)
3.0 -23 -138
1.6 -33 -128
0.6 -43 -118

14
References:
• Hajimiri, Ali, and Thomas H. Lee. "A general theory of phase noise in electrical oscillators."
IEEE journal of solid-state circuits 33.2 (1998): 179-194.
• Lee, Thomas H. The design of CMOS radio-frequency integrated circuits. Cambridge university
press, 2003.
• Razavi, Behzad. RF microelectronics. Vol. 2. New York: Prentice hall, 2012.
• Pozar, David M. Microwave engineering. John wiley & sons, 2011.

15
 RF Transceiver Design
Lecture 55
Power Amplifier Design - I

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
 PA Specification
• Gain (Gain Flatness)
• Power consumption
• Linearity
• Signal peak to mean ratio
• Bandwidth
• Frequency band (transmit and receive)
• Power delivered
• Permissible in-band emission
• Permissible out-of-band emission
• Stability over VSWR
• Ability to transmit into unknown/varying load Efficiency
• Minimize any lose in the form of heat & noise Size
• Find the minimum size as much as possible

2
Outline
Basic PA Classes PA Design Examples
• Cascode PAs
• Class A PAs
• Positive-Feedback PAs
• Class B PAs
• PAs with Power Combining
• Class C PAs
• Polar Modulation PAs
High Efficiency PAs • Outphasing PAs
Linearization Techniques
• Class A PAs with Harmonic
Enhancement • Feedforward
• Class E PAs • Cartesian Feedback
• Class F PAs • Predistortion
• Polar Modulation
• Outphasing
• Doherty PA

3
General Consideration

4
The Trade-Off between the Output Power and the Voltage Swing

• For a common-source (or common-emitter) stage to drive the load directly,

a supply voltage greater than Vpp is required.
• If the load is realized as an inductor, the drain ac voltage exceeds VDD, even
reaching 2VDD (or higher). But the maximum drain-source voltage
experienced by M1 is still at least 20 V if the stage must deliver 1 W to a
50-Ω load.
• It can be proven that the product of the breakdown voltage and fT of
silicon devices is around 200 GHz .

5
 Interposing a Matching Network
• In order to reduce the peak voltage experienced by the output transistor, a “matching
network” is interposed between the PA and the load.
• This network transforms the load resistance to a lower value, RT , so that smaller voltage
swings still deliver the required power.

The above PA must deliver 1 W to RL = 50 Ω with a supply voltage

of 1 V. Estimate the value of RT.

6
The peak-to-peak voltage swing, Vpp, at the drain of M1 is approximately equal to 2 V. Since:
2
1 𝑉𝑝𝑝 1
𝑃𝑜𝑢𝑡 = = 1𝑊
2 2 𝑅𝑇
1
= 𝑅𝑇 = Ω
2
• The matching network must therefore transform RL down by a factor of 100.
• Figure above shows an example, where a lossless transformer
having a turns ratio of 1:10 converts a 2-Vpp swing at the drain of
M1 to a 20-Vpp swing across RL.

7
Effect of High Currents
• Large Output current -> Higher width Transistor -> the design of the preceding stage difficult.
• Introducing Driver stage.

Driver Output
Stage Stage Matching
Network
RL
LO
• Another issue arising from the high ac currents in PAs relates to
the package parasitic.
• The large currents can also lead to a high loss in the matching
network.

8
Efficiency
The “drain efficiency” (for FET implementations) or “collector efficiency” (for bipolar implementations) is
defined as: 𝑃 𝐿
ƞ=
𝑃𝑠𝑢𝑝𝑝
where PL -> the average power delivered to the load, and Psupp -> the average power drawn from the
supply voltage. “Power-added efficiency”, PAE, defined as
𝑃𝐿 −𝑃𝑖𝑛 where Pin is the average input power
PAE=
𝑃𝑠𝑢𝑝𝑝
PAE of the CS stage.
• PAE = η , At low to moderate frequencies, the input impedance is
capacitive and hence the average input power is zero.
• At high frequencies, input port has real part in Zin, -> Draw some power.
• For stan-alone mixer PAE < η due to 50 ohm impedance matching at
input.

9
Linearity: PA Characterization Full Power
Full Power Level
6dB Level

20𝑙𝑜𝑔𝐴𝑜𝑢𝑡
1dB
IM3

𝐴𝑖𝑛 , 1𝑑𝐵 20𝑙𝑜𝑔𝐴𝑖𝑛

A more rigorous characterization: suppose the modulated input is of the form:
• PA nonlinearity leads to two effects:
▪ High adjacent channel power as a result of spectral regrowth
▪ Amplitude compression.
• The PA nonlinearity – the modulation scheme of interest.
• Circuit Simulation is longer with modulated signal.
• Generic Test:
1. Intermodulation
2. compression
10
Single Ended PAs (Ⅰ)
• Advantages of single-ended PAs: the antenna is typically single-ended, and single-ended RF circuits are
much simpler to test than their differential counterparts.
• Drawback No.1: they “waste” half of the transmitter voltage gain because they sense only one output of
the up converter.
Balun

I PA I
Up converter Up converter
Q Q

• This issue can be alleviated by interposing a balun between the up

converter and the PA. But balun introduces its own loss.

11
Single Ended PAs (Ⅱ)
• Drawback No.2 stems from the very large transient currents that they pull from the supply
Bond
to the ground. On-chip VDD Wire
External VDD
𝐿𝐷 𝐿𝐵1
Matching
Network
𝑀1 RL

On-chip GND
𝐿𝐵2
Feedback Bond
Wire
Path
• LB1 – change the resonance or impedance transformation
properties. Signal feedback to the preceding stages.
• LB2 – degenerates the output stage and introduces feedback.

12
Differential PAs
Balun

Up converter

• A differential realization -> less sensitivity to LB1 and LB2 and creating less
feedback. The degeneration issue is also relaxed considerably.

• The PA must still drive a single-ended antenna in most cases.

• A Balun is must now be inserted between the PA and the antenna.

13
Example of Efficiency and Loss in Balun Design

14
 RF Transceiver Design
Lecture 56
Power Amplifier Design - II

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
Classification of Power Amplifiers

2
Class A PAs 𝐼𝐷𝑆

𝐼𝐷𝐶

𝑡
𝑉𝐷𝑆

Lossless Matching 𝑉𝑃
𝑉𝐷𝐷

• The drain voltage is: 𝑉𝐷𝑆 = 𝑉𝐷𝐷 + 𝑉𝑝 sin 𝜔𝑜 𝑡

𝑉
• Given the load resistance RL, the drain current is: 𝐼𝐷𝑆 = 𝐼𝐷𝐶 + 𝑃 sin 𝜔𝑜 𝑡
𝑅𝐿
• Assuming a lossless matching network, the efficiency then is:
𝑉𝑃2
𝑃𝑂𝑈𝑇 2𝑅𝐿
𝑉𝑃2 𝜂= =
𝑃𝐼𝑁 𝐼𝐷𝐶 𝑉𝐷𝐷
2𝑅𝐿 𝑉𝑝 1
𝜂𝑀𝐴𝑋 = = = = 50%
𝑉𝑃
𝑉𝐷𝐷 2𝑉𝐷𝐷 2
𝑅𝐿

3
Efficiency in Different Scaling Scenarios
(1)The supply voltage and bias current (2)The supply voltage remains unchanged but the
remain at the levels necessary for full bias current is reduced in proportion to the output
output power and only the input signal voltage swing: 𝑉 2 Τ 2𝑅 𝑝 𝑉 𝑖𝑛 𝑝
swing is reduced: 𝑉𝑝2 Τ 2𝑅𝐿 𝑉𝑝 2 ƞ2 = =
ƞ1 = = (𝑉𝑝 Τ𝑅𝑖𝑛 ) 𝑉𝐷𝐷 2𝑉𝐷𝐷
𝑉𝐷𝐷 2 Τ 𝑅𝐿 2𝑉𝐷𝐷 2

Supply Voltage and

ƞ Ƞ
Bias Current Scaling 3
3)Both the supply voltage and the bias 50%
current are reduced in proportion to the Ƞ2

output voltage swing: Ƞ1

Ƞ3 = 50% Input Swing

Scaling
𝑉𝐷𝐷 𝑉𝑝

4
 𝐼𝐷𝑆
Class B PAs
𝐼𝑃
LCM
𝑡
𝑉𝐷𝑆
𝑉𝑃
𝑉𝐷𝐷

𝑡
𝐼𝑃 𝐼𝑃 2𝐼𝑃 𝑰𝑷
𝐼𝐷𝑆 = + sin 𝜔𝑜 𝑡 − cos 2𝜔𝑜 𝑡 + ⋯ : DC term
𝜋 2 3𝜋 𝝅

• When the fundamental component of the current reaches its

𝐼 𝑉
peak, 𝑃 , the total current sank from the load is 𝑃 , assuming a
2 𝑅𝐿
𝐼𝑃 𝑉𝑃
peak swing of A at the drain. Hence =
2 𝑅𝐿
𝑉𝑃2
𝜋
𝑃𝑂𝑈𝑇 2𝑅𝐿𝑉𝑃
𝑇ℎ𝑒 𝑒𝑓𝑓𝑖𝑐𝑖𝑒𝑛𝑐𝑦 𝜂 = = =4
𝑃𝐼𝑁 𝐼𝑃
𝑉𝐷𝐷 𝑉𝐷𝐷
𝜋

5
 𝑉𝐺𝑆
Class C PAs 𝑉𝑃
𝑉𝑇𝐻
• In Class C PAs, the conduction angle is further reduced,
τ
and possibly have a better efficiency than class B
• Assuming a conduction duration of τ < T/2, where T is 𝑡
𝐼𝐷𝑆
one cycle, we can see that the device turns on and off at
𝑇
the two points: 𝑡𝑂𝑁/𝑂𝐹𝐹 = ∓ τ/2
4
𝑉 𝑡
𝑇 cos−1 𝑇𝐻
𝑉𝑃
Where, 𝜏 = 𝑉𝑃
𝜋 𝑉𝐷𝐷
𝜋 𝑉
• The conduction angle 𝜃 = 𝜏 = cos −1 𝑇𝐻
𝑇 𝑉𝑃 𝑡
• During the conduction, the drain current: 𝐼𝐷𝑆 = 𝐼𝑃 − cos 𝜃 + sin 𝜃 𝑡𝑂𝑁 ≤ 𝑡 ≤ 𝑡𝑂𝐹𝐹
𝐼𝑃 sin 2𝜃
• For 𝑡 = 𝑡𝑂𝑁/𝑂𝐹𝐹 , 𝐼𝐷𝑆 = 0, 𝐼𝐷𝑆 = sin 𝜃 − 𝜃 cos 𝜃 + 𝜃 − sin 𝜔𝑜 𝑡 +. .
𝜋 2
𝑉𝑃
𝑅𝐿
• To get the swing Vp at RL, during the conduction we must have: 𝐼𝑃 = 𝜋 sin 2𝜃
𝜃− 2
𝑉𝑃2 sin 2𝜃 sin 2𝜃
𝑃𝑂𝑈𝑇 2𝑅𝐿 𝜃− 2 𝑉𝑃 𝜃− 2
𝜂= = = = 𝑖𝑓 𝑉𝑃 = 𝑉𝐷𝐷
𝑃𝐼𝑁 𝐼𝑃 sin 𝜃 − 𝜃 cos 𝜃 2𝑉𝐷𝐷 2(sin 𝜃 − 𝜃 cos 𝜃)
sin 𝜃 − 𝜃 cos 𝜃 𝑉𝐷𝐷
𝜋
6
Efficiency of Class C Power Amplifiers

Class C
Class B

sin 2𝜃 Class A
𝜃−
𝜂= 2
2(sin 𝜃 − 𝜃 cos 𝜃)

𝜃 − 𝑠𝑖𝑛𝜃
𝑃𝑜𝑢𝑡 ∝
𝜃
1 − 𝑐𝑜𝑠
2
• Efficiency of 100% as 𝜃 approaches zero.
• Pout falls to zero as 𝜃approaches zero.

7
High-Efficiency Power Amplifiers

8
High-Efficiency Power Amplifiers: Class A Stage with Harmonic Enhancement
𝒔𝒊𝒏𝝎𝟎
• Suppose the matching network is designed such
that its input impedance is low at the
fundamental and high at the second harmonic. 𝑡
• The average power consumed by the output 𝟎. 𝟑𝐬𝐢𝐧(𝟐𝝎𝟎 + 𝟗𝟎° )
transistor decreases and the efficiency increases.
𝑡
𝒔𝒊𝒏𝝎𝟎 +𝟎. 𝟑𝒔𝒊𝒏(𝟐𝝎𝟎 + 𝟗𝟎° )

VDD
RFC 𝑡

𝑉𝑋

Z1
𝑡
9
Class D PAs
VDD
𝑡

VDD VDD 𝑡

2
𝑉 𝑅
𝜋 𝐷𝐷 𝐿
The load voltage peak amplitude: 𝑉𝐿𝑜𝑎𝑑 =
𝑅𝐿 +𝑟𝐿 +𝑅𝑆𝑊
2
𝑉
𝜋 𝐷𝐷
The load current amplitude: 𝐼𝐿𝑜𝑎𝑑 =
𝑅𝐿 +𝑟𝐿 +𝑅𝑆𝑊
𝑉𝐿𝑜𝑎𝑑 𝐼𝐿𝑜𝑎𝑑
𝑃𝑂𝑈𝑇 2 𝑅𝐿
Efficiency 𝜂 = = =
𝑃𝐼𝑁 𝐼𝐷𝐶 𝑉𝐷𝐷 𝑅𝐿 +𝑟𝐿 +𝑅𝑆𝑊

10
Class E Stage: Revisiting Output Stage with Switching Transistor

• Class E stages are nonlinear amplifiers that

achieve efficiencies approaching 100% while
VDD VDD
delivering full power, a remarkable advantage
over class C circuits.

• “Switching Power Amplifier,” such a topology

achieves a high efficiency if : VDS
(1) M1 sustains a small voltage when it carries
current,
(2) M1 carries a small current when it sustains a
finite voltage
(3) the transition times between the on and off
states are minimized

11
Class E PAs
• The main challenge of class D PAs is to minimize: the voltage VDD
across the switch when it carries current, and the current
through it when there exists a voltage across.
• These conditions imply fast switching, which may not be
feasible at high frequencies.
• If the switch voltage and current overlap, as they do in
practice due to finite rise and fall times, the efficiency
degradation may be substantial.
• This may be avoided by proper design of the matching
network, which adds enough degrees of freedom to ensure
that there is no appreciable time duration that voltage and
current simultaneously exist

12
Class F Power Amplifiers

𝑉𝑋

• If in the generic switching stage the load network provides a

high termination impedance at the second or third harmonics,
the voltage waveform across the switch exhibits sharper edges
than a sinusoid, thereby reducing the power loss in the
transistor. Such a circuit is called a class F stage.

13
 RF Transceiver Design
Lecture 57
Power Amplifier Design - III

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
Cascode Output Stages
𝑉𝑋 𝑉𝐷𝐷
• One can choose VDD equal to half of the
maximum tolerable voltage of the Matching
Network 𝑡
transistor, but with two penalties:
✓ (a) the lower headroom limits the 𝑉𝑏 − 𝑉𝑇𝐻
linear voltage range of the circuit 𝑉𝑌
✓ (b) the proportionally higher
output current (for a given output 𝑡
power) leads to a greater loss in
the output matching network,
reducing the efficiency.

• The cascode device “shields” the input transistor as Vx rises, keeping the
drain-source voltage of M1 less than Vb- VTH2.

2
Linearity of Cascode Stages

𝑉𝑜 𝑉𝑜

𝑉𝑚 𝑉𝑚

From (a), 𝑉𝐷𝐷 − 𝑉𝑃,𝑐𝑎𝑠 − 𝑉𝐷𝑆2 + 𝑉𝑇𝐻 = 𝑉𝑜 + 𝑉𝑚

From (b), 𝑉𝐷𝐷 − 𝑉𝑃,𝑐𝑎𝑠 + 𝑉𝑇𝐻1 = 𝑉𝑜 + 𝑉𝑚

It follows that, 𝑉𝑃,𝐶𝑆 = 𝑉𝑃,𝑐𝑎𝑠 + 𝑉𝐷𝑆2

• The CS stage remains linear across a wider output voltage range than the
cascode circuit does. At low supply voltages, cascode output stages offer
only a slight voltage swing advantage over their CS counterparts, but at
the cost of efficiency and linearity.
3
Example of Stability of Cascode Stages
• Consider the two-stage PA
shown below. If the output
stage exhibits a negative
input resistance, how can + +
the cascade be designed to - -
remain stable? Rin Rin Rin

• Drawing the Thevenin equivalent of the first stage as shown in (b), we observe that instability can be avoided if

𝑅𝑒 𝑍𝑜𝑢𝑡1 + 𝑅𝑖𝑛 > 0

• so that VThev does not absorb energy from the circuit. If Zout is modeled by a parallel
tank, then
𝑅𝑒 𝑍𝑜𝑢𝑡1 = 𝑅𝑝

Thus, we require that 𝑅𝑝 +𝑅𝑖𝑛 > 0

• This condition must hold at all frequencies and for a certain range of Rin. For example,
if a cellphone user wraps his/her hand around the antenna, RL and hence Rin change.

4
Large-Signal Impedance Matching: the Simplistic Model and the
Practical Model
• This simplistic model assumed that the output
matching network simply transforms RL to a
lower value.
Matching
Network
• In practice, the situation is more complex: a
nonlinear complex output impedance must be
matched to a linear load.

Matching
Network

5
Large-Signal Impedance Matching: Starting from a Simple
Case
• Let us compute the power
delivered by M1 to RL, PRL, and
that consumed by the transistor’s
output resistance, Pro1. We have
𝐼𝑝2 𝑅𝐿 𝑟𝑜1
2
𝐼𝑝2 𝑅𝐿 𝑟𝑜1
2
𝑃𝑅𝐿 = 2 𝑃𝑟01 =
2 𝑅𝐿 + 𝑟𝑜1 2 𝑅𝐿 + 𝑟𝑜1 2

• For maximum power transfer, RL is chosen equal to rO1, yielding PRL = Pro1.
𝑃𝑅𝐿 𝑟𝑜1
=
𝑃𝑟01 𝑅𝐿

• The relation above shows that reducing RL minimizes the relative power
consumed by the transistor.

6
Load-Pull Measurement
• We vary Z1 such that the power
delivered to RL remains constant
and equal to P1, thus obtaining the
Tuner
contour depicted above.
• Next, we seek those values of Z1
that yield a higher output power,
P2, arriving at another contour.
Tuner
Tuner

• These “load-pull” measurements can be repeated for increasing

power levels, eventually arriving at an optimum impedance, Zopt,
for the maximum output power.

7
Basic Linearization Techniques

8
Feedforward
• The “feedforward” architecture computes the error and, with proper scaling, subtracts it from the output waveform.

𝐴𝑉 + 𝐴𝑉 ∆2 +

𝑉𝐷
𝑉𝑁 = 𝑉𝑖𝑛 +
𝐴𝑣
+ 𝐴𝑉 ∆1 + 𝐴𝑉

Feedforward suffers from several shortcomings that have made its use in integrated PA
design difficult.
(1) the analog delay elements introduce loss if they are passive or distortion if
they are active.
(2) the loss of the output subtractor degrades the efficiency
(3) the linearity improvement depends on the gain and phase matching of the
signals sensed by each subtractor

9
Cartesian Feedback +
X
+ -
X +
- +
X
-

LPF X
LPF X
LPF X

• If the PA output is downconverted and compared with the baseband

signal, an error term proportional to the nonlinearity of the transmitter
chain can be created. With quadrature down conversion, this is called
“Cartesian feedback”.
• Cartesian feedback avoids the output subtractor and is much less
sensitive to path mismatches, but requires some linearity in the PA.

10
Predistortion
If the PA nonlinear characteristics are known, it is possible to “predistort” the input waveform in such a manner that, after
experiencing the PA nonlinearity, it resembles the ideal waveform.

𝑃𝑟𝑒𝑑𝑖𝑠𝑡𝑜𝑟 𝐷𝐴𝐶 X
𝑔−1 (𝑥)
+

𝑃𝑟𝑒𝑑𝑖𝑠𝑡𝑜𝑟 𝐷𝐴𝐶 X

Three drawbacks:
(1) the performance degrades if the PA nonlinearity varies with process,
temperature, and load impedance while the predistorter does not track
these changes.
(2) the PA cannot be arbitrarily nonlinear as no amount of predistortion can
correct for an abrupt nonlinearity
(3) variations in the antenna impedance somewhat affect the PA nonlinearity,
but predistortion provides a fixed correction.

11
Envelope Feedback
In order to reduce envelope nonlinearity (i.e., AM/AM conversion) of PAs, it is possible to apply negative
feedback only to the envelope of the signal.

𝛼
Envelope Envelope
Detector Detector

How does the distortion of the envelope detectors

affect the performance of the above system?
• If the two detectors remain identical, their distortion does not affect the
performance because the feedback loop still yields VA ≈ VB and hence VD ≈
Vin. This property proves greatly helpful here as typical envelope detectors
suffer from nonlinearity.

12
Envelope Detection (Ⅰ)
Mixer as envelope detector:
A mixer can raise the input to the power of two, yielding from X LPF
Vin(t) = Venv (t) cos[ω0t + ϕ(t)] the following output
2
𝑉𝑜𝑢𝑡 𝑡 = 𝛽𝑉𝑒𝑛𝑣 𝑡 𝑐𝑜𝑠 2 𝜔0𝑡 + 𝜙 𝑡
2
1+cos [2𝜔0𝑡 + 2𝜙 𝑡 ]
= 𝛽𝑉𝑒𝑛𝑣 𝑡
2

Source follower as envelope detector: The slew rate is chosen much less than the carrier slew rate so that
the output tracks the envelope but not the carrier.

𝑉𝑖𝑛

13
Envelope Detection (Ⅱ) X LPF
• Limiter and mixer as envelope detector:
Denoting the signal at B by V0 cos[ω0t + ϕ(t)], we Limiter
have
2
𝑉𝑜𝑢𝑡 𝑡 = 𝛽𝑉𝑜 𝑉𝑒𝑛𝑣 𝑡 𝑐𝑜𝑠 2 𝜔0𝑡 + 𝜙 𝑡
2
1+cos [2𝜔0𝑡 + 2𝜙 𝑡 ]
= 𝛽𝑉𝑜 𝑉𝑒𝑛𝑣 𝑡
2

• In practice, the limiter may

require two or more cascaded
diff. pairs.

14
Polar Modulation: Basic Idea
Any bandpass signal can be represented as Vin(t) = Venv (t) cos[ω0t + ϕ(t)], we can decompose Vin(t) into an
envelope signal and a phase signal, amplify each separately, and combine the results at the end.

Envelope
Detector
t
Limiter

• This approach is called polar modulation because it processes the signal

in the form of a magnitude (envelope) component and a phase
component.

15
Outphasing: Basic Idea
• It is possible to avoid envelope variations in a PA by decomposing a variable-envelope signal into two constant-
envelope waveforms.
• A bandpass signal Vin(t) = Venv (t) cos[ω0t+ϕ(t)] can be expressed as V0
where 𝑉1 𝑡 =sin 𝜔𝑜 𝑡 + ∅ 𝑡 + 𝜃(𝑡)
𝑉𝑖𝑛 𝑡 = Venv 𝑡 cos 𝜔𝑜 𝑡 + ∅ 𝑡 2
= 𝑉1 𝑡 + 𝑉2 (𝑡) V0
𝑉2 𝑡 = − sin 𝜔𝑜 𝑡 + ∅ 𝑡 + 𝜃(𝑡)
2
𝑉𝑒𝑛𝑣 𝑡
𝜃 𝑡 = sin−1
𝑉𝑜

Signal
Separator +

𝑉𝑒𝑛𝑣 𝑡
VI (𝑡) =
𝑉1 𝑡 = VI cos 𝜔𝑜 𝑡 + ∅ 𝑡 + 𝑉𝑄 sin 𝜔𝑜 𝑡 + ∅ 𝑡 2
where
V2 𝑡 = −VI cos 𝜔𝑜 𝑡 + ∅ 𝑡 + 𝑉𝑄 sin 𝜔𝑜 𝑡 + ∅ 𝑡 2
𝑉𝑒𝑛𝑣 𝑡
VQ 𝑡 = 𝑉𝑜2 −
2

16
 RF Transceiver Design
Lecture 58
Basics of Phase Locked Loop - I

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
Phase-Locked Loops
➢ Order and Type
• Basic Concepts
• Type-I PLLs
• Type-II PLLs
➢ Frequency Ranges
➢ Loop Bandwidth
➢ Phase Noise
➢ Transient response
➢ Steady-state errors
➢ Basic Parameters: Power, supply, amplitude
➢ Spectrum Purity at Output

2
Phase Detector

Phase
Detector

• A PD is a circuit that senses two periodic inputs and produces an output whose average
value is proportional to the difference between the phases of the inputs
• The input/output characteristic of the PD is ideally a straight line,
• with a slope called the “gain” and denoted by KPD

3
Example of Phase Detector
Must the two periodic inputs to a PD have equal frequencies?

4
 𝑋1(𝑡)
𝑋1(𝑡)
𝑋2(𝑡)
𝑋𝑜𝑢𝑡(𝑡) ∆∅
𝑋2(𝑡)

𝑋𝑜𝑢𝑡(𝑡)

• We seek a circuit whose average output is

proportional to the input phase difference.
• An Exclusive-OR (XOR) gate can serve this
purpose. It generates pulses whose width is
equal to Δϕ

5
Type-I PLLs: Alignment of a VCO’s Phase

(1)change the frequency of the VCO

(2)allow the VCO to accumulate phase faster(or more slowly) than
the reference so that the phase error vanishes
(3)change the frequency back to its initial value

6
Simple PLL and Loop Filter

PD VCO PD LPF VCO

➢ Negative feedback loop: if the “loop gain” is sufficiently high, the circuit minimizes the
input error.
➢ The PD produces repetitive pulses at its output, modulating the VCO frequency and
generating large sidebands.
➢ Interpose a low-pass filter between the PD and
the VCO to suppress these pulses.

7
A student reasons that the negative feedback loop must force the phase error to zero, in
which case the PD generates no pulses and the VCO is not disturbed. Thus, a low-pass filter is
not necessary.

As explained later, this feedback system suffers from a finite loop gain, exhibiting a finite
phase error in the steady state. Even PLLs having an infinite loop gain contain nonidealities
that disturb Vcont

8
Simple PLL: Phase Locking

+
PLL
-

∅𝑜𝑢𝑡 − ∅𝑖𝑛 = 𝑐𝑜𝑛𝑠𝑡𝑎𝑛𝑡

𝑑∅𝑜𝑢𝑡 𝑑∅𝑖𝑛
=
𝑑𝑡 𝑑𝑡
➢ We say the loop is “locked” if ϕout(t)-ϕin(t) is constant with
time.
➢ An important and unique consequence of phase locking is
that the input and output frequencies of the PLL are exactly
equal.
9
Analysis of Simple PLLs

➢ If the loop is locked, the input and output frequencies are equal,
the PD generates repetitive pulses, the loop filter extracts the
average level , and the VCO senses this level so as to operate at
required frequency

10
Example of Phase Error
• If the input frequency changes by Δω, how much is the change in the phase error? Assume the loop
remains locked.

• Depicted in the figure above, such a change requires Vcont change by

Δω/KVCO. This in turn necessitates a phase error change of
∆𝜔
∆∅2 − ∆∅1 =
𝐾𝑉𝐶𝑂 𝐾𝑃𝐷
• The key observation here is that the phase error varies with the frequency.
• To minimize this variation, KPDKVCO must be maximized.
• This quantity is sometimes called the “loop gain” even though it is not dimensionless.
11
Response of PLL to Input Frequency Step

PD VCO

➢ The loop locks only after two conditions are satisfied:

(1)ωout becomes equal to ωin
(2)the difference between ϕin and ϕout settles to its proper value

12
Example of FSK Input Applied to PLL
An FSK waveform is applied to a PLL. Sketch the control voltage as a function of time.

Vcont
t
The input frequency toggles between two values and so does the output
frequency. The control voltage must also toggle between two values.
The control voltage waveform therefore appears as shown in figure above,
providing the original bit stream. That is, a PLL can serve as an
FSK (and, more generally, FM) demodulator if Vcont is considered the output.
13
PLL No Better than a Wire?
Having carefully followed our studies thus far, a student reasons that, except for the FSK
demodulator application, a PLL is no better than a wire since it attempts to make the input
and output frequencies and phases equal! What is the flaw in the student’s argument?

• Nonetheless, we can observe that the dynamics of the loop can yield interesting and useful properties.
• Suppose in the previous example, the input frequency toggles at a relatively high rate, leaving little time for the PLL
to “keep up.”
• As illustrated in figure, at each input frequency jump, the control voltage begins to change in the opposite direction
but does not have enough time to settle.
• In other words, the output frequency excursions are smaller than the input
frequency jumps.
• The loop thus performs low-pass filtering on the input frequency variations—just as
the unity-gain buffer performs low-pass filtering on the input voltage variations if
the op amp has a limited bandwidth.
• In fact, many applications incorporate PLLs to reduce the frequency or phase noise
of a signal by means of this low-pass filtering property.

14
Loop Dynamics: the Meaning of Transfer Function in Phase
Domain +
-

PLL

➢ The transfer function of a voltage-domain circuit signifies how a

sinusoidal input voltage propagates to the output.
➢ The transfer function of a PLL must reveal how a slow or a fast
change in the input (excess) phase propagates to the output.

15
 𝐾𝑉𝐶𝑂
𝑠

The open-loop transfer function 𝐾𝑃𝐷 Τ(𝑅1 𝐶1 𝑠 + 1) 𝐾𝑉𝐶𝑂 /𝑠

Overall closed-loop transfer function
∅ 𝐾𝑃𝐷 𝐾𝑉𝐶𝑂
H(s)= ∅𝑜𝑢𝑡 𝑠 = 𝑅 2
𝑖𝑛 1 𝐶1 𝑠 +𝑠+𝐾𝑃𝐷 𝐾𝑉𝐶𝑂

the open-loop transfer function contains one pole at the origin

-> This system is called “type-I PLL.”
-> slow input phase variations (s ≈ 0), H(s) ≈ 1

16
Damping Factor and Natural Frequency
➢ The damping factor ≈ 𝜔𝑛2
𝐻 𝑆 = 2
2 /2 be or larger so as to 𝑠 + 2ζ𝜔𝑛 𝑠 + 𝜔𝑛2
provide a well-behaved
1 𝜔𝐿𝑃𝐹
(critical damped or ζζType
= equation here.
overdamped) response. 2 𝐾𝑃𝐷 𝐾𝑉𝐶𝑂
➢ ωLPF=1/(R1C1)
𝜔𝑛 = 𝐾𝑃𝐷 𝐾𝑉𝐶𝑂 𝜔𝐿𝑃𝐹

• ζ is inversely proportional to KVCO.

• The behavior of the open-loop transfer function, Hopen, for two

different values of KVCO. As KVCO increases, the unity-gain frequency
rises, thus reducing the phase margin (PM).

17
Two Additions for Loop Dynamics
➢ Since a linear, time-invariant operation relates phase and frequency, the equation below
applies to frequency quantities.
𝜔𝑛2
𝐻 𝑆 = 2
𝑠 + 2ζ𝜔𝑛 𝑠 + 𝜔𝑛2

How do we ensure the feedback of previous simple PLL implementation is negative?

• The phase detector provides both negative and positive gains. Thus, the loop automatically
locks with negative feedback.

18
Frequency Multiplication
+
PD VCO
-

÷2

➢ The output frequency of a PLL can be divided and then fed back.
➢ The ÷M circuit is a counter that generates one output pulse
for every M input pulses.
➢ The divide ratio, M, is called the “modulus”.

19
Drawbacks of Simple PLL
➢ First, a tight relation between the loop stability and the corner frequency of the low-pass
filter. Ripple on the control line modulates the VCO frequency and must be suppressed by
choosing a low value for ωLPF, leading to a less stable loop
1 𝜔𝐿𝑃𝐹
ζ=
2 𝐾𝑃𝐷 𝐾𝑉𝐶𝑂
➢ Second, the simple PLL suffers from a limited “acquisition range”. If the VCO frequency and
the input frequency are very different at the start-up, the loop may never “acquire” lock.

➢ In addition, the finite static phase error and its variation with the
input frequency also prove undesirable in some applications.

20
 RF Transceiver Design
Lecture 59
Basics of Phase Locked Loop – II

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
Type-II PLLs: Phase/Frequency Detectors
PFD

➢ A rising edge on A yields a rising edge on QA (if QA is low)

➢ A rising edge on B resets QA (if QA is high)
➢ The circuit is symmetric with respect to A and B (and QA and QB)

2
Operation of PFD: State Diagram

𝑄𝐴 = 0 𝑄𝐴 = 0 𝑄𝐴 = 1
𝑄𝐵 = 1 𝑄𝐵 = 0 𝑄𝐵 = 0

➢ At least three logical states are necessary: QA=QB=0; QA=0, QB=1;

and QA=1, QB=0
➢ To avoid dependence of the output upon the duty cycle of the
inputs, the circuit should be realized as an edge-triggered
sequential machine

3
Use of a PFD in PLL
D
Q
CK

D
Q
CK

➢ QA and QB are simultaneously high for a duration given by the

total delay through the AND gate and the reset path of the flipflops.
➢ The width of the narrow reset pulses on QA and QB is equal to
three gate delays plus the delay of the AND gate

4
PFD: Logical Implementation

+
PFD 𝐴 VCO
- 1

➢ Using a PFD in a phase-locked loop resolves the issue of the limited acquisition range.
➢ At the beginning of a transient, the PFD acts as a frequency
detector, pushing the VCO frequency toward the input frequency.
After the two are sufficiently close, the PFD operates as a phase

5
Charge Pumps: an Overview
➢ Switches S1 and S2 are controlled by the
inputs “UP” and “Down”, respectively.
➢ A pulse of width ΔT on Up turns S1 on for
ΔT seconds, allowing I1 to charge C1. Vout
goes up by ΔT · I1/C1
➢ Similarly, a pulse on Down yields a drop in
Vout.
➢ If Up and Down are asserted
simultaneously, I1 simply flows through S1
and S2 to I2, creating no change in Vout.

6
Computation of the Transfer Function ➢ Infinite Gain: An arbitrarily
small (constant) phase
difference between A and B still
turns one switch on, thereby
PFD
charging or discharging C1 and
driving Vout toward +∞ or -∞

We can approximate the PFD/CP circuit of figure above as a current source of some average
value driving C1. Calculate the average value of the current source and the output slope for an
input period of Tin.

For an input phase difference of ΔΦ rad = [ΔΦ /(2π)] × Tin

seconds, the average current is equal to Ip ΔΦ /(2π) and
the average slope, Ip ΔΦ /(2π) /C1.

7
Charge-Pump PLL
𝐼𝑃 𝐾𝑉𝐶𝑂
2𝜋𝐶1 𝑠 . 𝑠
𝐻𝑆 =
𝐼𝑃 𝐾𝑉𝐶𝑂
PDF VCO 1 + 2𝜋𝐶 𝑠 . 𝑠
1
𝐼𝑃 𝐾𝑉𝐶𝑂
=
2𝜋𝐶1 𝑠 2 + 𝐼𝑃 𝐾𝑉𝐶𝑂

➢ Such a loop ideally forces the input phase error to zero because a finite
error would lead to an unbounded value fro Vcont.
➢ We will first derive the transfer function of the PFD/CP/C1 cascade.
➢ Called Type-II PLL because its open-loop transfer function contains two
poles at the origin

8
Charge Pump PLLs: First Attempt

PDF

We can approximate this waveform by a ramp --- as if the charge pump continuously injected
current into C1
∆∅𝑜 𝐼𝑝
∆𝑉𝑐𝑜𝑛𝑡 = 𝑇
2𝜋 𝑖𝑛 𝐶1
∆∅𝑜 𝐼𝑝
𝑉𝑐𝑜𝑛𝑡 (t)≈ tu(t)
2𝜋 𝐶1
𝑉𝑐𝑜𝑛𝑡 𝐼
(s) =2𝜋𝐶𝑃 𝑠
∆∅ 1

9
Charge-Pump PLL

PDF VCO

➢ If one of the integrators becomes lossy, the system can be stabilized.

➢ This can be accomplished by inserting a resistor in series with C1. The
resulting circuit is called a “charge pump PLL” (CPPLL)

10
Approximate the pulse sequence by a step of height (IpR1)[ΔΦ0/(2π)]:
∆∅𝑜 𝐼𝑝 ∆∅𝑜 𝐼𝑝
𝑉𝑐𝑜𝑛𝑡 (t)= tu(t)+ 𝑅 u(t)
2𝜋 𝐶1 2𝜋 𝐶1 1 𝐼𝑃 𝐾𝑉𝐶𝑂
𝑅1 𝐶1 𝑠 + 1
𝑉𝑐𝑜𝑛𝑡 𝐼 1
2𝜋𝐶1
(s) = 𝑃 + 𝑅1 𝐻𝑆 =
𝐼 𝐼 𝐾
∆∅ 2𝜋 𝐶1 𝑠 𝑠 2 + 𝑃 𝐾𝑉𝐶𝑂 𝑅1 𝑠 + 𝑃 𝑉𝐶𝑂
2𝜋 2𝜋𝐶1

11
Stability of Charge-Pump PLL
Write the denominator as 𝑠 2 + 2ζωns + ω2𝑛

𝑅 𝐼𝑃 𝐾𝑉𝐶𝑂 𝐶1
ζ= 21 2𝜋

𝐼𝑃 𝐾𝑉𝐶𝑂
𝜔𝑛 =
2𝜋𝐶1
Closed-loop poles are given by
𝜔𝑝1,2 = −ζ ± ζ2 − 1 𝜔𝑛

a closed-loop zero at –ωn / 2ζ

𝑉𝑐𝑜𝑛𝑡 𝐼𝑃 1
(s) = + 𝑅1
∆∅ 2𝜋 𝐶1 𝑠
12
Integer-N Frequency Synthesizers
• Why do we need frequency synthesizers?
÷𝐾 PFD ➢ The VCO frequency High (GHz Range)
/CP ➢ The practical references (MHz Range) -> the limitation of
crystals.
➢ The VCO frequency → Tunable; Reference is not
÷𝑁
𝑁𝑓𝑅𝐸𝐹
𝑓𝑂𝑈𝑇 = = 𝑁𝑓𝐶ℎ𝑎𝑛𝑛𝑒𝑙
𝐾

Required channel spacing

13
The Bode plot of the open-loop gain G(s) as well as the PLL closed-loop transfer function H(s)

ωz ωu
14
Noise Sources in Synthesizer

15
 Phase Noise
Assuming a simple RC loop filter, the transfer function follows
as
𝑁𝜔𝑛 2 1+𝑅𝐶𝑠
2
𝑆 2 +2𝜁𝜔𝑛 𝑠+𝜔𝑛

and the two poles of the transfer function (assuming

overdamped function) are given by
𝜔𝑃1,2 = 𝜔𝑛 𝜁 ± 𝜁 2 − 1

Synthesizer typical noise contributors Frequency Offset

16
Fractional-N Frequency Synthesizers PFD
/CP
• The integer-N synthesizers have a major drawback: the reference frequency
cannot be higher than the channel spacing.
• This, in turn, sets the upper bound of the loop bandwidth, which causes several
implications: ÷N/N+1
– The size of the loop filter capacitors and resistors
– Synthesizer settling time
– Close-in and far-out phase noise
𝑀𝑜𝑑𝑢𝑙𝑢𝑠
– Ability to work with any arbitrary crystal frequency
Control
– Reference spurs, and the amount of filtering they could be subject to

17
 • The main drawback of the simple approach outlined in Figure is
÷N the creation of fractional spurs.
• Hypothetical example of dividing by N for three cycles, and by N+1
for the fourth cycle.
REF • Now, assume the PLL feedback loop forces the output steady-
state frequency to be
DIV 1
𝑓𝑂𝑈𝑇 = 𝑓𝑅𝐸𝐹 𝑁 +
𝐾
U
• Where fREF is the reference frequency and K=4.
D • For the first three cycles of dividing by N, the divider frequency is

1
𝑓𝑅𝐸𝐹 𝑁 + 𝐾
VCTRL 𝑓𝐷𝐼𝑉 = > 𝑓𝑅𝐸𝐹
𝑁

• Thus, the PFD starts to generate down pulses to slow down the VCO, which in turn causes the
control voltage to reduce
• On the 4th cycle, the VCO is divided by N+1, resulting in the divider output to be slower than the
reference, and hence, an up signal is created that raises the control voltage.
• This pattern repeats every K = 4 cycles, leading to the VCO being modulated by a periodic signal
with a period of fREF/K =α.fREF, creating sidebands at α.fREF, and its harmonics.

18
Noise Shaping
• One very common and elegant technique to deal with fractional spurs is exploiting the noise shaping
concept widely used in data converters.
• The periodicity of the control voltage could be broken if the divider modulus is randomly selected
between N and N+1, but still maintains the desired average value.
• The deterministic fractional spurs appearing as tones will be converted to noise spreading around the
VCO signal, with the total energy remaining the same.
• relation between the divider and output frequencies as
𝑓𝑜𝑢𝑡
𝑓𝑂𝑈𝑇 = where b(t) is a random stream of 0s and 1s with an average value of α.
𝑁+𝑏 𝑡 q(t) additive quantization noise

𝑏 𝑡 = α+q(t)

𝑓𝑜𝑢𝑡 𝑓𝑜𝑢𝑡 /(𝑁 + α ) 𝑞 𝑡

𝑓𝐷𝐼𝑉 = = ≅ 𝑓𝐷𝐼𝑉,𝑛𝑜𝑟𝑚 1 −
𝑁 + α+ q(t) 𝑞 𝑡 𝑁𝑛𝑜𝑟𝑚
1+
𝑁+α

19
20
Frequency Dividers
• common circuit ideas to realize these dividers: Latches and D Flip-Flops

Analog current-mode latch

Schematic of a static CMOS latch Dynamic CMOS latch

21
D flip-flop formed with two back-to-back latches Dynamic CMOS flip-flop

22
Divide by 2 using a toggle flip-flop (flip-flop in a feedback loop)

Speed concerns in a divide-by-2 circuit IN

Clk L1 OUT
CK
L2 OUT
L1 OUT
L2 OUT

• For the divider to function properly, the delay of one latch must be less
than half the input signal period as depicted in the above Figure
• Once the input goes high, the first latch is transparent, and its input is
expected to go up, but with some delay in practice (Δ1 in the figure). This
signal must be ready before the second latch becomes transparent, which
is when the input goes back low, or else the divider fails

23
Dual-mode Dividers
• With the D flip-flops used as the main building block, and with a few simple gates, we can construct the
dual- or multi-modulus dividers needed in the synthesizer design.
• As a simple rule of thumb, to create a certain divide ratio, n, the number of latches needed is usually
chosen such that 2n is the closest integer larger than the desired divide ratio, e.g., two latches for a
divide-by-3, or three latches for a divide-by-5, or 6.
An example of a divide-by-2/3 circuit and the corresponding timing
diagram

IN
Q1
A1
Q2

24
Multi-mode Dividers
• The dual-modulus dividers presented
÷2/3 ÷2/3 ÷2/3 earlier are not directly usable in integer or
MOD MOD MOD fractional synthesizers, given that typically
much larger divide ratios are needed.
• They can, however, be used to create
programmable multi-modulus dividers.

IN IN
Q1 Q3
Q2 Out
Q3

• Programmable multi-modulus divider (MMD) consisting of several divide-

by-2/3 stages presented earlier. By choosing the 3-bit programming word,
M2M1M0, a programmable divide ratio of 8 to 15 can be achieved.

25
Introduction to Digital PLLs
• Limitations of the analog PLLs
– Depending on the noise requirements and the reference frequency, the loop filter size can become large.
– While the capacitors scale with technology, their size still does not reduce as favourably as the digital gates.
– A large charge pump current is often required to achieve a low in-band phase noise.
– PFD/CP linearity could be a concern for certain applications.
– There is an important trade-off between the noise contribution of the PLL building blocks, particularly the VCO
and the ΔΣ modulator.

Digital
PFD/CP TDC LF

MMD MMD

26
 RF Transceiver Design
Lecture 60
System Level Considerations

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
Link Budget
• From Transmitter to receiver, accounting all losses, gain, and powers.
EIRP P𝑅𝑥 =P𝑇𝑥 − 𝐿 𝑇𝑥 + 𝐺𝑇𝑥 − 𝐿𝑃 + 𝐺𝑅𝑥 − 𝐿𝑅𝑥
(Radiated
Power)
2
4𝜋𝑅
𝐿𝑃 𝑓𝑟𝑒𝑒 𝑠𝑝𝑎𝑐𝑒 =
𝜆
Received
Power
Transmitted

Transmitted

Link Margin
Power

Loss

Receiver
Sensitivity
Path Loss

𝑃𝑇𝑥 𝐿 𝑇𝑥 𝐿𝑃 𝐿𝑅𝑥 𝑃𝑅𝑥

2
SYSTEM-LEVEL CONSIDERATIONS
• Deriving Transceiver performance
(1) Budget allocated for each component has sufficient margin.
(2) Both the TX and the RX corrupt the signal

Receiver Transmitter Receiver Architecture

• Noise Figure • Linearity
• Sensitivity • Gain Frequency Synthesizer
• Nonlinearity • IQ Imbalance
• Automatic Gain
Control (AGC) Range Frequency Planning
• Max. I and Q Mismatch

3
Receiver
Noise Figure Estimation :
• Identification of standard -> BER/PER, Modulation scheme (QAM,BPSK), SNR, BW
• Based on Sensitivity, find overall receiver NF.
• Add sufficient margin for switches, Antennas, cable losses.
• Receiver is stationary or Moving -> Variability in Gain

4
Nonlinearity:

• Modulation scheme,
• blocker information,
• peak-to-average power ration

AGC Range:

• The receiver must automatically control its gain if the received signal level varies
considerably.
• ADC require full scale range:
• It follows that the RX gain must vary to accommodate the rate-dependent
sensitivities.
• The challenge is to realize this gain range while maintaining a noise figure.
• The receiver gain range is also determined by the maximum allowable desired
input level.

5
Transmitter
• The transmitter chain must be linear enough to deliver a desired modulation signal to the antenna
with acceptable distortion.
• In order to quantify the tolerable nonlinearity, a TX or PA model must be assumed and simulated
with such a signal.
• To achieve high linearity:

(1) Assign most of the gain to the last PA stage so as to minimize the output swing
of the preceding stages
(2) Minimize the number of stages in the TX chain.

6
• The gain of the TX chain from the baseband to the antenna somewhat depends on the
design details.
• For example, a baseband swing of 0.2Vpp requires a gain of 20 to reach an output swing of
4Vpp (=+16 dBm).
• It is desirable to employ a relatively large baseband swing so as to minimize the effect of
DC offsets and, hence, the carrier feedthrough, but mixer nonlinearity constrains this
choice.
• The I/Q imbalance necessary in the TX is similar to that given for the RX (0.2 dB and 1.5o),
requiring calibration in the transmit path as well.
• The carrier feedthrough is another source of corruption in direct-conversion transmitters.
• For 11a/g systems, a feedthrough of about -40 dBc is achieved by means of baseband
offset cancellation.

7
Role of EDA Simulation Design in RF Transceiver Design
• Electronic Design Automation, or EDA, is a market segment
consisting of software, hardware, and services with the collective
goal of assisting in defining, planning, designing, implementing,
verifying, and subsequent manufacturing of semiconductor
devices, or chips.
• Regarding the manufacturing of these devices, the primary
providers of this service are semiconductor foundries or fabs.
• These highly complex and costly facilities are owned and operated
by large, vertically integrated semiconductor companies or
independent, “pure-play” manufacturing service providers.

Source: https://www.synopsys.com/glossary/what-is-electronic-design-automation.html

8
Why is EDA Important?
• Semiconductor chips are incredibly complex. State-of-the-art devices can contain over one billion circuit
elements.
• All of these elements can interact with each other in subtle ways, and variation in the manufacturing
process can introduce more subtle interactions and changes in behavior.
• There is simply no way to manage this level of complexity without sophisticated automation.
• EDA provides this critical technology, without it, it would be impossible to design and manufacture
today’s semiconductor devices.
• Chips errors cannot be “patched.” The entire chip must be re-designed and re-manufactured.
• The time and cost of this process are often too long and too expensive, resulting in the failure of the
entire project.
• Without EDA tools, these challenges cannot be met.
• EDA tools: Synopsys, Cadence, and Mentor (now Siemens EDA) are the
primary companies leading this phase.
Keysight’s ADS, LT Spice (freeware)

9
How Does EDA Work?
• EDA is a very sophisticated and complex software program that functions
primarily in one of three ways to assist with the design and manufacture
of chips:
• Simulation tools take a description of a proposed circuit and predict its
behavior before is it implemented.
• Design tools take a description of a proposed circuit function and
assemble the collection of circuit elements that implement that function.
This is a logical process (assemble and connect the circuit elements) and a
physical process (create the interconnected geometric shapes that will
implement the circuit during manufacturing).
• Verification tools examine the chip's logical or physical representation to
determine if the resultant design is connected correctly and will deliver
the required performance.

10
Types of EDA Tools

Simulation Design Verification

• Simulation tools take a • Design tools take a description of a • This examines the chip's logical or
description of a proposed circuit proposed circuit function and assemble physical representation.
and predict its behavior before is the collection of circuit elements that • This also ensures their placement
it implemented. implement that function. obeys the manufacturing
• This is typically presented in a • Logic synthesis is an example of this requirements of the fab.
standard hardware description process. • Layout vs. schematic, or LVS, is
language such as Verilog or • It can also be a physical process where an example of this process.
VHDL. the geometric shapes that implement
• Simulation tools perform various the circuit in silicon are assembled,
operations to predict the placed, and routed together.
resultant behavior of the circuit. • Broadly, this process is known as place
and route.
• It can also take the form of an
interactive process guided by a designer.
• This is called custom layout.

11
 RF Transceiver Design
Lecture 61
RF Testing & Measurement Techniques

Prof. Darshak Bhatt

Department of Electronics and Communication Engineering

1
Ways of RF Testing

Die

Bond wire + PCB

PCB
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Essentials for Die Testing
❖ Probes availability as per layout
❖ Desired instruments
❑ NA (Network Analyzer)
❑ Spectrum Analyzer
❑ Source Generator
❑ DC Supply Meter
❑ Noise Source for NF measurement
❖ Cables and Connectors
❖ Baluns and Combiners

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Essentials for Bond Wire + PCB
❖ To reduce the parasitic and complexity of probe testing, this method is
used
❖ It will add more parasitic than die testing and less than package
❖ Easy to handle it.
❖ Difficult to bond wire. It should be done with expertise in bond wiring.
❖ Bond wiring requirement
❑ Pitch should known
❑ Minimum pad area to bond wire
❑ Pad metal used (Al, Cu, etc.)

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Essentials for Package Testing
❖ The bond wire diagram should be clear.
❖ For RF testing, standard packages that add fewer parasitics have been used, such
as QFN, BGA, etc.
❖ Matching network should be inside chip (challenges, it will have low Q and lossy).
❖ External matching is a concern because you need to model the s-parameter and
design PCB while considering matching issues.
❖ With L and C, only narrow band matching is possible for wideband matching; it will
take more space and be lossy.
❖ For RF input signal, use the RF transformer concept
for impedance matching.
❖ Your PCB design should be tested in any EM Software.

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Summary of Challenges in RF Testing
❖ RF devices need extra attention during testing (challenge #1)
❑ Impedance matching @ input and output ports to ensure optimal power
transfer.
❑ Shielding from external wireless signals during testing.
❖ The test needs to perform all of the above with
❑ Cheaper instrumentation -> a low-cost commercial tester (challenge #2)
❑ Perform tests in a short duration (challenge #3)
❑ Achieve a high degree of accuracy (challenge #4)

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Fabricated Die and Probe Testing Setup

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Fabricated Die and Probe Testing Setup

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Input Matching plot

Input is matching at 2.4 GHz, which is the desired frequency matching

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RF-LO Isolation using Network Analyzer (56 dB)

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Folded Mixer PCB setup for measurement

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Measured Gain of Folded Mixer RF input = -33 dBm
(By considering Connectors,
Cable, baluns, Bias Tee losses)
LO input=1.5 dBm
IF Output = -30.66 dBm
Conversion Gain= 2.34 dB

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Noise Figure Measurement: SNR Method

Input SNR Plot

𝑆𝑁𝑅𝐼𝑁
𝑁𝐹 =
𝑆𝑁𝑅𝑂𝑈𝑇
𝑆𝑁𝑅𝐼𝑁 = 60.93 𝑑𝐵

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Noise Figure Measurement: SNR Method

Output SNR Plot

𝑆𝑁𝑅𝑜𝑢𝑡 = 50.79 𝑑𝐵
𝑁𝐹 = 𝑆𝑁𝑅𝑖𝑛 − 𝑆𝑁𝑅𝑂𝑢𝑡
= 60.93 − 50.79
= 10.14 𝑑𝐵

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Noise Figure Measurement: Y Factor Method
• Setting: Frequency setting, ENR table setting,
analysis time setting, etc.
• Calibration: The NF of the measurement system
(NF_2) using the Y factor method, and then it
normalizes NF and conversion gain.
• Measurement: Measurement of total NF (DUT +
measurement system) using the Y factor method,
and then it calculates the NF of the DUT (NF_1)

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Linearity Measurement (IIP3 = -1.5 dBm)

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Thank You

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