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CMOS LNA Using 130nm Process With Improved Noise Figure And Linearity
Using Harmonic Rejection Technique

Conference Paper · November 2015

DOI: 10.1109/ICESA.2015.7503381

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 CMOS LNA Using 130nm Process With Improved
Noise Figure And Linearity Using Harmonic
Rejection Technique

Madhura Khisti Satish Turkane

Department of E & TC Department of E & TC
Pravara Rural Engineering College, Loni, Pravara Rural Engineering College, Loni,
Savitribai Phule Pune University, Savitribai Phule Pune University,
Maharashtra, India Maharashtra, India
[email protected] [email protected]

Abstract—A Cascode differential LNA using 130nm CMOS degradation, nonlinear output conductance, velocity saturation,
process is proposed. The linearity enhancement is achieved by, etc.; which introduces difficulties in CMOS LNA linearization,
restrained generation of 3rd order Harmonic component. To particularly in the expression of low supply voltages [3].
cancel the 3rd Harmonic component, a RC feedback from Drain
node of common-gate to the Source node of common-gate The progressive technology scaling allows designing high
transistor is used. To achieve low Noise Figure, Cascode stage gain, low noise, and low power consumption. On the other
transistors are used. This technique is verified by comparing the hand, the linearity of CMOS is being paid of inferior quality as
design of Classical LNA and the Proposed LNA. The LNA the process scales down. This has inspired quite a few CMOS
achieves Noise Figure 2.435dB, Input-referred P1dB -4.18dBm LNA linearization methods. Simple methods of LNA
and Gain 19dB. From these measured result the Proposed LNA linearization must be employed ought to have minimum Noise
successfully proves that it has minimum Noise Figure and is Figure, less power, high gain and input matching. Many old-
linear. style linearization techniques are not possible for LNAs. For
example, floating-gate input attenuation; resistive source
Keywords—cascode differential amplifier; CMOS; LNA (Low degeneration, etc. it deteriorate Noise Figure, decrease the gain.
Noise Amplifier); linearity; harmonic rejection; NF(Noise Figure) Hence, LNA linearization proves considerably more difficult to
perform than that of base band circuits [3], [4].
I. INTRODUCTION
The basic philosophy of feedback is to correct a nonlinear
The first active block of receiver path of communication active device in the forward path with a linear passive element
transceivers is typically a Low Noise Amplifier. Since antenna in feedback path. Feedback linearizes a circuit at the price of
receives weak signals prior to any of the signal processing thus gain reduction. Thus, feedback is an effective technique for
the signal has to be amplified. The receiver’s sensitivity is the linearization in analog and RF circuits. The linearity
important feature of the receiver. Sensitivity is defined as the performance is depreciated caused in a high frequency region;
least possible signal that can be received by the receiver. The feedback could introduce harmonic feedback components. In a
receiver that can receive largest signal founds an upper power low frequency region, the harmonic feedback components are
level boundary that the system deals while preserving generally suppressed by high loop gain. Still, in high frequency
information excellence. The dynamic range of the receiver, region, it is hard to get a high loop gain because the open-loop
which is the deviation of the largest signal from the smallest gain is already too low. Thus, in high frequency circuit design,
signal received, describes the excellence of the receiver chain. it is difficult to enjoy the advantage of feedback in linearization
The noise contributed by the LNA must be low to maintain the [5]–[8].
signal integrity. To restrain the interference and retain high
sensitivity LNA must be linear. Other important design Feedback is to correct a nonlinear active device in the
parameters are input return loss, stability, frequency of forward path with a linear passive element in the feedback
operation. LNA designed to use CMOS technology presents path. Feedback linearizes a circuit at the price of gain reduction
various obstacles like gain reduction due to parasitic thus feedback is the important technique for analog and RF
inductance, linearity of CMOS process is worse [1], [2]. circuit [6]. The two design parameters that we focus on are
Noise Figure and Linearity.
For System on chip CMOS is the utmost promising
technology. Even though MOSFETs are innately linear than In this paper, we propose a differential LNA which
bipolar transistors, they need greater DC current to attain the simultaneously cancels the 3rd order harmonic component and
obligatory linearity and transconductance, thus to reduce the noise. Section II describes the proposed technique with the
DC power, linearization techniques must be implemented. LNA schematic. Section III shows the experimental results,
Deep sub-micrometer technology defies include mobility and Section IV concludes this paper.
 II. PROPOSED LNA Noise Figure and impedance matching for narrow band
The schematic diagram of Proposed Single Stage systems. It gives very low Noise Figure with a good narrow
Differential LNA is shown in the Fig. 2. A LNA design boons band match. The Fig. 1 shows the designed Classical LNA.
substantial defy due to its simultaneous necessity for high gain, The Fig. 2 shows Proposed Single Stage LNA, in which RC
good input and output matching, linearity, low Noise Figure cross coupled feedback is shown. The implemented Classical
and unconditional stability at the lower most probable current LNA and the Proposed LNA are Single Stage LNA. The
pulled from the amplifier. The LNA employs a Cascode further improvement in the Proposed LNA is the gain
differential topology. The inductively degenerated LNA can improvement. This is done by implementing Two Stage LNA.
achieve maximum gain, minimum Noise Figure and input In this Two Stage LNA design the first stage has been
impedance matching [9]. A nonlinear LNA with input X and implemented with NF improvement. LNA with a high linearity
output Y can be approximated by the first three power series is required; the best place for applying the linearity
terms enhancement technique is at the second stage. Fig. 3 shows
Proposed Two Stage LNA.
Y  g1 X  g2 X 2  g3 X 3 (1)
VCC

Where g1,2,3 are first, second and third ordered nonlinearity 1.2V
C1 R1 R2 C4
coefficients of the LNA, respectively. Thus the objective is to 245Ω 235Ω 4 T2 1

make the values of g2,3 as small as possible. Keeping the only 10pF 15pF
3
R6
50Ω
linear term g1 therefore Y ~ g1X [3]. C5
2 0

The node voltage is calculated as follows: Q1 Q2 20pF

VIN (t )  A cos(t ) (2)

1kΩ R5

VM (t )  1VIN (t )   2VIN2 (t )  3VIN3 (t )  .....

4nH VCC
(3) L1
1.2V
4nH
L2
Q3 Q4
19pF C3 30pF

VOUT (t )  1VM (t )  2VM2 (t )  3VM3 (t )

V3 T1 2 L5 L6
(4)
0
2.5nH 4.5nH
3 C2
5 R3 R4
L3 L4 1.5kΩ

3 3 A 3 1 4 1.5kΩ 0.5nH 0.5nH

1
VOUT (t ) |3rd  (1 A  3 ) 4 V1
V2

4 4 (5)
0.5 V
0.5 V

3 A3
3  3 A3 3
 1 ( )  3 ( )
4 4 4
Where VIN (t ) is the input signal, VM (t ) is the signal at Fig. 1. Classical Single Stage LNA

the differential source node of common gate, VOUT (t ) is the VCC

1.2V
output signal, α and β are the harmonic constants and A is C1 R1 R2 C4
T2 1
245Ω 235Ω 4

amplitude. To guarantee the linearity, 1 A  (33 A3 ) / 4 and 10pF 15pF

3
R6
R7 R8 50Ω
1 are considered higher than (33 A3 ) / 4 and  3 these are 1200Ω 1200Ω
C5
2 0
C6 C7
factors that are affected. The linearity of the LNA is enhanced Q1 Q2 20pF

by suppressing the harmonic components at the nodes of the 2pF 2pF

amplifier. In this design the second order harmonic component

gets suppressed by the virtue of the benefit of differential
1kΩ R5
structure, at the input output baluns and at the nodes as virtual 4nH
L1
VCC 4nH
ground [1]. The amplifier intended differential topology so the Q3
1.2V L2
Q4
even order harmonics gets terminated. Only the odd harmonic V3 T1 2
19pF L5 L6 C3 30pF
0
terms exist. 3 C2
2.5nH 4.5nH
5 R3 R4
The third harmonic component is restrained by feedback 1 4
L3
1.5kΩ 0.5nH
L4 1.5kΩ

loop. The transfer function H(ω), is of RC feedback is used in 1

0.5nH
V2
the cross coupled it has between drain and source of the V1
0.5 V
common gate transistor. The transfer function H(ω) polarity 0.5 V

magnitude essentially be negative for the third order harmonic

term in the circuit. This is possible owing to the cross coupling
of RC feedback connection [1].
Fig. 2. Proposed Single Stage LNA
To improve the Noise Figure, the inductive degeneration
topology is used along with Cascode transistors to generate the The feasibility of the Proposed LNA is done by comparing
required input impedance. This topology gives very good the Classical LNA and the Proposed LNA using CMOS 130nm
process. The RF and CF are the feedback components have III. MESUREMENT RESULTS
values 1.2KΩ and 2.0pF respectively. Now, strength of the Fig. 4 shows the measured S-parameters of the Proposed
feedback signal is set by value of RF the feedback component. LNA Single Stage. Fig. 5 shows the measured S-parameters of
DC blocking is achieved by CF and limits the fundamental Proposed Two Stage LNA. The improved NF obtained are
components from ingoing into the feedback loop. 2.073dB and 2.435dB for the Proposed Single Stage and Two
VCC
Stage LNA respectively. The input referred P1dB obtained for
1.2V the both Proposed LNAs are -6.134dBm and -4.185dBm. Thus
C1 R1
245Ω 235Ω
R2 C4
4 T2 1
the Noise Figure is minimum compared to the designed
10pF 15pF R6 Classical LNA and also linearity is improved. We obtain
R7 R8
3
50Ω maximum gain of 19dB. LNA parameters are simulated using
C5
1200Ω 1200Ω 2 0 the ADS simulator.
C6 C7
Q1 Q2 20pF
2pF 2pF We determined the gain of the designed circuit gets
degraded because of the feedback technique proposed. The
proposed feedback loop introduced to reduce the 3rd order
1kΩ R5 harmonic component, does not cause the instability in the
4nH VCC
L1 4nH
1.2V L2 designed circuit of LNA.
Q3 Q4
19pF L5 L6 C3 30pF
The linearity is enhanced as P1dB given by the Proposed
C2
2.5nH
R3 R4
4.5nH
LNA is improved even though the technology is scaled down
L3 L4 1.5kΩ from 180nm to 130nm. The Noise Figure is shown in the Fig. 6
1.5kΩ 0.5nH
Stage 1
0.5nH
V2
and Fig. 7. The Noise Figure has improved than the LNA with
V1
0.5 V
cross coupled RC feedback. The measured performances of the
0.5 V
Classical
SC1 and Proposed LNAs are summarized in Table I.

Fig. 3. Proposed Two Stage LNA

2N7000
2N7000
2N7000
20 2N7000 20

10
0
dB(S(2,2))
dB(S(2,1))
dB(S(1,2))
dB(S(1,1))

dB(S(2,2))
dB(S(2,1))
dB(S(1,2))
dB(S(1,1))

-20

-10

-40
-20

-30 -60
4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5.0 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5.0

freq, GHz freq, GHz

Fig. 4. Proposed Single Stage LNA S-Parameters Fig. 5. Proposed Two Stage LNA S-Parameters

Noise Figure (dB) Noise Figure (dB)

2.44 m1
2.08
m1 m1
m1 freq=5.000GHz
freq=5.000GHz 2.42
2.07 nf(2)=2.073 nf(2)=2.435
2.40

2.06 2.38
nf(2)
nf(2)

2.36
2.05

2.34
2.04
2.32

2.03 2.30
4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5.0 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5.0

freq, GHz freq, GHz

Fig. 6. Proposed Single Stage LNA Noise Figure Fig. 7. Proposed Two Stage LNA Noise Figure
 TABLE I. COMPAROSION OF D IFFERENTIAL LNA
This work
Parameters Classical LNA Proposed LNA [1] [10] [11]
Stage 1 1 2 2 1 1
Supply [V] 1.2 1.2 1.2 1.2 3 1.8
Frequency[GHz] 5.00 5.00 5.00 4.60 5.25 5.7
Tech. [nm] 130 130 130 180 250 180
NF [dB] 2.237 2.073 2.435 2.87 2.5 3.7
Gain [dB] 11.617 11.4 19 19 16 12.5
P1dB [dBm] -6.375 -6.1 -4.18 -11 -11 -11
Technology Scaling on CMOS RF and Digital Circuits for Wireless
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