1

CHAPTER 2+3:
(1) BASIC MOSFET
(2) SINGLE AND MULTISTAGE AMPLIFIER
ASSOC. PROF. LOAN PHAM-NGUYEN

Hà Nội, 9/10/2024
 Chapter 2’s Content : Basic MOSFET
2

❑ Review
❑ Deep triode region - 𝑅𝑂𝑁
❑ Transconductance
❑ Body affect
❑ Channel-length modulation
❑ MOS small-signal model
 MOSFET and Circuit
3

 MOSFET components
 MOSFET layout and interconnection to design circuit
 Review: Electronics Circuits 1
4

❖ If 𝑽𝑮𝑺 > 𝑽𝑻𝑯 , turn on MOSFET (NMOS).

❖ If 𝑉𝐷𝑆 ≤ 𝑉𝐺𝑆 − 𝑉𝑇𝐻 , MOSFET operates in triode region +
+ +
Vin _ V1 k.V1 R Vout
𝑊 1 2 _ _
𝐼𝐷 = 𝜇𝑛 𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇𝐻 𝑉𝐷𝑆 − 𝑉𝐷𝑆
𝐿 2
❖ If 𝑉𝐷𝑆 > 𝑉𝐺𝑆 − 𝑉𝑇𝐻 , MOSFET enters saturation region 𝑉𝑜𝑢𝑡
𝑔𝑚. 𝑉1 + =0
𝑅
1 𝑊
𝐼𝐷 = 𝜇𝑛 𝐶𝑜𝑥 𝑉 − 𝑉𝑇𝐻 2 ➔ 𝑉𝑜𝑢𝑡 = −𝑔𝑚. 𝑅. 𝑉1 = −𝑔𝑚. 𝑅. 𝑉𝑖𝑛
2 𝐿 𝐺𝑆
❖ The gain of the circuit is:
𝛿𝐼𝐷 𝑊
❖ Transconductance: 𝑔𝑚 = 𝛿𝑉𝐺𝑆
= 𝜇𝑛 𝐶𝑜𝑥 𝐿 𝑉𝐺𝑆 − 𝑉𝑇𝐻
𝑉𝑜𝑢𝑡
= −𝑔𝑚. 𝑅
𝑉𝑖𝑛
 Distinguish Saturation and Triode (linear) Region
5

 Determine IX as a function of VX?

 Deep triode region - 𝑅𝑂𝑁
MOSFET as a switch
6

𝑊 1 2
𝐼𝐷 = 𝜇𝑛 𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇𝐻 𝑉𝐷𝑆 − 𝑉𝐷𝑆
𝐿 2
❖ For 𝑉𝐷𝑆 ≪ 2 𝑉𝐺𝑆 − 𝑉𝑇𝐻 , MOSFET enters deep triode region:
𝑊
𝐼𝐷 ≈ 𝜇𝑛 𝐶𝑜𝑥 𝑉 − 𝑉𝑇𝐻 𝑉𝐷𝑆
𝐿 𝐺𝑆
which is linear function of 𝑉𝐷𝑆 ➔ MOSFET operates as a resistor.

1
𝑅𝑂𝑁 =
𝑊
𝜇𝑛 𝐶𝑜𝑥 𝐿 𝑉𝐺𝑆 − 𝑉𝑇𝐻

❖ Concept of switch (in Power Electronics Course)

 MOSFET as an amplifier
Transconductance gm
7

❖ In saturation region 1
Output resistance: 𝑟𝑜 = 𝜆𝐼
𝐷
1 𝑊 2
𝐼𝐷 = 𝜇𝑛 𝐶𝑜𝑥 𝑉 − 𝑉𝑇𝐻
2 𝐿 𝐺𝑆
❖ We have
𝛿𝐼𝐷 𝑊
𝑔𝑚 = = 𝜇𝑛 𝐶𝑜𝑥 𝑉 − 𝑉𝑇𝐻
𝛿𝑉𝐺𝑆 𝐿 𝐺𝑆
representing the sensitivity of current in gate-source voltage.

❖ Higher 𝑔𝑚 , a small change in 𝑉𝐺𝑆 result in a large change in 𝐼𝐷 .

❖ Other expressions of 𝑔𝑚 ?
 Body effect
8

❖ As 𝑉𝐵 becomes more negative, the depletion region becomes wider

❖ 𝑉𝐺𝑆 is required to be larger to turn on MOSFET:
❖ 𝑽𝑻𝑯 = 𝑽𝑻𝑯𝟎 + 𝜸 𝟐𝜱𝑭 + 𝑽𝑺𝑩 − 𝟐𝚽𝑭
❖ This phenomenon is called “body affect”

❖ How to bias MOSFET to modulate 𝑉𝑇𝐻 ?

 Channel-length modulation
9
❖ We know that the channel length decreases as 𝑉𝐷𝑆 − (𝑉𝐺𝑆 − 𝑉𝑇𝐻 )
increase. ➔ channel-length modulation
❖ The actual length of the channel

′
Δ𝐿 𝐿
𝐿 =𝐿 1+ =
𝐿 1 + 𝜆VDS
1 𝑊
→ 𝐼𝐷 ≈ 𝜇𝑛 𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇𝐻 2 1 + 𝜆𝑉𝐷𝑆
2 𝐿
❖ where 𝜆 is channel-length modulation coefficient.
❖ What make 𝐼𝐷 dependent on channel-length modulation?
10
 Junction Capacitance
11
 PN junction capacitance
 A pn junction has NA = 1025 holes/m3 and ND = 1022 electrons/m3. What is the barrier
voltage VD? Assuming that ni=1.5.1016 cariers/m3.
𝑁𝐴 𝑁𝐷 𝑘𝑇
◼ VD (= Φ0) = 𝑉𝑇 where 𝑉𝑇 = (≈ 26𝑚𝑉 𝑎𝑡 25℃) → Replace Φ0=0.88V
𝑛𝑖2 𝑞

 Inreverse bias (VR), the junction capacitance due to varying charge storage in the
depletion regions is modeled as Depletion Capacitance.
𝑁𝐴 𝑁𝐷 1/2
 On n side, the dep. Charge is: 𝑄+ = 2𝑞𝐾𝑠 𝜀0 ∅0 + 𝑉𝑅
𝑁𝐴 +𝑁𝐷
1/2
𝑑𝑄 + 𝑞𝐾𝑠 𝜀0 𝑁𝐴 𝑁𝐷 𝐶𝑗0 𝑞𝐾𝑠 𝜀0 𝑁𝐴 𝑁𝐷
◼ ➔ 𝐶𝑗 = = = where 𝐶𝑗0 = at VR= 0
𝑑𝑉𝑅 2 ∅0 +𝑉𝑅 𝑁𝐴 +𝑁𝐷 𝑉 2 ∅0 𝑁𝐴 +𝑁𝐷
1+ ∅𝑅
0
𝑞𝐾𝑠 𝜀0 𝑁𝐷 𝐶𝑗0 𝑞𝐾𝑠 𝜀0 𝑁𝐷 𝑉𝑅
◼ When NA >>ND, 𝐶𝑗 = = where 𝐶𝑗0 = and 𝑄 = 2𝐶𝑗0 ∅0 1+
2 ∅0 +𝑉𝑅 𝑉 2 ∅0 ∅0
1+ ∅𝑅
0
 Summary on MOSFET behavior
13

 Operation mode
 Saturationvs. Linear (Triode)
 As a switch (in Triode/Linear region)

 As an amplifier circuit (in Saturation region)

 Important parameters to characterize a MOSFET

𝑊
 Dimension: ; Bias voltage: VGS; Threshold voltage : VTH;
𝐿
 Transconductance gm
 Second order effect: Channel length modulation (CLM); Body effect
 MOSFET equations
14

 DC biasing of MOSFET:
 𝑉𝑔𝑠 < 𝑉𝑡ℎ : MOSFET is OFF, 𝐼𝐷 = 0
 𝑉𝑡ℎ < 𝑉𝑔𝑠 < 𝑉𝑑𝑠 + 𝑉𝑡ℎ : MOSFET turns ON in saturation
1 𝑊 2
◼ 𝐼𝐷 = 𝜇𝑛 𝐶𝑜𝑥 𝑉𝑔𝑠 − 𝑉𝑡ℎ : without channel length modulation (CLM)
2 𝐿
1 𝑊 2
◼ 𝐼𝐷 = 𝜇 𝐶 𝑉𝑔𝑠 − 𝑉𝑡ℎ 1 + 𝜆𝑉𝑑𝑠 : with CLM
2 𝑛 𝑜𝑥 𝐿
 𝑉𝑔𝑠 > 𝑉𝑑𝑠 + 𝑉𝑡ℎ : MOSFET turns ON in triode (linear) region
𝑊 2 1
◼ 𝐼𝐷 = 𝜇𝑛 𝐶𝑜𝑥 𝑉𝑔𝑠 − 𝑉𝑡ℎ 𝑉𝑑𝑠 − 𝑉𝑑𝑠
𝐿 2
𝑊
◼ 𝐼𝐷 = 𝜇𝑛 𝐶𝑜𝑥 𝑉𝑔𝑠 − 𝑉𝑡ℎ 𝑉𝑑𝑠 : deep triode region
𝐿
15

AC Analysis
 MOS Small-Signal Model
16

With channel length modulation With CLM & Body effect

𝛿𝐼𝐷 Also, body affect can be models as a

𝑔𝑚 = = 𝜇𝑛 𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇𝐻 ❑ Channel-length modulation can be
𝛿𝑉𝐺𝑆 𝛿𝑉𝐷𝑆 current source connected between D and S:
modeled by a resistor: 𝑟𝑜 = = 𝛿𝐼𝐷
❑ A small change Δ𝑉 = 𝑉𝐺𝑆 to the 𝛿𝐼𝐷
1 𝑔𝑚𝑏 =
gate-source voltage → Δ𝐼𝐷 = 𝑔𝑚 VGS 1 𝑊 ≈ 1/𝜆𝐼𝐷 𝛿𝑉𝐵𝑆
𝜇 𝐶 𝑉𝐺𝑆 −𝑉𝑇𝐻 2 .𝜆
2 𝑛 𝑜𝑥 𝐿 𝑊 𝛿𝑉𝑇𝐻
= 𝜇𝑛 𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇𝐻 −
1 𝑊 2 𝐿 𝛿𝑉𝐵𝑆
𝐼𝐷 = 2 𝜇𝑛 𝐶𝑜𝑥 𝐿
𝑉𝑔𝑠 − 𝑉𝑡ℎ 1 + 𝜆𝑉𝑑𝑠 = 𝑔𝑚 . 𝜂
 Complete MOS small-signal model
17

❖ The origin of these parasitic capacitances come from?

 MOSFET configuration
18

VDD

RD
Vout

Vin M1

Common Source Common Drain Common Gate

 Draw AC equivalent circuit
19
VDD

RD
Vout

Vin M1

Common Source Common Gate

Common Drain
20
 MOSFET summary (cont.)
21
 Small signal model

Basic small signal model + Channel length modulation +Channel length modulation + body effect

𝑊
• Transconductance: 𝑔𝑚 = 𝜇𝑛 𝐶𝑜𝑥 𝑉𝑔𝑠 − 𝑉𝑡ℎ (SATURATION EQUATION)
𝐿
1
• Output resistance: 𝑟𝑜 =
𝜆𝐼𝐷
 22

CHAPTER 3:
SINGLE & MULTISTAGE AMPLIFIER
ASSOC. PROF. LOAN PHAM-NGUYEN

Hà Nội, 9/10/2024
 Single and multiple stage amplifiers
23

 Common – Source (CS) stage

 CS stage with Resistive load
 CS stage with diode-connected load

 CS stage with current source load

 CS stage with Source Degeneration

 Source Follower (Common – Drain) (CD) stage

 Common – Gate (CG) stage
 Cascode stage
 Review MOSFET
24
Large signal analysis (DC): Small signal analysis (AC):
❖ Triode region:

 Bias:
◼ VGS>VTH
◼ VDS<VGS-VTH
𝑊 12
 𝐼𝐷 = 𝜇𝑛 𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇𝐻 𝑉𝐷𝑆 − 𝑉𝐷𝑆
𝐿 2

❖ Saturation region: ❖Without channel length modulation:

 Bias: 𝐼𝐷 = 𝑔𝑚 𝑉𝐺𝑆
𝑉
◼ VGS>VTH ❖Input impedance: 𝑍𝐼𝑁 = 𝐼𝑁 |𝑉 = 0
𝐼𝐼𝑁 𝑂𝑈𝑇
◼ VDS≥VGS-VTH 𝑉𝑂𝑈𝑇
1 𝑊 ❖Output impedance: 𝑍𝑂𝑈𝑇 = |
 𝐼𝐷 = 𝜇𝑛 𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇𝐻 2 𝐼𝑂𝑈𝑇 𝐼𝐼𝑁 = 0
2 𝐿
 Amplifiers: general considerations (cont.)
26

 Important aspects of amplifiers

 Single and multiple stage amplifiers
27

 Common – Source (CS) stage

 CS stage with Resistive load
 CS stage with diode-connected load

 CS stage with current source load

 CS stage with Source Degeneration

 Source Follower (Common – Drain) (CD) stage

 Common – Gate (CG) stage
 Cascode stage
 Single and multiple stage amplifiers
28
CS stage with CS stage with diode- CS stage with CS stage with Source
Resistive load connected load current source load Degeneration

VDD
VDD VDD VDD

RD
RD
M2 Vb M2
Vout
Vout
Vout Vout
Vin M1
Vin M1
Vin M1 Vin M1
RS
 Diode connected
29
 CS stage: CS stage with resistive load
30
❖ Sketch the output voltage (Vout)
as a function of input voltage.
Known Vin increases from zero.
VDD

RD
Vout

Vin M1
 Example
31
❖ Assuming that M1 is biased in
saturation, calculate the small-signal
voltage gain of the circuit

VDD

Iideal

Vout

Vin M1
 CS stage: CS stage with Diode-connected load
32

𝑉𝑋 1 1
= ||𝑟𝑂 ≈
𝐼𝑋 𝑔𝑚 𝑔𝑚
 CS stage: CS stage with Diode-connected load
33

❖ Assuming that M1 is biased in

saturation, calculate the small-
signal voltage gain of the circuit
VDD

M2

Vout

Vin M1
 CS stage: CS stage with current source load
34

❖ Assuming that M1 & M2 are biased

in saturation, calculate the small-
signal voltage gain of the circuit
VDD

Vb M2

Vout

Vin M1
 CS stage: CS stage with source degeneration
35

❖ Assuming that M1 is biased in

saturation, calculate the small-signal
voltage gain of the circuit
VDD

RD

Vout

Vin M1

RS
36

Common-Source stage
 Common-Source stage: CS stage with resistive load
37
❖ CS stage schematic: input signal to Gate and output signal at Drain
DC analysis:
𝑉𝑂𝑈𝑇 = 𝑉𝐷𝐷 − 𝐼𝐷 ∗ 𝑅𝐷

AC analysis:
❖ Neglected channel-length modulation (λ = 0):

𝜕𝑉𝑜𝑢𝑡
𝐴𝑣 = = −𝑔𝑚 𝑅𝐷
𝜕𝑉𝑖𝑛
❖ With channel-length modulation (λ ≠ 0):
𝐴𝑣 = −𝑔𝑚 (𝑅𝐷 ||𝑟𝑜 )
❖ Input impedance: 𝑍𝑖𝑛 ~ ∞
❖ Output impedance:𝑍𝑜𝑢𝑡 = (𝑅𝐷 ||𝑟𝑜 )
 Common-Source stage: CS stage with diode-connected load
38
 Common-Source stage: CS stage with diode-connected load
39
Small-signal model of diode-connected
❖ Impedance seen from Source of diode-connected:
𝑉 1
❖ If neglected body effect: 𝑋 = ||𝑟𝑜
𝐼𝑋 𝑔𝑚
𝑉𝑋 1
❖ With body effect: = ||𝑟𝑜
𝐼𝑋 𝑔𝑚+𝑔𝑚𝑏
diode-connected Equivalent resistor
NMOS and PMOS 1
||𝑟𝑜
𝑔𝑚

❖ Small-signal analysis:
If λ = 0, gmb2=0 Advantages: Gain independent with bias condition

1 (𝑊 Τ𝐿)1
𝐴𝑣 = −𝑔𝑚1 =− Disadvantages: low gain, limit output voltage swing, low Zout
𝑔𝑚2 𝑊 Τ𝐿 2
If λ = 0, gmb2 ≠ 0
1 (𝑊 Τ𝐿)1 1
𝐴𝑣 = −𝑔𝑚1 =−
𝑔𝑚2 + 𝑔𝑚𝑏2 𝑊 Τ𝐿 2 1 + ɳ
 Common-Source stage: CS stage with current-source load
40
❖ Ideal current source characteristics:
❖ + I = constant
❖+R→∞
❖ Characteristics of MOSFET in saturation:
PMOS connected as a If λ = 0:
current source 1 𝑊
❖ +𝐼𝐷 = 𝜇𝑛Cox 𝑉𝑏 − 𝑉𝑇𝐻 2 = constant
2 𝐿
❖ + Rout → ∞
If λ ≠ 0:
1 𝑊
❖ 𝐼𝐷 = 𝜇𝑛Cox 𝑉𝑏 − 𝑉𝑇𝐻 2(1 + λVDS)
2 𝐿
❖ Rout = 𝑟𝑜
NMOS connected as a
current sink
 Common-Source stage: CS stage with current-source load
41

Small-signal analysis:
If λ2 = 0:
𝐴𝑣 = −𝑔𝑚1 𝑟𝑜1
If λ2 ≠ 0:
𝐴𝑣 = −𝑔𝑚 1(𝑟01||𝑟02)
Input impedance: 𝑍𝑖𝑛 ~ ∞
Output impedance:
𝑍𝑜𝑢𝑡 = (𝑟01||𝑟𝑜2)
Advantages: Higher gain, Higher
voltage swing than diode-connected
Disadvantages: Need bias voltage
 Common-Source stage: CS stage with source degeneration
42

1 𝑊
𝐼𝐷 = 𝜇𝑛 𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇𝐻 2
2 𝐿
𝑉𝑂𝑈𝑇 = 𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷
𝑉𝐺𝑆 = 𝑉𝐼𝑁 − 𝐼𝐷 𝑅𝑆
𝑑𝑉𝑂𝑈𝑇 𝑅𝐷 ∗𝑑𝐼𝐷 𝑅𝐷
𝐴𝑉 = =− =− 1
𝑑𝑉𝐼𝑁 𝑑𝑉𝐼𝑁 +𝑅𝑆
𝑔𝑚

𝑍𝑖𝑛 ~ ∞
𝑍𝑜𝑢𝑡 = 1 + 𝑔𝑚 + 𝑔𝑚𝑏 𝑟0 𝑅𝑆 + 𝑟0 ||𝑅𝐷

Advantages: More linear gain, Reduce

temperature effect, High output impedance
Disadvantages: Lower gain
43
44
45

Source Follower stage

(Common – Drain)
 Source Follower:
46

Q: Tính Av của mạch CS như hình bên (cho

ro1=ro2=1MΩ) với trường hợp có tải R0
và không có tải R0=16Ω? Rút ra nhận xét
gì?

➔ cần bộ đệm (buffer) có ZIN lớn và ZOUT

nhỏ
 Source Follower (common drain)
47

❖ CD stage schematic: input signal at

Gate and output signal at Source
❖ Large signal analysis:
𝑉𝑂𝑈𝑇 = 𝐼𝐷 ∗ 𝑅𝑆
❖ Small signal analysis
𝑔𝑚𝑅𝑆
𝐴𝑣 =
1+ 𝑔𝑚+𝑔𝑚𝑏 𝑅𝑆
1
𝑍𝑜𝑢𝑡 = 1 1
𝑔𝑚+𝑔𝑚𝑏+𝑟 +𝑅
𝑜 𝑆

Advantages: Small ZOUT ; Gain is less

dependent on load ; Small ZOUT
Disadvantages: gm>>gmb ➔ Av ≤ 1;
Body effect cause VTH variation
48

Common – Gate stage

 Common Gate Stage
49
50
 Common – Gate stage:
51
CG stage schematic: input signal at
Source and output signal at Drain
❖ Large signal analysis:
𝑉𝑂𝑈𝑇 = 𝑉𝐷𝐷 − 𝐼𝐷 ∗ 𝑅𝑆
❖ Small signal analysis
𝐴𝑣 = 𝑔𝑚 1 + 𝜂 𝑅𝐷
𝑅𝐷 +𝑟0
Zin =
1+ 𝑔𝑚+𝑔𝑚𝑏 𝑟0
Zout = 1 + 𝑔𝑚 + 𝑔𝑚𝑏 𝑟0 𝑅𝑆 + 𝑟0 ||𝑅𝐷

High gain but low ZIN

Low ZIN and parasitic of VIN make a resistor divider
➔ Application in matching impedance 50Ω
52

Cascode stage
 Cascode stage:
53
The cascade of a CS stage and a CG
stage is called “cascode” topology
❖ DC bias:
M1 saturation: Vb ≥ Vin + VGS2 – VTH1
M2 saturation: Vout ≥ Vin + VGS2 – VTH1 – VTH2
❖ Small-signal analysis:
𝐴𝑣 = −𝐺𝑚 𝑍𝑂𝑈𝑇 Advantages:
𝐺𝑚 = 𝑔𝑚1 Increase ZOUT ➔ increase gain
𝑍𝑜𝑢𝑡 = 1 + 𝑔𝑚2 + 𝑔𝑚𝑏2 𝑟02 𝑟01 + 𝑟02 Disadvantages:
≈ 𝑔𝑚2 + 𝑔𝑚𝑏2 𝑟02𝑟01 Limited output voltage swing
Need bias voltage Vb
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 Impact of Rs/Rload to gain
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 Homework
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 2.5; 2.6; 2.7; 2.9; 2.11

 3.15; 3.16; 3.19; 3.23; 3.27
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