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Midsem

The document contains mid-semester examination questions for EE 210 at IIT Kanpur, focusing on the design and analysis of MOSFETs and BJTs in various configurations. It includes tasks such as calculating device parameters, determining drain currents, and analyzing circuit behaviors under specific conditions. The questions require a solid understanding of semiconductor physics and circuit design principles.
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0% found this document useful (0 votes)
11 views8 pages

Midsem

The document contains mid-semester examination questions for EE 210 at IIT Kanpur, focusing on the design and analysis of MOSFETs and BJTs in various configurations. It includes tasks such as calculating device parameters, determining drain currents, and analyzing circuit behaviors under specific conditions. The questions require a solid understanding of semiconductor physics and circuit design principles.
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Department of Electrical Engineering

Indian Institute of Technology, Kanpur

EE 210 MID-SEM P1 24.2.21

The fab line data for an n-channel MOSFET: NA = 1016 cm3, tox = 30 nm, VTN0 = 0.7 V, n = 430 cm2/V-
sec, and (, Cgs0, Cgd0) → 0. Other relevant data: VT = 26 mV, 0 = 8.854  1014 F/cm, r(Si) = 11.7,
r(SiO2) = 3.9, q = 1.6  1019 C, ni = 1.5  1010 cm3.
a) Design the values (in m) of W and L, such that with the device biased in saturation with the lowest
allowed values of the gate overdrive voltage and the corresponding VDS, it should have unity-gain
cutoff frequency (fT) of 5 GHz and device power dissipation of 100 nW. 8
b) If the designed device is biased with VG = 3 V, VD = 1.5 V, VS = 1 V, and VB = 0 V, determine the
drain current ID. 4
c) If the values of VG and VS are maintained as in part b), but now VD is changed to 3 V, determine the
required value of VB that will make the device operate with a body factor () of 0.1. 3
Department of Electrical Engineering
Indian Institute of Technology, Kanpur

EE 210 MID-SEM P2 24.2.21

VCC
All BJTs in the circuit shown are identical with (, VA) →  [for parts V0
a)-d)]. I1
R1
a) Show that I0 is a function only of VCC and RE, if R1 = R2. 4 R0
I0
b) If I0 = I1, how is RE related to R1 (or R2, since R1 = R2)? 2
c) If VCC = 5 V, determine R1 (= R2) and RE to give I0 = 1 mA. 2
d) What is V0,min? Is the value acceptable to you? Comment. 2 Q1 Q3
e) Only for this part, assuming  = 100, VA = 100 V, I0 and I1 remain at
1 mA, and using the values of R1 (= R2) and RE calculated in part c),
estimate the output resistance R0. 5 Q2
RE

R2
Department of Electrical Engineering
Indian Institute of Technology, Kanpur

EE 210 MID-SEM P3 24.2.21

VDD
In the BiMOS (combination of BJT and MOS) cascode current source
5V
shown in the figure, M1-M2 is a perfectly matched pair, and so is Q3-Q4. V0
Neglect DC base current, and assume that VDS  1. R0
IREF
Data: for M1-M2: VTN0 = 0.7 V, k N = 40 A/V2,  = 0.4 V1/2, 2F = 0.6 V; R
I0
for Q3-Q4:  = 100, VA = 100 V.
a) Show that R0  r04. Clearly highlight all the assumptions made in
arriving at this result. 5 Q3 Q4
b) Choose the values of IREF, R, and (W/L) of M1-M2, in order to have
R0 and V0,min of 1 G and 1 V respectively. 7
c) What is the most critical parameter and what should be its value for
the assumption made in the derivation of R0 [part a)] to hold? An M1 M2
error band of 5% is acceptable. 3
Department of Electrical Engineering
Indian Institute of Technology, Kanpur

EE 210 MID-SEM P4 24.2.21

VCC
A DC reference voltage (VREF) generator circuit is shown in the figure. For Q, 5V
assume  = 100, and neglect Early effect. The DC current source IREF is ideal. IREF
a) Choosing the base current of Q to be 20% of the current flowing through R1, 2.1 mA
VREF
design the values of R1 and R2 to produce VREF = 2 V. Caution: Do not use
equations blindly. 5
b) Quantitatively prove that the DC power of the circuit is a conserved quantity, R1
i.e., the DC power supplied by VCC is completely dissipated in the circuit. 4 R0
c) What is the output resistance (R0) of the designed voltage reference? Is it Q
acceptable? Why or why not? 6
R2

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