Agro-Technical and Technology

College (ATTC)
Menschen fuer Menschen Foundation

CHAPTER FIVE
Input/Output
BY
Mr. Chala Tesfaye
EET 4216 - Computer Architecture and Organization
 INPUT/OUTPUT PROBLEMS
❑ Wide variety of peripherals: Devices like keyboards, printers, monitors, and hard
drives, each with unique functions.

 Delivering different amounts of data

 At different speeds

 In different formats

❑ All slower than CPU and RAM

❑ Need I/O modules

❖ Manage communication between CPU and peripherals.

❖ Control data transfer speeds.

❖ Convert data into compatible formats for both the CPU and peripherals.
 INPUT/OUTPUT MODULE
❑ Interface to CPU and Memory:
❖ The CPU is the brain of the computer, and memory stores data temporarily for quick
access.

❖ The interface to the CPU and memory is like a communication bridge between the
Input/Output (I/O) modules and the CPU.

❖ When data from a peripheral (like a printer or hard drive) needs to be processed, it gets
transferred through this interface to the CPU.

❖ The CPU can then work on the data, store it in memory, or return it to the I/O device.

❖ This interface controls how the CPU reads and writes data from memory and manages
the flow between them.
 INPUT/OUTPUT MODULE
❑ Interface to One or More Peripherals:
❖ Peripherals (like a keyboard, mouse, or printer) need a way to communicate with the
computer. This is done through an interface to the I/O module.

❖ The interface to peripherals connects the I/O modules to different devices.

❖ It ensures that data can be sent back and forth between the computer and the
peripherals.

❖ These interfaces may work with multiple peripherals at once (like connecting a printer
and a keyboard at the same time), ensuring that data is properly directed to and from the
correct devices.
GENERIC MODEL OF I/O MODULE
 EXTERNAL DEVICES
❑ We can broadly classify peripheral devices into three categories:
❑ Human Readable Devices: These devices allow users to interact with the computer. They
display or take input that humans can understand.
❖ Video Display Terminal (VDT): The screen where you see the computer's output.
❖ Printers: Devices that print text or images on paper.
❑ Machine Readable Devices: These devices allow the computer to communicate with other
machines or equipment. They don't involve direct communication with the human user.
❖ Magnetic Disk: A storage device like a hard drive.
❖ Magnetic Tape: Used for storing large amounts of data.
❖ Sensors: Devices that detect changes (like temperature or motion).
❖ Actuators: Devices that perform physical actions, often used in robotics.
❑ Communication Devices: These devices help the computer exchange data with other
remote devices or systems.
❖ Modem: Allows the computer to connect to the internet via phone lines.
❖ Network Interface Card (NIC): Connects the computer to a network, such as the internet or a
LAN.
EXTERNAL DEVICE BLOCK DIAGRAM
 I/O MODULE FUNCTION
❑ Control and Timing: Coordinates the flow of data between the CPU and external
devices, ensuring proper synchronization.

❑ CPU Communication: Handles command decoding, data exchange, status reporting,

and address recognition between the I/O module and CPU.

❑ Device Communication: Manages the exchange of commands, status, and data between
the I/O module and peripherals.

❑ Data Buffering: Temporarily stores data to manage speed mismatches between I/O
devices and memory.

❑ Error Detection: Identifies and reports errors like mechanical malfunctions and
transmission issues during data transfer.
 I/O STEPS
❑ CPU checks I/O module device status – The CPU sends a request to the I/O module to
check whether the device is ready for communication.
❑ I/O module returns status – The I/O module responds with the current status of the
device (e.g., ready, busy, or error).
❑ If ready, CPU requests data transfer – If the device is ready, the CPU sends a command
to initiate data transfer.
❑ I/O module gets data from the device – The I/O module collects data from the
peripheral device (e.g., a keyboard, disk, or network interface).
❑ I/O module transfers data to CPU – The I/O module sends the retrieved data to the CPU
for processing.
❑ Variations for output, DMA, etc. – Different methods can be used for data transfer, such
as Direct Memory Access (DMA), which allows the I/O module to transfer data directly to
memory without CPU intervention.
 I/O MODULE DIAGRAM

❑ The I/O bus from the processor is connected to all peripheral interfaces.
❑ The processor places a device address on the address bus to communicate with specific devices.
❑ Each interface has an address decoder that monitors the address line and activates the path when
the device address is detected.
❑ The processor provides a function code in the control line, which includes control command,
output data, and input data.
 I/O MODULE DECISIONS
❑ Hide or reveal device properties to CPU – The I/O module can either simplify
communication by hiding device details from the CPU or allow direct interaction.

❑ Support multiple or single devices – Some I/O modules manage multiple devices,
while others handle just one.

❑ Control device functions or leave for CPU – The I/O module can handle tasks like
error checking and data formatting or let the CPU do them.

❑ Operating System (OS) decisions – The OS also influences I/O management. For
example, Unix treats most devices (printers, disks, keyboards) as files, making
access uniform.
 INPUT OUTPUT TECHNIQUES
❑ Modes of transfer
❖ Data Transfer between the central computer and I/O devices may be handled in a
variety of modes.

❖ Some modes use the CPU as an intermediate path, and others transfer the data
directly to and from the memory unit.

❖ Data transfer to and from peripherals may be handled in one of three possible modes.

✓ Programmed

✓ Interrupt driven

✓ Direct Memory Access (DMA)

THREE TECHNIQUES FOR INPUT OF A BLOCK OF DATA
 PROGRAMMED I/O
❑ Programmed I/O means the CPU directly manages the communication with input/output
(I/O) devices. Here's how it works:

❖ The CPU checks the status of the I/O device to see if it's ready.

❖ It sends commands to read from or write to the device.

❖ It transfers the data between the device and memory.

❑ However, during this process, the CPU has to wait for the I/O operation to finish, which
can waste its time, as it can't do other tasks until the operation is done.
 PROGRAMMED I/O - DETAIL
❑CPU requests I/O operation: The CPU asks the I/O module to perform a specific task
(e.g., reading or writing data).
❑I/O module operates: The I/O module then carries out the requested task with the device.

❑I/O module sets status bits: Once the operation is complete, the I/O module sets specific
status bits to indicate the task’s progress or completion.
❑CPU checks status bits periodically: The CPU doesn’t get an immediate notification.
Instead, it regularly checks the status bits to see if the operation is finished.
❑ The I/O module does not inform the CPU directly: The I/O module doesn’t send any
signals or alerts directly to the CPU when the task is done.
❑I/O module does not interrupt CPU: The I/O module doesn’t interrupt the CPU to notify
it about the operation's completion.
❑CPU may wait or come back later: The CPU can either wait for the operation to finish
or check back later.
 I/O COMMANDS
❑ CPU issues address: The CPU provides an address to specify which module (and
device, if there’s more than one device per module) it wants to communicate with.

❑ CPU issues command:

❖ Control: Tells the module what action to perform, such as “spin up the disk.”

❖ Test: Check the status of the device, for example, checking if the power is on or if
there’s an error.

❖ Read/Write: Directs the module to transfer data between the device and the CPU,
usually through a buffer.
 ADDRESSING I/O DEVICES
❑In programmed I/O, data transfer looks similar to memory access from the CPU’s
perspective.
❑Each device is assigned a unique identifier (address).
❑The CPU commands include the identifier (address) to specify which device it wants
to interact with.
 I/O MAPPING
❑ When the processor, main memory, and I/O devices share a common bus, there are two
modes of addressing: memory-mapped and isolated I/O.
❑ Memory Mapped I/O:
❖ Devices and memory share the same address space.
❖ I/O operations are handled like regular memory read/write operations.
❖ No special commands are needed for I/O.
❖ A large selection of memory access commands is available.

❑ Isolated I/O:
❖ Devices have a separate address space from memory.
❖ Requires I/O or memory select lines.
❖ Uses special commands for I/O.
❖ A limited set of commands is available.
 INTERRUPT DRIVEN I/O
Solves the problem of CPU waiting – CPU doesn’t waste time checking the device.
No need for repeated checks – CPU can do other tasks.
I/O module interrupts the CPU when ready – CPU responds only when needed.

❑ How It Works:

1️⃣ CPU sends a request to the I/O module.

2️⃣ CPU continues doing other work.
3️⃣ When the I/O module is ready, it sends an interrupt to the CPU.
4️⃣ CPU pauses, processes the I/O request and resumes its task.

Result: Faster and more efficient CPU operation!

 INTERRUPT DRIVEN I/O BASIC OPERATION
❑ CPU Issues Read Command – CPU tells the I/O module to read data.

❑ I/O Module Gets Data – The I/O module fetches data from the peripheral (device).

❑ I/O Module Interrupts CPU – Once the data is ready, the I/O module sends an interrupt
to the CPU.

❑ CPU Requests Data – The CPU then asks the I/O module for the data.

❑ I/O Module Transfers Data – The I/O module sends the data to the CPU.

❑ Result:

❖ CPU doesn't waste time waiting and can do other tasks.

❖ I/O module handles data transfer and notifies the CPU when ready.
 SIMPLE INTERRUPT PROCESSING

PSW (Program Status Word)

and PC (Program Counter)
 CPU VIEWPOINT
❑ Issue Read Command – CPU gives the read command to the I/O module.
❑ Do Other Work – CPU continues executing other instructions or tasks.
❑ Check for Interrupt – At the end of each instruction cycle, the CPU checks if there is
an interrupt signal.
❑ If Interrupted:

❖ Save Context: The CPU saves the current state (e.g., registers) to ensure it can
resume correctly after handling the interrupt.

❖ Process Interrupt: The CPU stops its current task and begins handling the interrupt.

❖ Fetch Data & Store: The CPU retrieves the data from the I/O module and stores it in
memory or uses it as needed.
CHANGES IN MEMORY AND REGISTERS FOR AN INTERRUPT
 DESIGN ISSUES IN INTERRUPT-DRIVEN I/O
1. Identifying the Interrupting Module:
❑ Different Lines for Each Module

❖ Issue: While theoretically possible, this method is impractical because it requires a

separate interrupt line for every device, which limits the number of devices that can be
connected and increases complexity.

❑ Software Polling

❖ Process: The CPU queries each device in turn to determine which one caused
the interrupt.

❖ Issue: It's slow and inefficient because the CPU has to check each module
individually.
 DESIGN ISSUES IN INTERRUPT-DRIVEN I/O
2. Identifying the Interrupting Module (Advanced Techniques):
❑ Daisy Chain or Hardware Polling:
▪ Process: An interrupt acknowledgment signal is sent down a chain of devices. The device
responsible for the interrupt places a vector (identifier) on the bus.

▪ Advantage: The CPU reads the vector from the bus to identify which device triggered the
interrupt and can then call the corresponding interrupt handler routine.
❑ Bus Mastering:
▪ Process: In systems like PCI (Peripheral Component Interconnect) or SCSI (Small
Computer System Interface), the device must first claim control of the bus (become the
bus master) before it can raise an interrupt.

▪ Advantage: Prevents conflicts and ensures that only the active bus master can interrupt
the CPU.
 DESIGN ISSUES IN INTERRUPT-DRIVEN I/O
3. Dealing with Multiple Interrupts:

❑ Priority Interrupts:

▪ Process: Each interrupt line is assigned a priority. Higher-priority interrupts can

interrupt lower-priority ones.

▪ Issue: This ensures that critical tasks are handled first, but it requires proper
management of priorities to avoid missing important tasks.

❑ Bus Mastering with Multiple Interrupts:

▪ Issue: When bus mastering is involved, only the current bus master is allowed to
interrupt. This is important to avoid conflicts when multiple devices might try to
interrupt the CPU at the same time.
 DIRECT MEMORY ACCESS (DMA)
❑ Need for DMA:
❖ Both interrupt-driven and programmed I/O require active CPU intervention during data
transfer.
❖ This results in:
o Limited transfer rate due to CPU involvement in every I/O operation.
o CPU is tied up and cannot perform other tasks while I/O is being handled.
❑ DMA Function:
❖ DMA is a solution to reduce CPU involvement in I/O operations.

❖ DMA Controller:

o It is an additional hardware module connected to the system's bus.

o It takes over from the CPU to manage I/O operations directly between memory and
peripheral devices.
❑ The CPU only initializes the DMA process, and once the transfer starts, the DMA
TYPICAL DMA MODULE DIAGRAM
 DMA OPERATION
❑ CPU Instructs DMA Controller: The CPU provides the following information to the DMA
controller:
❖ Read/Write operation (whether it's a read or write transfer).
❖ Device address (the address of the I/O device).
❖ Starting address of memory block for data (the memory location where data will be
transferred to/from).
❖ Amount of data to be transferred.
❑ CPU Continues with Other Work: After setting up the DMA controller, the CPU is free to
perform other tasks while the DMA controller handles the data transfer.

❑ DMA Controller Takes Over: The DMA controller directly manages the data transfer
between memory and the I/O device without CPU involvement.

❑ Interrupt on Completion: Once the transfer is complete, the DMA controller sends an
interrupt to the CPU, notifying it that the I/O operation is finished.
DMA TRANSFER CYCLE STEALING
❑ DMA Controller Takes Over Bus for a Cycle: The DMA controller temporarily
takes control of the system bus for one cycle to transfer data.
❑ Transfer of One Word of Data: During this cycle, a single word of data is
transferred between the I/O device and memory.
❑ No Interrupt: Unlike interrupt-driven I/O, cycle stealing doesn't cause an interrupt.
The CPU doesn't need to switch its context, meaning it continues execution without
being interrupted.
❑ CPU Suspended Just Before Accessing Bus: The CPU is paused just before it needs
to use the bus, typically:
❑ Before fetching an operand or data.
❑ Before writing data to memory.
❑ Impact on CPU: While the CPU is temporarily suspended during each cycle stealing
transfer, this process slows down the CPU somewhat but less significantly compared
to if the CPU were handling the entire data transfer itself.
DMA AND INTERRUPT BREAKPOINTS DURING AN INSTRUCTION CYCLE
 ASIDE
❑ Caching Memory and DMA: Cache memory stores frequently used data to make things faster
for the CPU.
❖ However, DMA (Direct Memory Access) directly transfers data between devices and memory,
bypassing the CPU.
❖ If the CPU cache has data being transferred by DMA, the CPU might end up using old or
incorrect data because the cache and memory may not match.
❑ On-Board Cache and DMA: Some devices have their on-board cache. If data is transferred
through DMA while it's in the cache, there can be data conflicts because the cache may not be
updated correctly with the new data.
❑ System Bus Availability: The system bus is shared between the CPU, DMA, and cache. If both
the CPU and DMA want to use the bus at the same time, it can cause a slowdown or bottleneck.
❖ DMA transfers can delay the CPU or cache updates since the bus is being used for the transfer.
 DMA CONFIGURATIONS (1)

❑ In a Single Bus, Detached DMA controller setup:

❖ I/O to DMA Transfer: The I/O device sends data to the DMA controller using the
bus.
❖ DMA to Memory Transfer: The DMA controller then transfers the data to the
memory, again using the bus.
❑ Since the CPU is suspended twice during this process:
❖ First, when waiting for the I/O device to send data to DMA.
❖ Second, when waiting for DMA to move data to memory.
 DMA CONFIGURATIONS (2)

❑ In a Single Bus, Integrated DMA Controller setup:

❖ DMA to Memory Transfer: The DMA controller moves data directly from the I/O
device to memory using the bus.
❖ The DMA controller can support multiple devices, allowing it to manage data transfers
for more than one I/O device.
❑ Since the CPU is suspended once during the process:
❖ The CPU is paused only while the DMA controller is transferring data to memory. The
CPU isn't interrupted multiple times, as the transfer process is more efficient.
 DMA CONFIGURATIONS (3)

❑ In a Separate I/O Bus setup:

❖ Dedicated Bus for I/O Devices: The I/O devices have their bus, which is separate from the
main memory bus.
❖ Bus Supports All DMA Devices: This bus is used by all DMA-enabled devices, allowing
efficient communication.
❖ DMA to Memory: Data is transferred directly from the I/O devices to memory via DMA.
❖ Single Suspension of CPU: The CPU is only paused once while the DMA controller handles
the transfer, so the CPU can continue its work with minimal interruption.
 EVOLUTION
❑ The evolution of I/O systems follows a progression that allows for more efficient
communication between the CPU, I/O devices, and memory.
❖ CPU Directly Controls I/O Devices: In the early systems, the CPU handled all
communication with I/O devices directly, which can be slow and inefficient.

❖ I/O Module (Controller) Added - Programmed I/O: To improve efficiency, an I/O

module (or controller) is introduced to manage I/O operations. The CPU still controls the
process but in a more organized manner, with the CPU managing each transfer step-by-step
(Programmed I/O).

❖ Interrupt-Driven I/O Service: To further reduce CPU involvement and improve

efficiency, the system uses interrupts. Instead of the CPU constantly checking devices
(polling), the devices notify the CPU when they need attention (interrupt-driven I/O).
 EVOLUTION
❖ DMA (Direct Memory Access): DMA allows I/O devices to transfer data directly
to/from memory without involving the CPU. This speeds up data transfers significantly
since the CPU is no longer needed for every data move.

❖ I/O Module Becomes a Processor (I/O Channel): At this stage, the I/O module becomes
more sophisticated, essentially acting as its processor. It can handle more complex
operations independently from the CPU, allowing for faster and more efficient processing
of I/O operations.

❖ I/O Module Has Memory and Becomes a Computer: Eventually, the I/O module can
even have its memory, becoming a small computer in its own right. It can handle tasks
like buffering, processing, and decision-making, further reducing the burden on the CPU
and enhancing overall system performance.
 I/O CHANNELS
❑ I/O Channels are a significant advancement in handling I/O operations in modern computer
systems.
❖ Sophisticated I/O Devices: As I/O devices become more advanced (e.g., 3D graphics cards),
they require more complex processing to handle data efficiently. These devices can process a lot
of data at once, and doing so through the CPU alone would slow down the system.
❖ CPU Instructs I/O Controller to Perform Transfer: Instead of having the CPU manage each
transfer of data, it gives instructions to the I/O controller. The CPU just sets up the transfer, but
the I/O controller handles the actual process.
❖ I/O Controller Does Entire Transfer: The I/O controller is designed to perform the entire data
transfer without further CPU intervention. This allows the CPU to focus on other tasks while the
I/O controller works on handling the data.
❖ Improved Speed:
o Takes Load Off CPU: Since the I/O controller is doing the heavy lifting, the CPU is freed
up to execute other instructions, which speeds up the overall system performance.
o Dedicated Processor is Faster: The I/O controller is typically a dedicated processor
optimized for handling I/O tasks, making it faster than having the CPU handle all I/O
transfers.
I/O CHANNEL ARCHITECTURE
 INTERFACING
❑ Interfacing in computing refers to the connection between devices and the system,
facilitating data exchange.
❖ Connecting Devices Together: Devices, such as I/O devices, processors, memory, and
peripherals, need to be connected in a way that allows them to communicate with each other.
This connection is vital for transferring data between devices.

❖ Is it Just a Bit of Wire?: In the simplest form, devices can be connected using wires (such as
cables), but this isn't enough for more complex data transfers. The wires need to carry signals
and data in a way that both devices can understand and process.

❖ Dedicated Processor/Memory/Buses?: For more advanced systems, dedicated processors,

memory, and buses are used to manage and optimize communication. These components work
together to ensure that data is transferred efficiently between devices. Buses serve as the
pathways through which data flows, and processors or memory help in managing or processing
this data.
 INTERFACING
❑ Examples of Interfacing Technologies:

❖ FireWire: A high-speed data transfer standard used for connecting devices like
cameras, external hard drives, and audio/video equipment to computers. It allows
fast and reliable data communication.

❖ InfiniBand: A high-performance, low-latency interconnect technology often used

in data centers and high-performance computing (HPC) environments. It's designed
for fast and scalable data transfer between devices.
THANK YOU