Digital ASIC Design

(EELE 5331)

Dr. Yushi Zhou

Electrical and Computer Engineering

Email: [email protected]
Layout and Packaging
• Design Rules
• Layout Skills
– Active devices
– Capacitors
– Resistors
– Shielding
– Other tips
• Packaging

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Process Design Rules-1
• Minimum width rules

• Minimum space rules

• Minimum extension rules

• Overlap rules

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Process Design Rules-2
Minimum widths

• Minimum width of polygon defines the limits of a fabrication

process

• Failure of obeying the rules results in open.

❑ An open circuit maybe created during fabrication
❑ A narrow path may be created during fabrication, causing EM
failure.

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Process Design Rules-3
Minimum spacing

• To avoid an unwanted short circuit between two polygons

during fabrication: S1>Smin, where Smin is the minimum width.

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Process Design Rules-4
Minimum Enclosure

• Minimum Enclosure defines the sufficient margin of

geometries surrounded by other masks

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Process Design Rules-5
Minimum Extension

• Minimum Extension defines some geometries must extend

beyond the edge of others by a minimum value.
• Example shown in the figure, has a minimum extension x1
beyond the active region to ensure proper operation of the
transistor. Yushi Zhou [email protected] 6
Process Design Rules-6

A layout of a differential amplifier

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 Latch-Up-1
conducting
current

• One of the critical design rules that affect functionality of the circuit.
• The base of each bipolar transistor is inevitably tied to the collector of
the other.
• Owing to the finite resistance of the n-well and the substrate, the
bases of Q₁ and Q₂ see a nonzero resistance to VDD and ground,
respectively. Yushi Zhou [email protected] 8
Latch-Up-2
• Fig(b) illustrates a positive feedback loop around Q₁ and Q₂.
• In fact, if a current is injected into node X such that Vx rises, then
IC2 increases, Vy falls, IC1 increases, and Vx rises further.
• If the loop gain is greater than or equal to unity, this phenomenon
continues until both transistors turn on completely, drawing an
enormous current from VDD and clamping VDD to around 0.9 V.
We say the circuit is latched up.
• The initial current required to trigger latch-up may be produced by
various sources in an integrated circuit.
• In the circuit, a large voltage swing at the drains of inverters can
therefore inject a significant displacement current into the n-well
or the substrate, initiating latch-up.
• A numerous layout technique can be used to avoid the violation.
You will see it later.
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Antenna

• If metal 1 interconnect having a large area is tied to the

small gate of MOSFET. The metal area acts as an antenna
during etching, collecting ions and rising in potential.
Eventually, damage the thin oxide layer.
• Gate oxide may break down. Both happens in metal 1 and
poly.

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l Rules – Digital Standard Cells
• Minimum dimensions of masks determine
transistor size (and hence speed, cost, and power)
• Feature size f = distance between source and drain
(length), e.g. 65nm, 45nm, 28nm, 10nm, etc.
– Set by minimum width of polysilicon
• Feature size improves 30% every 3 years or so
• Normalize for feature size when describing design
rules
• Express rules in terms of l = f/2
– E.g. l = 0.3 mm in 0.6 mm process
– Under 180nm, this rule will not be applied
– But it is still useful to understand the layout

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Inverter Layout
• Transistor dimensions specified as Width / Length
– Minimum size is 4l / 2l, sometimes called 1 unit
– In f = 0.6 mm process, this is 1.2 mm wide, 0.6 mm long
– Standard cell layout: from top → bottom, VDD, P+, N+ and
GND

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Example: NAND3
• Horizontal N-diffusion and p-diffusion strips
• Vertical polysilicon gates
• Metal1 VDD rail at top
• Metal1 GND rail at bottom
• 32 l by 40 l

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Stick Diagram
• Symbolic layout
• No need to draw the logic gates to scale
• Fast way to plan cells
• Easy way to estimate the area
VDD VDD
A A B C
metal1
c poly
ndiff
pdiff
Y
Y contact

GND GND
INV NAND3

14
Wiring Tracks
• A wiring track is the space required for a wire
– 4 l width, 4 l spacing from neighbor = 8 l pitch
• Transistors also consume one wiring track

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Area Estimation
• Estimate area by counting wiring tracks
– Multiply by 8 to express in λ
1

2
3 48λ
40 l
NAND 3 4

6
32 l

32λ 1 2 3 4

16
Area: 32*48 = 1536 λ2
Example: OAI3(3 input OR, AND, INV)
Function: 𝑌 = (A+ B+ C)D

VDD
A B C D

76 tracks =
48 l
56
Y

GND
5 tracks =
40 l

Area: 40 * 56 = 2240 λ2
17
Standard Cells - Abutment
• Uniform cell height
• Uniform well height
• M1 VDD and GND rails
• M2 Access to I/Os
• Well / substrate taps
• Exploits regularity

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Example
• Customized digital cells

VDD

GND
VDD
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Layout of A Transistor
• Multi-fingers
❑ Reduce gate resistance
• Symmetry
❑ Improve matching
• Interdigitate
❑ Improve matching

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Example

(a)

M1 Mn
(b)
• Figure (a) is equivalent to (b).
• S/D and gate see large resistance, e.g. 7.8±2.5 Ω/ for
poly and p+ region, and 6.8±2.5 Ω/ for n+ region in 0.18
um process.
• Non-uniform current from M1 to Mn. M1 carry much
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higher current than Mn.
Multi Fingers - 1

• Reduce both the S/D junction area (about 2) and the gate
resistance(~ a factor of 4) by one fold
• Multiple “fingers” is suitable for very wide devices.
• Rule of Thumb:
The width of each finger is chosen such that the gate resistance of
the finger is less than .
Note: For low noise applications, 1/5 or 1/10 is fine.
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Multi Fingers -2

• The layout of a cascode circuit can be simplified if the

input device and the cascode device have equal widths.
• The drain of M1 and the source of M2 can share the same
junction.
• This junction does not need a contact window, which is
quite small to improve HF performance.
• Wide cascode device may be needed to add fingers.
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Symmetry

• Asymmetries may lead to inevitable mismatch, thus introducing

input-referred offsets, and limiting the minimum signal level.
• Two plausible solutions in (c) and (d).
• Much severe impacts for analog circuits but less effects for digital
circuits.
• Keeping same orientation of devices is preferable.
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Gate Shadowing

different

• The implant is tilted by about 7 degree to avoid

channeling
• A small asymmetry between source and drain side
diffusions
• The first topology is preferable
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Adding “Dummy” Devices

same
• Almost 50% of devices in mixed-signal circuit needs dummy
devices to reduce mismatch, e.g. dummy poly, dummy
resistors, etc.
• In complex circuits, such measures cannot be easily applied.
• We emphasize the importance of the axis of symmetry.

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Interdigitated Devices

2 3
[Hastings]
• Interdigitated 8 elements for two patterns: AABBAABB or
ABBAABBA.

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Layout of Resistors
• Poly resistor
• Diffusion resistor
• Layout techniques

130 nm process

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Silicide Poly Resistor

• Silicide process is designed to reduce resistance. It is widely

used in poly contacts.
• High linear, low capacitance to the substrate, small resistance,
e.g. R =8Ω in 0.18 um process.

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Non-Silicide Poly Resistor

Silicide blocker

• R =50Ω to a few hundred ohms per square in 0.18 um

process

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Diffusion Resistors-1

• N-well, source/drain p+ or n+ material, silicided

polysilicon, or metal with R decreasing in this order.
• N-well
- Vary a large fraction, 40% with process.
- Depends on the width of resistor.
- Depends on n-well-substrate voltage difference.
- Large parasitic capacitance.
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Diffusion Resistors-2

– Parasitic capacitance: non-linear junction capacitance to substrate

– Where VR is reverse biasing voltage, phi is build-in potential, Cj0 is

junction cap at zero reverse biasing voltage.
– N-well resistor are quite noisy since a) all noise from substrate directly
coupled to the resistors, b) if time-varying current flowing through n-
well resistor, it interacts with the substrate through junction capacitor.

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Layout of Resistors-1

• Resistors are usually decomposed into shorter units that laid

out in parallel and connected in series. Each segment should
be long enough to avoid large impact from both ends.
• From the viewpoint of matching and reproducibility, the
structure is preferable to “serpentine” topologies.
• The sheet resistance varies with temperature and process.
Around 0.1%/°C and less than 20% process variation.
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Layout of Resistors-2

• Interdigitated devices minimize the effects along x-axis.

• Dummy resistors are often preferable. Depending on the
technology, multiple dummy may be necessitated.

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Layout of Capacitors
• Key parameters
❑ Linearity: more important in analog design.
❑ Parasitic capacitance to substrate(bottom-plate.
parasitic cap): decrease the total capacitance.
❑ Series resistance: determine the quality factor.
• Types of Capacitors
❑ Polysilicon-diffusion
❑ Metal-Metal : MIM cap, vncap
❑ Metal-polysilicon, etc.

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Polysilicon-Diffusion Capacitor

C1

Cp
• More common in analog design.
• Linearity: moderate.
• Capacitance: C1 & Cp

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Mental-Metal Capacitor
• Formed by metal layers in the
factor of sandwiches or inter-
fingers.
• Linearity: good
• Fig. (d) has highest capacitance
density, and smallest process
variation.
• CP/C determines the topology.

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Metal-Insulator-Metal Capacitor

Sandwich

Example of 130 nm
• Good linearity.
• Moderate capacitance density.
• Poor accuracy.
• Not allowed wiring above and below the metals to increase the accuracy.
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Vertical Natural Capacitor

• Good linearity.
• Moderate capacitance density.
• High accuracy.

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Layout of Capacitors-1

Gradient
Y-axis

Gradient x-axis

• Matched capacitors: common-centroid-structure to minimize the

process gradient.

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Layout of Capacitors-2

dummy

• Unit cap is always preferable.

• Dummy cap is often preferable as well.
• Capacitors are sensitive to interconnections, thus some error may
adds to our desired value.
• Exp.:C1/C2=8, so make one C2, and replicate 8 C2 to form C1.
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Shielding and Grounding -1
How to prevent noise from other parts?
• Capacitive coupling
• Inductive coupling
• Substrate current

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Shielding and Grounding -2

• Sensitive signals can be “shielded” in the layout

- shielding by ground is better than spacing
- introduce capacitance and complex wiring

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Shielding and Grounding -3
• Different shielding

a) Inter-connect shielding; b) P+ guarding ring

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Shielding and Grounding -4
• Double guard rings
N+ collect noises from electrons
• Protect the critical circuits
• Prevent latch-up
P+
Collect noise
from holes

Vdd Gnd
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Other Layout Tips - 1
• Vias

a) Bad via design: high resistance, high current density on a single via.
b) Good via design: low resistance, current is distributed.

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Other Layout Tips - 2
• Latch-up prevention
a) Reduce pnpn bipolar gain: make P- substrate contact big and close to NFET. And
make Nwell contact big and close to the PFET.
b) Use guard ring for I/O transistors as below:

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 Other Layout Tips - 5
• Antenna prevention

• Add a tie-down device to build a discharge path to prevent polysilicon gate

• Break long metal wire to a several short segments.

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Pattern Density - 1
• Pattern density: percentage of area covered by metal or polysilicon
shapes on particular level, e.g. Max. and Min.
a) Global percentage coverage of level.
b) Local percentage of smaller areas .
• Why do we need pattern density?
• Because manufacture requires uniform thickness through the
chip for critical photolithography, etch, and planarization
process steps.

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Pattern Density - 2
• Auto fill or manual fill
• Auto fill works for most of digital design.
• Whereas, manual fill is usually required.
• Shape
• Should be DRC clean.

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Pattern Density - 3
• Examples of 130 nm
• Global

• Local

• Global density check entire chip.

• Local density check every step
when doing layout based upon
the tile size.
• You may pass global density but
fail local density requirement.
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Packaging Requirements

• Electrical: low parasitic, which affects the signal performance in

high speed applications.
• Mechanical: robust and reliable, which affect the lifetime of the
chip.
• Thermal: efficiently remove the heat generating from the operation
of the circuit, which also affects the reliability of the chip.
• Economical: must be cheap.

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Packaging Requirements
• Bond pad

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Packaging Requirements
• Flip chip
• contains a metal ground plane to which the die can attached
by conductive epoxy.

Die

Solder bumps
Interconnect
layers

Substrate

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Package to Board Connection

(a) Through-Hole Mounting (b) Surface Mount

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Most of slides and figures are from Dr. B. Razavi’s book. Some of
the contents are from Dr. F. Yuan’s notes. We thank to be
allowed to share these resources.

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