Scribd
Upload
5 views

Testing Unit 1 part 3

The document discusses sequential controllability and observability calculations in digital circuits, detailing how these measures are determined through the interaction of signals and storage elements. It also covers implications in circuit logic, distinguishing between direct and indirect implications, and introduces algorithms like the D-algorithm and PODEM for test generation. Additionally, it highlights fanout-oriented test generation to optimize decision points in circuit testing.

Uploaded by

Akash Rajput
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
5 views

Testing Unit 1 part 3

The document discusses sequential controllability and observability calculations in digital circuits, detailing how these measures are determined through the interaction of signals and storage elements. It also covers implications in circuit logic, distinguishing between direct and indirect implications, and introduces algorithms like the D-algorithm and PODEM for test generation. Additionally, it highlights fanout-oriented test generation to optimize decision points in circuit testing.

Uploaded by

Akash Rajput
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 26

2

3
4
5
Sequential Controllability and Observability Calculation
• Sequential controllability and observability measures are calculated in a
similar manner as combinational measures,
• Combinational measure:1 is added as we move from one level of logic gate
to another.
• Sequential measure: 1 is added when a signal passes through a storage
element.

Asynchronous reset
+ ve edge triggered clock
• CC0(q) - measures how many signals in the circuit must be set to control
q to 0.
• SC0(q) - measures how many flip-flops in the circuit must be clocked to
set q to 0.

• CC0(q)
• d = 0, clk = 0 to 1, r = 0
r = 1, clk = 0
• r = 1, clk = 0 because clk pulse is not applied to clk, 1 is not added
to the sequential controllability.
CO(d) & SO (d)
d can be observed at q by holding the reset signal r at 0 and apply clk 0
to 1.
CO(r) & SO(r) asynchronous reset
r can be observed by first setting q to 1 & then holding clk
at the in active state 0.

CO (ck) & SO(ck) two ways are there to indirectly observe the clk
signal at q.
1. q =1 r =0 d = 0 apply clk signal
2. q = 0 r = 0 d = 1 apply clk signal
Implications
Implication is the process of determining the logic values that appear at
various lines of a circuit as a consequence of the values assigned to some of
its lines.

Two types

Direct implications
determines the value at an input or an output of a circuit element,
given the values assigned to the elements inputs & outputs.

Indirect implications
determines the value at a circuit line ci given the values at lines other
than the inputs & outputs of the circuit elements that are directly connected
to ci.
g = 1 k= 1

f=1 Direct Implications

f=1 x=1 Indirect Implications


Two types of Direct Implication operation

Forward Implication - only proceeds from a line to line directly in its


fanout.
Backward Implication - only proceeds from a line to line directly in its
fanin.
perform one input at a time.
14
D - Algorithm
The D – algorithm tries to propagate a D or D of the target fault to a
primary output.
Sensitized path based algorithm D-Algorithm
f SA0 f SA0

D-algorithm
f SA1
D-algorithm h SA1 D-algorithm b SA0

17
X5 SA0

18
19
20
21
22
PODEM Algorithm
Path oriented decision making algorithm.

D – algorithm – decision space is the entire circuit


every internal gate could be a decision point.

Number of primary inputs less than the number of gates in the circuit.

Makes decision only at primary inputs rather than at internal nodes of the
circuit.

23
24
25
FAN
Fanout – oriented test generation
To reduce the number of decision points FAN first identifies the headlines in
the ckt.

K=0 m=1
Objective Z= 1
a= 0 b=1 c= 1
PODEM a=1 c=1 d=1 e=1 f=1
b=0 conflict will occur
26
FAN x=1 y=1

You might also like