Computer

Architecture
CH4 Processor Microarchitecture (I)

Prof. Ren-Shuo Liu

NTHU EE
Outline
• Background
• Single-cycle design
• Pipelined design

2
Processor

stdin stdout

1~2 billion transistors in a modern processor

3
Processor

D[n:1] Q[n:1]
Non-clocked elements
D = f(Q, stdin) Clocked Elements
(D flip-flops)
clk

Develop D Update Q

Time
4
Processor
memory memory
M M2
R 1 R
R
1 f1
2 f2
3 f3 = R
M
1
1 f1

M2
=
R
2
f2

D[m:1] Q[n:1] R
Non-clocked elements 3 f3
D = f(Q, stdin) Clocked Elements
(D flip-flops)
clk

5
Quiz 4-1 Circuit Speed

6
Simplified Processor Example
• Single-cycled
• Simplified instruction (sub)set
• Memory access
• lw, sw
• Arithmetic/logical
• add, sub, and, or, slt
• Control transfer
• beq, j

7
Building Blocks
• Memory
• Instruction memory
• Data memory
• Register ($0 ~ $31) memory
• Sign extender
• Shifter (fixed shift amount)
• ALU (as described in CH3)

8
Memory
• Read-only memory (ROM)

• Random access memory (RAM)

R enable
• Multi-port RAM R
addr 1
R
data 1

R R
R enable R enable addr 2 data 2
R R R/W R
addr data addr data W
addr
W W
data data
W enable W enable

9
Sign Extender and Shifter

8-bit signed integer

4-bit signed integer

8-bit unsigned integer 8-bit unsigned integer

(fixed shift amount)
0
0

10
Rough Processor Design

P
C

11
Rough Processor Design (Cont'd)
Multiplexers are used
but not shown

P
C

12
Instruction Fetching Hardware
N

N R enable
PC R
addr
R 32
data 32-bit instruction

Instruction Memory
(e.g., 2N B ROM)

N can be up to 32

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 Instruction Fetching Hardware
31:26 25:21 20:16 15:11 10:6 5:0
R-type 0 rs rt rd shamt funct

Load/Store 35 or 43 rs rt address

Branch 4 rs rt address

Jump 2 address_2
[31:26] 6
op
[25:21] 5
rs • All these fields are generated
[20:16] 5 regardless of instruction types
32 rt
ROM
[15:11] 5
rd • Depending on the op field,
[10:6] 5 some fields turn out to be
shamt
[10:0] 5
meaningless and are not
funct
actually used
[15:0] 5
address
[25:0] 26 14
address_2
Branch Related Hardware

rs1

rs2

address

15
R-Type and Load/Store Related
Hardware
rs

rt

rd

address

16
Datapath with Control
(Except for Jump)

funct
op Control

rs1
PC
rs2
rd

address

17
Control funct
op Control

rs1
PC

• PCSrc
rs2
rd

• 1: if (op==beq) && (zero==1)

• 0: otherwise
address

• RegWrite
• 1: if (op==lw) || (op==R-type)
• 0: otherwise

18
Control (Cont'd) funct
op Control

rs
PC

• ALUSrc rt
rd M
u
x

• 1: if (op==lw || op==sw) RegDst

• 0: otherwise address

• ALU operation
op Operation ALU function
lw load word add
sw store word add
beq branch equal subtract
R-type add add
subtract subtract
AND AND
OR OR
set-on-less-than set-on-less-than
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Control (Cont'd) funct
op Control

rs
PC

• MemtoReg rt
rd M
u
x

• 1: if (op==lw) RegDst

• 0: otherwise address

• MemWrite
• 1: if (op==sw)
• 0: otherwise
• MemRead
• 1: if (op==lw)
• 0: otherwise

20
Recap
D

funct
op Control

rs1 C G B
PC
rs2 E
rd

RegDst

F
address
H

21
Executing R-Type Instructions

22
Executing a Load Instruction

23
Executing the BEQ Instruction

24
Performance Concerns
• Critical path determines clock period
• Load instruction corresponds to the critical path
• Instruction memory → register file → ALU → data memory →
register file
• Setting different clock periods for different instructions
is not a feasible solution
• Violates the "making the common case fast" principle
• We will improve performance by pipelining

25
Outline
• Background
• Single-cycle design
• Pipelined design

26