I/O Interface

Need:
* Peripheral are electromechanical or electro magnetic, but CPU and memory are electronic
devices. The signal conversion may be required
*I/O Devices have slower data transfer rates.
*Data codes and formats in I/O devices are different from CPU and Memory
*All the devices are different from each other

AB
CPU CB
DB

Interface Interface Interface Interface

K/B M MD P
 Isolated Vs Memory mapped I/O

As a CPU needs to communicate with the various memory and input-output devices (I/O) as we know data
between the processor and these devices flow with the help of the system bus. There are three ways in which
system bus can be allotted to them :
1.Separate set of address, control and data bus to I/O and memory.
2.Have common bus (data and address) for I/O and memory but separate control lines.
3.Have common bus (data, address, and control) for I/O and memory.
 Isolated I/O

The CPU has common bus(data and address) for I/O and memory but separate read and write control lines for
I/O. So when CPU decode instruction then if data is for I/O then it places the address on the address line and set
I/O read or write control line on due to which data transfer occurs between CPU and I/O. As the address space
of memory and I/O is isolated and the name is so. The address for I/O here is called ports. Here we have
different read-write instruction for both I/O and memory.
 Memory Mapped I/O

In this case every bus in common due to which the same set of instructions work for memory and I/O. Hence we
manipulate I/O same as memory and both have same address space, due to which addressing capability of
memory become less because some part is occupied by the I/O.
 Isolated Vs Memory mapped I/O

Isolated I/O Memory Mapped I/O

Memory and I/O have separate address space Both have same address space

Due to addition of I/O addressable memory become less for

All address can be used by the memory
memory

Separate instruction control read and write operation in I/O

Same instructions can control both I/O and Memory
and Memory

In this I/O address are called ports. Normal memory address are for both

More efficient due to separate buses Lesser efficient

Larger in size due to more buses Smaller in size

It is complex due to separate logic is used to control both. Simpler logic is used as I/O is also treated as memory only.

*** Strength, Limitations and Applications of Isolated and Memory-Mapped I/O

 Serial Vs Parallel

Serial Parallel

Shift Register No SR

Burst Error Bit Error

Less Expensive Expensive

Less Reliable More Reliable

More Distance Less distance

 Synchronous Data Transfer

In Synchronous Data Transfer, the sending and receiving units are enabled with the same clock
signal. It is possible between two units when each of them knows the behavior of the other. The
master performs a sequence of instructions for data transfer in a predefined order. All these actions
are synchronized with the common clock. The master is designed to supply the data at a time when
the slave is definitely ready for it.
 Asynchronous Data Transfer

Asynchronous input/output (I/O) synchronization is a technique used in computer organization to

manage the transfer of data between the central processing unit (CPU) and external devices. In
asynchronous I/O synchronization, data transfer occurs at an unpredictable rate, with no fixed timing
or synchronization between the CPU and external devices.

Asynchronous input output is a form of input output processing that allows other devices to do
processing before the transmission or data transfer is done. Problem faced in asynchronous input output
synchronization – It is not sure that the data on the data bus is fresh or not as their no time slot for
sending or receiving data. This problem is solved by following mechanism:

Strobe
Handshaking
 Asynchronous Data Transfer

Asynchronous input/output (I/O) In asynchronous I/O synchronization, data transfer occurs at an

unpredictable rate, with no fixed timing or synchronization between the CPU and external devices.

Asynchronous input output is a form of input output processing that allows other devices to do
processing before the transmission or data transfer is done. Problem faced in asynchronous input output
synchronization – It is not sure that the data on the data bus is fresh or not as their no time slot for
sending or receiving data. This problem is solved by following mechanism:

Strobe
Handshaking
 Asynchronous Data Transfer

Source initiated Strobe – When source initiates the process of data transfer. Strobe is just a signal
(i) First, source puts data on the data bus and ON the strobe signal. (ii) Destination on seeing the ON
signal of strobe, read data from the data bus. (iii) After reading data from the data bus by
destination, strobe gets OFF.

Destination initiated signal – When destination initiates the process of data transfer

(i) First, the destination ON the strobe signal to ensure the source to put the fresh data on the data
bus. (ii) Source on seeing the ON signal puts fresh data on the data bus. (iii) Destination reads the
data from the data bus and strobe gets OFF signal.
 Asynchronous Data Transfer
Problems faced in Strobe based asynchronous input output –
1.In Source initiated Strobe, it is assumed that destination has read the data from the data bus but
there is no surety.
2.In Destination initiated Strobe, it is assumed that source has put the data on the data bus but there is
no surety.

Source initiated Handshaking – When source initiates the data transfer process. It consists of
signals: DATA VALID: if ON tells data on the data bus is valid otherwise invalid. DATA
ACCEPTED: if ON tells data is accepted otherwise not accepted.

(i) Source places data on the data bus and enable Data valid signal. (ii) Destination accepts data
from the data bus and enable Data accepted signal. (iii) After this, disable Data valid signal means
data on data bus is invalid now. (iv) Disable Data accepted signal and the process ends. Now there
is surety that destination has read the data from the data bus through data accepted signal.
 Asynchronous Data Transfer
Problems faced in Strobe based asynchronous input output –
1.In Source initiated Strobe, it is assumed that destination has read the data from the data bus but
there is no surety.
2.In Destination initiated Strobe, it is assumed that source has put the data on the data bus but there is
no surety.

Destination initiated Handshaking – When destination initiates the process of data transfer.
REQUEST FOR DATA: if ON requests for putting data on the data bus. DATA VALID: if ON tells
data is valid on the data bus otherwise invalid data.

(i) When destination is ready to receive data, Request for Data signal gets activated. (ii) source in
response puts data on the data bus and enabled Data valid signal. (iii) Destination then accepts
data from the data bus and after accepting data, disabled Request for Data signal. (iv) At last, Data
valid signal gets disabled means data on the data bus is no more valid data. Now there is surety
that source has put the data on the data bus through data valid signal.