Slide 2
Slide 2
❑ Computer architecture
➢ Represented in abstract layers to manage complexity
➢ ISA = what the computer does; Organization = how the ISA is implemented;
Realization = implementation of the ISA on specific integrated circuits.
❑ Computer performance
➢ Is reciprocal of CPU time
➢ Also follows the classical CPU performance equation
Hardware
(implementation of
the instruction set)
❑ Stored program
➢ A program is written as a sequence of instructions,
which are stored in a memory, in conjunction
with data, as binary bits.
➢ Instructions are automatically fetched, decoded,
and executed one by one.
1. Data Storage
❑ Design principles:
1. Simplicity favors regularity
2. Make the common case fast
3. Smaller is faster
4. Good design demands good compromises
CISC RISC
Many instructions and addressing Few instructions and addressing
modes modes
Single instruction performs Simple instructions, combined by
complex operation SW to perform complex operations
Smaller program size Larger program size
Complex implementation Easier to build/optimize hardware
RISC-V, Sun SPARC, HP PA-RISC,
Intel, AMD, Cyrix
IBM PowerPC
❑ Storage Architecture
❑ General Purpose Register Architecture
❑ Accumulator architecture:
➢ One operand is implicitly in the accumulator.
Examples: IBM 701, DEC PDP-8.
❑ Memory-memory architecture:
➢ All operands in memory. Example: DEC VAX.
Storage Architecture: GPR Architecture
❑ For modern processors (after 1980):
➢ General-Purpose Register (GPR) is the most common choice for storage
design.
➢ RISC computers typically uses Register-Register (Load/Store) design
E.g. RISC-V, ARM
➢ CISC computers use a mixture of Register-Register and Register-Memory
E.g. IA32.
❑ Design question
➢ How many GPRs should be sufficient?
➢ Design principle #3: smaller is faster.
Aspect #2 – Memory Addressing Mode
Big-endian: Little-endian:
Most significant byte stored in Least significant byte stored in
lowest address. lowest address.
MSB LSB MSB LSB
Address 0 1 2 3 Address 3 2 1 0
int A, B, C;
store 0 B C = A + B;
4
8 C
load 12 A
16
R0 ← Mem[12]
. . R1 ← Mem[4]
. .
Up to232 bytes . .
R2 ← R0 * R1
organized as 230
4-byte words; 32-bit words Mem[8] ← R2
addresses of
consecutive words
differ by 4.
Memory
RISC-V general registers
Human-friendly
symbolic names ABI name Register Number Usage
in assembly code zero x0 Constant value 0
ra x1 Return address
sp x2 Stack pointer
gp x3 Global pointer
tp x4 Thread pointer
t0-2 x5-7 Temporaries
s0/fp x8 Saved register / Frame pointer
s1 x9 Saved register
a0-1 x10-11 Function arguments / return
values
a2-7 x12-17 Function arguments
s2-11 x18-27 Saved registers
Numbers t3-6 x28-31 Temporaries
hardware
understands
More on RISC-V registers
❑ There are other registers!
➢ Not accessible to user (no name/number).
registers .
.
.
Aspect #3 – Operations in Instructions
Set
❑ Standard Operations in an Instruction Set
❑ Frequently Used Instructions
❑ Things to be decided:
➢ Number of registers
➢ Number of addressing modes
➢ Instruction length
➢ Number of operands in an instruction
❑ Fixed-length instructions.
➢ Fixed number of operands, with addressing modes (if options exist) specified
as part of the opcode → largest code size.
➢ Allow for easy fetch and decode + simplify pipelining and parallelism → best
performance.
❑ Hybrid instructions.
➢ Has multiple formats: fixed-length plus one or two variable-length
instructions.
➢ Improving the variability in size and work of the variable-length architecture
while reducing the code size of fixed-length counterpart.
Aspect #5 – The role of compilers
❑ Instruction simplicity
➢ Special features that “match” a language construct (e.g. FOR and CASE
statements) or a kernel function often make the compiler work more.
➢ “Provide primitives, not solutions” – compiler works best with a minimalist
instruction set.
Summary
❑ ISA design is hard
➢ Adhere to 4 qualitative principles
➢ Applying quantitative method