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VLSI Intro

Rajendra has 1.5 years of experience in cybersecurity, focusing on security incident monitoring and vulnerability assessments, with proficiency in tools like Wireshark and programming languages like Python. The document also explains VLSI concepts, including basic and universal gates, combinational and sequential circuits, multiplexers, and various design files used in VLSI design. Additionally, it covers static timing analysis inputs relevant to digital design.

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Rajendra Raj
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3 views4 pages

VLSI Intro

Rajendra has 1.5 years of experience in cybersecurity, focusing on security incident monitoring and vulnerability assessments, with proficiency in tools like Wireshark and programming languages like Python. The document also explains VLSI concepts, including basic and universal gates, combinational and sequential circuits, multiplexers, and various design files used in VLSI design. Additionally, it covers static timing analysis inputs relevant to digital design.

Uploaded by

Rajendra Raj
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as RTF, PDF, TXT or read online on Scribd
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Introduction

Hello,

My name is Rajendra.

I have 1.5 years of experience in the field of cybersecurity domain at Invofivion. and I am responsible for
monitoring and analyzing security incidents, conducting vulnerability assessments, and implementing
security policies to protect our systems and data. I have hands-on experience with various security tools
such as Wireshark, Nessus, Metasploit, and Burp Suite, and I'm proficient in programming languages like
Python and Java.

And i Completed my Btech in Electronics and Communication Engineering with aggregate of 75 percent
in SV University Tirupati.

And i Have done my intern at ECIL hyderabad by creating Electronic voting machine by using Verilog and
VHDL code.

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What is VLSI?

VLSI, or Very Large Scale Integration, is a process in semiconductor technology where an extremely large
number of transistors are integrated into a single chip. This allows for the creation of complex electronic
circuits and systems within a compact space.

System Specification –>Architecture Design-> Logic Design–> Circuit Design–> Physical Design–
>[(partitioning–>chip planning–>placement–>Signal Routing–>Time Closure)]–> Verification and Testing.

––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––

what are basic gates and universal gates in VLSI?

Basic Gates:

AND Gate –>Output High(True) only if all inputs are true(1)

OR Gate –>Output High(True) if atleast one input is true(1)

NOT Gate –>Outputs the inverse of the input.

Universal Gates:

NAND Gate –> Output Low(false) only if all inputs are true (1)

NOR Gate –>Outputs High (True) only if all inputs are false (0)

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Latch:

-Doesnt require clock signal.

-level Sensitive device

-Asynchonous device.

-Less power requied.

Flipflops:

-Requires clock signal.

-Edge sensitive device

-Synchonous device

-More power requires.

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Combinational Circuits:

-Output depends on present input.

memory element is absent

No clock signal is applied

ex:Adders

Sequential Circuits:

-Output depends on present and past input.

Memory elements is present

Clock Signal is required

ex:flipflops, counters

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What is mux or Multiplexer?

A multiplexer or mux is a combinational circuits that selects several analog or digital input signals and
forwards the selected input into a single output line.

A multiplexer of 2n inputs has n selected lines, are used to select which input line to send to the output.
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Floorplan Inputs-->

Netlist:A netlist is nothing but textual description of a circuit made of components in VLSI design.
Components are: gates, resistors, capacitors or transistors.

Lef:lef file is also called Library Exchange Format file, has basically two parts technology lef and cell lef
file.

Technology lef contains information about the metal layers.

Cell lef file contains an abstract view of the layout of standard cells

Def:The Design Exchange (DEF) file is an ASCII representation of physical information of the design. DEF
contains Property definition, Die area, Row definition, Physical cell definition, STD cell definition, special
net, regular nets, port, blockages, module constraints etc

Lib: contains code that is linked to users' programs at compile time.

Techfile:The technology file provides information on various aspects, including layer definitions, design
rules, spacing requirements, wire widths, and other parameters that guide the layout of the integrated
circuit.

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Static Timing Analysis inputs-->

Synopsys Design Constraints: An SDC (Synopsys Design Constraints) file is a text file that contains timing
constraints for a digital design.

Netlist: The netlist provides the structural representation of the circuit, including the logical gates and
their interconnections.

SPEF (Standard Parasitic Extraction Format): SPEF file contains information related to parasitic
components of a design like Resistance and Capacitance values.

Multi Mode Multi corner (MMMC) file : Multi Mode Multi corner (MMMC) file during the physical design
gives the analysis of the design over varied modes & corners

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