Department of Electronics and Communication Engineering

EC3561- VLSI Laboratory Manual

Regulation 2021

THIRD YEAR & SEMESTER V

EC3561 VLSI LABORATORY

LIST OF EXPERIMENTS:

1. Design of basic combinational and sequential (Flip-flops) circuits using HDL.

Simulate it using Xilinx/Altera Software and implement by Xilinx/Altera FPGA.
2. Design an Adder ; Multiplier (Min 8 Bit) using HDL. Simulate it using
Xilinx/Altera Software and implement by Xilinx/Altera FPGA
3. Design and implement Universal Shift Register using HDL. Simulate it using
Xilinx/Altera Software
4. Design Memories using HDL. Simulate it using Xilinx/Altera Software and
implement by Xilinx/Altera FPGA
5. Design Finite State Machine (Moore/Mealy) using HDL. Simulate it using
Xilinx/Altera Software and implement by Xilinx/Altera FPGA
6. Design 3-bit synchronous up/down counter using HDL. Simulate it using
Xilinx/Altera Software and implement by Xilinx/Altera FPGA
7. Design 4-bit Asynchronous up/down counter using HDL. Simulate it using
Xilinx/Altera Software and implement by Xilinx/Altera FPGA
8. Design and simulate a CMOS Basic Gates & Flip-Flops. Generate
Manual/Automatic Layout .
9. Design and simulate a 4-bit synchronous counter using a Flip-Flops. Generate
Manual/Automatic Layout.
10. Design and Simulate a CMOS Inverting Amplifier.
11. Design and Simulate basic Common Source, Common Gate and Common
Drain Amplifiers.
12. Design and simulate simple 5 transistor differential amplifier.
Expt 1: Design of basic combinational and sequential circuits using HDL.
Simulate it using Xilinx/Altera Software.

Half adder

Verilog Program

module half_adder_d (
input a,b,
output sum,carry
);
assign sum = a ^ b;
assign carry = a & b;
endmodule

Output Waveform
Full adder
 Verilog Program

module fulladder ( input [3:0] a,

input [3:0] b,

input c_in,

output c_out,

output [3:0] sum);

assign {c_out, sum} = a + b + c_in;

endmodule

Output Waveform
SR Flipflop

Schematic diagram
Truth Table

Verilog Program

module SR_flipflop (
input clk, rst_n,
input s,r,
output reg q,
output q_bar
);

// always@(posedge clk or negedge rst_n) // for asynchronous reset

always@(posedge clk) begin // for synchronous reset
if(!rst_n) q <= 0;
else begin
 case({s,r})
2'b00: q <= q; // No change
2'b01: q <= 1'b0; // reset
2'b10: q <= 1'b1; // set
2'b11: q <= 1'bx; // Invalid inputs
endcase
end
end
assign q_bar = ~q;
endmodule

Output Waveform

Result:
Thus the basic combinational and sequential circuits were successfully designed
usini using verilog HDL and implemented with simulation.
Expt 2:

Design an Adder (Min 8 Bit) using HDL. Simulate it using Xilinx/Altera Software .

Aim:
To design and simulate 8 bit adder using Xilinx ISE simulator.
Apparatus Required:
Personal computer, Xilinx ISE design suite software.

Schematic diagram- 8 bit adder

Procedure:
1. Open the Xilinx ISE design suite, a Xilinx navigator window will be displayed.
2. Select File and open new project .
3. Give the project name in the new project wizard window and select the top level
source type as HDL.
4.Click next and confirm the prefered language in the project settings and press next
and finish.
5. Now open project , new source and select verilog module and give file name.
6. Next , finish and enter the program in the window ,save the program.
7. Enable implementation on the top left of the page and click synthesis xst .
8. Then select simulation on the top left of the window and select the file with module
name and click Isim simulator, check error with behavioral check syntax and then
double click on the simulate behavioral model.
9.Now you can view the simulation window . Give proper value for the inputs as per
the program and press run.
10. Finally verify the output from the simulated waveform.

Program ( 8bit Adder)

module adder(s,cout,a,b,cin);
output[7:0]s;
output cout;
input[7:0]a,b;
input cin;
wire c1,c2,c3,c4,c5,c6,c7;
fulladd fa0(s[0],c1,a[0],b[0],cin);
fulladd fa1(s[1],c2,a[1],b[1],c1);
fulladd fa2(s[2],c3,a[2],b[2],c2);
fulladd fa3(s[3],c4,a[3],b[3],c3);
fulladd fa4(s[4],c5,a[4],b[4],c4);
fulladd fa5(s[5],c6,a[5],b[5],c5);
fulladd fa6(s[6],c7,a[6],b[6],c6);
fulladd fa7(s[7],cout,a[7],b[7],c7);

endmodule

module fulladd(s,cout,a,b,cin);
output s,cout;
input a,b,cin;
xor (s,a,b,cin);
assign cout = ((a & b )|(b& cin)|( a & cin)) ;
endmodule
8bit Adder- Output

Result:

Thus the 8 bit adder was successfully designed using verilog HDL and
implemented with simulation.
Experiment:3

Design a Multiplier using HDL. Simulate it using Xilinx/Altera Software .

Aim:
To design and simulate 4 bit multiplier using Xilinx ISE simulator.

Apparatus Required:
Personal computer, Xilinx ISE design suite software

Procedure:
1. Open the Xilinx ISE design suite, a Xilinx navigator window will be displayed.
2. Select File and open new project .
3. Give the project name in the new project wizard window and select the top level
source type as HDL.
4.Click next and confirm the preffered language in the project settings and press
next and finish.
5. Now open project , new source and select verilog module and give file name.
6. Next , finish and enter the program in the window ,save the program.
7. Enable implementation on the top left of the page and click synthesis xst .
8. Then select simulation on the top left of the window and select the file with
module name and click Isim simulator, check error with behavioral check syntax
and then double click on the simulate behavioral model.
9.Now you can view the simulation window . Give proper value for the inputs as
per the program and press run button.
10. Finally verify the output from the simulated waveform.
Program

module fourbitmulti(m,a,b);
input[3:0]a;
input[3:0]b;
output[7:0]m;
wire[15:0]p;
wire[12:1]s;
wire[12:1]c;
and(p[0],a[0],b[0]);
and(p[1],a[1],b[0]);
and(p[2],a[0],b[1]);
and(p[3],a[2],b[0]);
and(p[4],a[1],b[1]);
and(p[5],a[0],b[2]);
and(p[6],a[3],b[0]);
and(p[7],a[2],b[1]);
and(p[8],a[1],b[2]);
and(p[9],a[0],b[3]);
and(p[10],a[3],b[1]);
and(p[11],a[2],b[2]);
and(p[12],a[1],b[3]);
and(p[13],a[3],b[2]);
and(p[14],a[2],b[3]);
and(p[15],a[3],b[3]);
half ha1(s[1],c[1],p[1],p[2]);
half ha2(s[2],c[2],p[4],p[3]);
half ha3(s[3],c[3],p[7],p[6]);
full fa4(s[4],c[4],p[11],p[10],c[3]);
full fa5(s[5],c[5],p[14],p[13],c[4]);
full fa6(s[6],c[6],p[5],s[2],c[1]);
full fa7(s[7],c[7],p[8],s[3],c[2]);
full fa8(s[8],c[8],p[12],s[4],c[7]);
full fa9(s[9],c[9],p[9],s[7],c[6]);
half ha10(s[10],c[10],s[8],c[9]);
full fa11(s[11],c[11],s[5],c[8],c[10]);
full fa12(s[12],c[12],p[15],s[5],c[11]);
buf (m[0],p[0]);
buf (m[1],s[1]);
buf (m[2],s[6]);
buf (m[3],s[9]);

buf (m[4],s[10]);
buf (m[5],s[11]);
buf (m[6],s[12]);
buf (m[7],c[12]);
endmodule

module half (s,c0,x,y);

input x,y;
output s,c0;
 xor(s,x,y);
and(c0,x,y);
endmodule

module full(s,c0,x,y,cin);
input x,y,cin;
output s,c0;
wire s1,d1,d2;
half ha_1(s1,d1,x,y);
half ha_2(s,d2,s1,cin);
or or_gate(c0,d2,d1);
endmodule

Output- 4 bit Multiplier

Result:
Thus the 4 bit multiplier was successfully designed using verilog HDL and
implemented with simulation.
Experiment: 4
Design a Universal shift register using HDL. Simulate it using Xilinx/Altera
Software .

Aim:
To design and simulate Universal shift register using Xilinx ISE simulator.
Apparatus Required:
Personal computer, Xilinx ISE design suite software

Procedure:
1. Open the Xilinx ISE design suite, a Xilinx navigator window will be displayed.
2. Select File and open new project .
3. Give the project name in the new project wizard window and select the top level
source type as HDL.
4.Click next and confirm the preffered language in the project settings and press
next and finish.
5. Now open project , new source and select verilog module and give file name.
6. Next , finish and enter the program in the window ,save the program.
7. Enable implementation on the top left of the page and click synthesis xst .
8. Then select simulation on the top left of the window and select the file with
module name and click Isim simulator, check error with behavioral check syntax
and then double click on the simulate behavioral model.
9.Now you can view the simulation window . Give proper value for the inputs as
per the program and press run button.
10. Finally verify the output from the simulated waveform.

Diagram- Universal shift register

Program:

module usr (clr,clk,left_in,right_in,sel,par_in,out);

input clr, clk, left_in, right_in;

input [1:0] sel;

input [3:0] par_in;

output reg[3:0] out;

always@ (posedge clk)

begin

if (clr)
 out=4'b0000;

else

begin

case(sel)

2'b00: out=out;

2'b01: out={right_in, out[3:1]};

2'b10: out={out[2:0],left_in};

2'b11: out=par_in;

endcase

end

end

endmodule

Output- Universal shift register

Result:
Thus the Universal shift register was successfully designed using verilog HDL
and implemented with simulation.
Experiment: 5

Design a Finite state machine(Mealy) using HDL. Simulate it using

Xilinx/Altera Software.

Aim:
To design and simulate FSM with Mealy sequence detector using Xilinx ISE
simulator.
Apparatus Required:
Personal computer, Xilinx ISE design suite software

Procedure:
1. Open the Xilinx ISE design suite, a Xilinx navigator window will be displayed.
2. Select File and open new project .
3. Give the project name in the new project wizard window and select the top level
source type as HDL.
4.Click next and confirm the preffered language in the project settings and press
next and finish.
5. Now open project , new source and select verilog module and give file name.
6. Next , finish and enter the program in the window ,save the program.
7. Enable implementation on the top left of the page and click synthesis xst .
8. Then select simulation on the top left of the window and select the file with
module name and click Isim simulator, check error with behavioral check syntax
and then double click on the simulate behavioral model.
9.Now you can view the simulation window . Give proper value for the inputs as
per the program and press run button.
10. Finally verify the output from the simulated waveform.

The state diagram of a Mealy machine for a 101 sequence detector

Sequence detector using Mealy machine

module mealy fsm(

input in,

input clk,

input rst,

output reg out);

reg [1:0] cst;

reg [1:0] nst;

parameter [1:0] s0=2'b00;

parameter [1:0] s1=2'b01;

parameter [1:0] s2=2'b10;

always@ (posedge clk)

begin

if (rst) begin

out=1'b0;

cst=s0;

nst=s0; end
else

begin

cst=nst;

case(cst)

so: if(in) begin

out=1'b0;

nst=s1; end

else begin

out=1'b0;

nst=s0; end

s1: if(in) begin

out=1'b0;

nst=s1;end

else begin

out=1'b0;

nst=s0; end

s2: if(in) begin

out=1'b1;

nst=s1;end

else begin

out=1'b0;

nst=s0; end

endcase

end

end
 endmodule

Testbench (FSM Mealy)

#10;

rst=1;

#10;

rst=0;

#10;

in=1;

#10;

in=0;

#10;

in=1;

#10;

end

always #5 clk= ~clk;

endmodule

Output- Mealy sequence detector

 Result:
Thus the FSM with mealy sequence detector was successfully designed using
verilog HDL and implemented with simulation.
Experiment: 6
Design Memories using HDL and Simulate it using Xilinx/Altera Software .

Aim:
To design Memories and simulate using Xilinx ISE simulator.
Apparatus Required:
Personal computer, Xilinx ISE design suite software

Procedure:
1. Open the Xilinx ISE design suite, a Xilinx navigator window will be displayed.
2. Select File and open new project .
3. Give the project name in the new project wizard window and select the top level
source type as HDL.
4.Click next and confirm the preffered language in the project settings and press
next and finish.
5. Now open project , new source and select verilog module and give file name.
6. Next , finish and enter the program in the window ,save the program.
7. Enable implementation on the top left of the page and click synthesis xst .
8. Then select simulation on the top left of the window and select the file with
module name and click Isim simulator, check error with behavioral check syntax
and then double click on the simulate behavioral model.
9.Now you can view the simulation window . Give proper value for the inputs as
per the program and press run button.
10. Finally verify the output from the simulated waveform.

Verilog code for dual port RAM

module dualportRAM(clk,cs,wr,rd,addr,data_in,data_out);

input clk,cs,wr,rd;

input [3:0] data_in;

input [7:0] addr;

output reg [3:0]data_out;

reg[3:0] mem [255:0];

always@(posedge clk)
begin

if (~ cs)

data_out <= 4’b0000;

else

begin

if(wr)

mem [addr]<=data_in;

if(rd)

data_out<= mem[addr];

end

end

endmodule

Testbench (RAM)

# 100;

cs=1;

wr=1;

rd=0;

data_in=4’b0001;

addr= 8’d01;

#10;

data_in=4’b0010;

addr=8’d02;

#10;

rd=1;
 wr=0;

addr= 8’d01;

#10;

addr=8’d02;

end

always clk= #5 ~ clk;

endmodule

Output - Design of Memories

Result:
Thus the Design of memories was successfully done using verilog HDL and
implemented with simulation.
Expt 7:

Design 3-bit synchronous up/down counter using HDL. Simulate it using

Xilinx/Altera Software.

Aim:
To design a 3-bit synchronous counter and simulate using Xilinx ISE
simulator.
Apparatus Required:
Personal computer, Xilinx ISE design suite software

Procedure:

1. Open the Xilinx ISE design suite, a Xilinx navigator window will be displayed.
2. Select File and open new project .
3. Give the project name in the new project wizard window and select the top level
source type as HDL.
4.Click next and confirm the preffered language in the project settings and press
next and finish.
5. Now open project , new source and select verilog module and give file name.
6. Next , finish and enter the program in the window ,save the program.
7. Enable implementation on the top left of the page and click synthesis xst .
8. Then select simulation on the top left of the window and select the file with
module name and click Isim simulator, check error with behavioral check syntax
and then double click on the simulate behavioral model.
9.Now you can view the simulation window . Give proper value for the inputs as
per the program and press run button.
10. Finally verify the output from the simulated waveform.

Diagram
Verilog code 3bit Synchronous Counter

module updown (clk ,dir_up,clear,count );

input clk,dir_up,clear ;

output reg [2:0] count;

always @ (posedge clk or posedge clear)

begin

if (clear)

begin

count<= 3'b000;

end

else

begin

if (dir_up)

begin

count<= count+1;

end

else

begin
count<= count-1;

end

end

end

endmodule

Testbench -3 bit sync

initial begin

clear=1; clk=0; dir_up=0;

#100 clear=0; dir_up=1;

#200 dir_up=0;

#100

$ finish;

end

always #10 clk=~ clk;

endmodule
 Output- 3 bit Sync. counter

Result:
Thus the 3-bit synchronous up/down counter was successfully done using
verilog HDL and implemented with simulation.
Experiment: 8
Design and simulate a 4-bit synchronous counter using Flip-Flops .

Aim:
To design a 4-bit synchronous counter and simulate using Xilinx ISE
simulator.
Apparatus Required:
Personal computer, Xilinx ISE design suite software

Procedure:

1. Open the Xilinx ISE design suite, a Xilinx navigator window will be displayed.
2. Select File and open new project .
3. Give the project name in the new project wizard window and select the top level
source type as HDL.
4.Click next and confirm the preffered language in the project settings and press
next and finish.
5. Now open project , new source and select verilog module and give file name.
6. Next , finish and enter the program in the window ,save the program.
7. Enable implementation on the top left of the page and click synthesis xst .
8. Then select simulation on the top left of the window and select the file with
module name and click Isim simulator, check error with behavioral check syntax
and then double click on the simulate behavioral model.
9.Now you can view the simulation window . Give proper value for the inputs as
per the program and press run button.
10. Finally verify the output from the simulated waveform.

Diagram

Program
 module Counter_4Bit ( clk ,reset ,dout );
output [3:0] dout ;
reg [3:0] dout ;
input clk ;
wire clk ;
input reset ;
wire reset ;
initial dout = 0;
always @ (posedge (clk)) begin
if (reset)
dout <= 0;
else
dout <= dout + 1;
end
endmodule

Output

Result:
Thus 4bit synchronous counter was successfully designed using verilog HDL
and implemented with simulation.
Expt 9:

Design 4-bit Asynchronous up/down counter using HDL. Simulate it using

Xilinx/Altera Software.
Aim:
To design a 4-bit asynchronous counter and simulate using Xilinx ISE
simulator.
Apparatus Required:
Personal computer, Xilinx ISE design suite software

Procedure:
1. Open the Xilinx ISE design suite, a Xilinx navigator window will be displayed.
2. Select File and open new project .
3. Give the project name in the new project wizard window and select the top level
source type as HDL.
4.Click next and confirm the preffered language in the project settings and press
next and finish.
5. Now open project , new source and select verilog module and give file name.
6. Next , finish and enter the program in the window ,save the program.
7. Enable implementation on the top left of the page and click synthesis xst .
8. Then select simulation on the top left of the window and select the file with
module name and click Isim simulator, check error with behavioral check syntax
and then double click on the simulate behavioral model.
9.Now you can view the simulation window . Give proper value for the inputs as
per the program and press run button.
10. Finally verify the output from the simulated waveform.

4bit asynchronous counter

module asynchronous_count (q,clk,t,reset);

output [3:0]q;

input clk,t,reset;

T_FF1 tff0 (q[0],clk,t,reset);

T_FF1 tff1 (q[1] q[0],t,reset);

T_FF1 tff2 (q[2], q[1], t,reset);

T_FF1 tff3 (q[3], q[2], t,reset);

endmodule

module T_FF1 (q,clk,t,reset);

output q;

input clk,t,reset;

D_FF dff0 (q,d,clk,reset);

xor n2 (d,q,t);

endmodule

module D_FF (q,d,clk,reset);

output q;

reg q;

input d,clk,reset;

always@(posedge reset or negedge clk)

if (reset)

q=1’b0;

else

q=d;

endmodule

Testbench ( 4 bit async Counter)

initial begin

t=1;

reset=1;

#15 reset =0;

#340 reset =1;

#10 reset =0;

end

initial clk=0;

always #10 clk =~clk;

endmodule

Output- 4 bit Asynchronous counter

Result:

Thus the 4-bit asynchronous up/down counter was successfully done using

verilog HDL and implemented with simulation.

Experiment: 10

Design and simulate a CMOS inverter circuit

Aim:
To design and simulate a CMOS inverter using Dsch2 and Microwind tools and
perform the simulation.
Apparatus Required:
Dsch2 and microwind, Personal Computer

Theory:
NOT gate: The CMOS NOT design is detailed in the following figure. Here one
p-channel MOS and one n-channel MOS transistors are used as switches. The
channel width for pMOS devices is set to twice the channel width for nMOS
devices. When the input signal is logic 0, the nMOS is switched off while the
PMOS passes VDD through the output, which turns to 1. When the input signal
is logic 1.the pMOS is switched off while the nMOS passes VSS to the output,
which goes back to 0. In that simulation, the MOS is considered as a simple
switch. The n channel MOS symbol is a device that allows the current to flow
between the source and the drain when the gate voltage is "1".

Procedure:

1.Open the Dsch3 file.

2.Select the nNMOS transistor from Symbol Library on top right and dragging it
to the main screen. Select the nNMOS transistor from Symbol Library on top right
and dragging it to the main screen.
3.Similarly selecting supply and ground symbols from Symbol Library and
dragging them to the main screen.
4.Connecting all symbols as shown in the figure.
5.Use add a line command to connect different nodes of these symbols .
6.Adding a Button Symbol to the input and Light symbol to the output of the
circuit from Symbols library and completes the schematic diagram. Then save as
the file using a particular name.
7.Then go to simulate tab and click start simulation. After few seconds stop the
simulation and click on timing diagram to view the outputs.
Go to file and click on make verilog file and save it
8.Open the microwind file. Choose Compile verilog file option and select the
respective file from dsch2 folder.
9.Compile it and back to editor to view the automatic generated layout.
10.Finally simulate the file and get the final output.
CMOS Inverter Output

RESULT:

Thus the CMOS inverter was designed and simulated successfully using microwind
and dsch2 tools.

_____________________________________________________
Experiment: 11

Design and simulate CMOS Basic gates and Flipflops

AIM:
To design and simulate a CMOS basic logic gates (NAND and NOR) and flipflops
(D,T, JK flipflops) using Dsch2 and microwind tools and perform the prelayout
and post layout simulations.
Apparatus Required:
Dsch2 and microwind
Theory:
NAND gate: A NAND gate can be implemented using four MOS transistors i.e.
two pmos and two nmos as the inputs of the gate is two. pmos are connected in
parallel while nmos are connected in series, Vdd is supplied to the parallel
combination of pmos while the series combination of nmos is grounded. Inputs a
& b are applied to the gate terminals of all FETs, and the output f is obtained from
the common junction of these series and parallel combinations as illustrated in
NAND circuit.
NOR gate: The two-input NOR gate shown on the left is built from four
transistors. The parallel connection of the two n-channel transistors between GND
and the gate-output ensures that the gateoutput is driven low (logical 0) when
either gate input A or B is high (logical 1). The complementary series-connection
of the two transistors between VCC and gate-output means that the gate-output is
driven high (logical 1) when both gate inputs are low (logical 0).

Procedure:
1. Open the Dsch3 file.
2.Select the nNMOS transistor from Symbol Library on top right and dragging it
to the main screen.
3.Select the nNMOS transistor from Symbol Library on top right and dragging it
to the main screen.
4.Similarly selecting supply and ground symbols from Symbol Library and
dragging them to the main screen.
5. Connect all symbols as shown in the figure.Use add a line command to connect
different nodes of these symbols .
6.Add a Button Symbol to the input and Light symbol to the output of the circuit
from Symbols library and completes the schematic diagram. Then save as the file
using a particular name.
7.Then go to simulate tab and click start simulation. After few seconds stop the
simulation and click on timing diagram to view the outputs.
8.Go to file and click on make verilog file and save it
 9.Open the microwind file. Choose Compile verilog file option and select the
respective file from dsch2 folder.

10.Compile it and back to editor to view the automatic genrated layout.Simulate

and verify the output.

Diagram- CMOS NAND gate

Diagram- CMOS NOR gate
 Output - D FLIP FLOP

LOP

RESULT:
Thus the CMOS basic gates and flipflops were designed and simulated successfully.

________________________________________________________________
Experiment: 12

Design a CMOS inverting amplifier

Aim:
To design and simulate CMOS inverting amplifier circuit and measure the
parameters using Tanner EDA tools.
Apparatus Required:
PC with windows, Tanner EDA tools .
Procedure:
1. Click on the S-Edit . In the window select the file.
2. Create new design by Click file . Then New and open New Design
3. Enter the design name and select the path to save the design.
4. Create new cell view , Cell , select new view and Select the parameters and
give ok.
5. Click add available in library window and select the library file.
6. Select devices in the library drag required PMOS and NMOS components from
the symbol browser and design the amplifier circuit.
7. Common mode Inputs are applied to the circuit.
8. To open T spice window click Tools and T- Spice.
9. Insert technology file and required comments using insert comment option in
T- Spice.
10. Run the simulation by click on simulation icon.
11. Output waveform is viewed in the waveform viewer (W-edit) now verify the
result.

Theory

CMOS inverter act as an inverting linear amplifier with a characteristics of Vout =-

AVin where A is the stage gain. Near the input threshold voltage the, the CMOS inverter
acts as an inverting linear amplifier. It should be noted that the CMOS inverter when
used as a logic element is in reality an analog amplifier operated under saturating
condition. It can also be viewed as an nMOS common source amplifier driving a pMOS
common source amplifier.. For amplifiers operating at very low supply voltages, the
inverting amplifier stages should be applied. This circuits display an output voltage
range that is nearly equal to the supply voltage and can operate on
Output- CMOS Inverting amplifier

RESULT:

Thus the CMOS inverting amplifier was designed and simulated successfully.

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