||Jai Sri Gurudev ||

Sri AdichunchanagiriShikshana Trust®

SJB INSTITUTE OF TECHNOLOGY

Accredited by NBA & NAAC with ‘A’ Grade
No. 67, BGS Health & Education City, Dr. Vishnuvardhan Road
Kengeri, Bangalore – 560 060

Department of Electronics & Communication

Engineering
DIGITAL SYSTEM DESIGN USING VERILOG[BEC302]

MODULE - 2
Notes (as per VTU Syllabus)

III SEMESTER – B. E

Academic Year: 2023 – 2024 (ODD)

Course Coordinator : Dr. Shilpa K Gowda

Designation: Associate Professor

Digital Communication 18EC61

SYLLABUS

DIGITAL SYSTEM DESIGN USING VERILOG

[As per Choice Based Credit System (CBCS) scheme]

Sub Code: BEC302 CIEMarks:50

Teaching Hrs./ Week: 3:0:2 Exam Hours: 03
Total Hrs.: 40 Hrs. Theory + 8-10 lab slots SEE Marks :50
Credits – 04

Course Learning Objectives: This course will enable students to:

 To impart the concepts of simplifying Boolean expression using K-map techniques

and Quine- McCluskey minimization techniques.
 To impart the concepts of designing and analysing combinational logic circuits.
 To impart design methods and analysis of sequential logic circuits.
 To impart the concepts of Verilog HDL-data flow and behavioural models for the
design of digital systems

Module – 1
Principles of Combinational Logic: Definition of combinational logic, Canonical forms,
Generation of switching equations from truth tables, Karnaugh maps- up to 4 variables,
Quine-McCluskey Minimization
Technique. Quine-McCluskey using Don’t Care Terms. (Section 3.1 to 3.5 of Text 1).
8 Hrs.

Module – 2
Logic Design with MSI Components and Programmable Logic Devices: Binary Adders and
Subtractors, Comparators, Decoders, Encoders, Multiplexers, Programmable Logic Devices
(PLDs)(Section 5.1 to 5.7 of Text 2) 8 Hrs

Module – 3
Flip-Flops and its Applications: The Master-Slave Flip-flops (Pulse-Triggered flip-flops):
SR flip-flops, JK flip flops, Characteristic equations, Registers, Binary Ripple Counters,
Synchronous Binary Counters, Counters based on Shift Registers, Design of Synchronous
mod-n Counter using clocked T, JK, D and SRflip-flops. (Section 6.4, 6.6 to 6.9 (Excluding
6.9.3) of Text 2)8 Hrs.

Module – 4
Introduction to Verilog: Structure of Verilog module, Operators, Data Types, Styles of
Description. (Section 1.1 to 1.6.2, 1.6.4 (only Verilog), 2 of Text 3)
Verilog Data flow description: Highlights of Data flow description, Structure of Data flow
description. (Section 2.1 to 2.2 (only Verilog) of Text 3)8Hrs

Module – 5
Verilog Behavioral description: Structure, Variable Assignment Statement, Sequential
Statements, Loop Statements, Verilog Behavioral Description of Multiplexers (2:1, 4:1,
8:1). (Section 3.1 to 3.4 (only Verilog) of Text 3)
Verilog Structural description: Highlights of Structural description, Organization of structural
description, Structural description of ripple carry adder. (Section 4.1 to 4.2 of Text 3)
Dept. of ECE/SJBIT Page 2
Digital Communication 18EC61

8Hrs

COURSE OUTCOMES:

Course Outcomes: At the end of the course, the students will be able to

 Explain the concept of combinational and sequential logic circuits and PLD.
 Design the combinational logic circuits.
 Design the sequential circuits using SR, JK, D, and T flip-flops.
 Understand the various Verilog HDL descriptions and verify the functionality in the
digital circuit systems.
 Synthesize Verilog programs for Combinational, sequential circuits and interface the
peripherals on FPGA.

TEXTBOOK:

1. Digital Logic Applications and Design by John M Yarbrough, Thomson Learning,

2001.
2. Digital Principles and Design by Donald D Givone, McGraw Hill, 2002.
3. HDL Programming VHDL and Verilog by Nazeih M Botros, 2009 reprint, Dreamtech
press.

REFERENCE BOOKS:

1. Fundamentals of logic design, by Charles H Roth Jr., Cengage Learning

2. Logic Design, by Sudhakar Samuel, Pearson/ Sanguine, 2007

3. Fundamentals of HDL, by Cyril P R, Pearson/Sanguine 2010

MODULE–2
Dept. of ECE/SJBIT Page 3
Digital Communication 18EC61

LOGICDESIGNWITHMSI COMPONENTS AND

PROGRAMMABLELOGICDEVICES

DESIGNOFCOMBINATIONALCIRCUITS

Thedesignofcombinationalcircuitsstartsfromtheverbaloutlineoftheproblemandendsinalogi
ccircuit diagram. Theprocedureinvolves thefollowingsteps:
1. State the given problem completely and exactly
2. Interpret the problem and determine the available input variables and required output
variables.
3. Assign a letter symbol to each input and output variables.
4. Design the truth table, which defines the required relations between inputs and outputs.
5. Obtain the simplified Boolean expression for each output using k-maps.
6. Draw the logic circuit diagram to implement the Boolean expression.

ARITHMETICCIRCUITS

One essential function of most computers and calculators is the performance of

arithmeticoperations.Thelogicgatesdesignedsofarcanbeusedtoperformarithmeticoperation
ssuchasaddition,subtraction,multiplicationanddivisioninelectroniccalculatorsanddigitalins
truments.Since these circuits are electronic, they are very fast. Typically, an
additionoperationtakes less than1 µs.

HALF– ADDER

ALogiccircuitusedfortheadditionoftwoone-bitnumbersisreferredtoasahalf-adder.Fromthe
verbal explanation of a half adder, we find that this circuit needs two binary inputs and
twobinary outputs. The input variables designate the augend and addend bits; the output
variablesproduce the sum and carry. We assign the symbols A and B to the two inputs
and S (for sum)andC (for carry) to theoutputs. Thetruth tablefor thehalf-adder is
shownbelow.

Dept. of ECE/SJBIT Page 4

Digital Communication 18EC61

Here the C output is 1 only when both inputs are 1. The S output represents the least
significantbit of the sum. The logic expression for the sum output can be obtained from
the truth table.
ItcanbewrittenasaSOPexpressionbysumminguptheinputcombinationsforwhichthesumiseq
ualto 1.

Inthetruthtable,thesumoutputis1for A′BandAB′.Therefore,theexpressionforthesumis

S=A′B+ AB′=A⊕B.

Similarly, the logic expression for carry output can be written as a SOP expression by
summingup the input combinations for which the carry is equal to 1.In the truth table, the
carry is 1
forAB.ThereforeC=ABThisexpressionforCcannotbesimplified.Thesumoutputcorresponds
to a logic Ex-OR function while the carry output corresponds to an AND function.So the
half-addercircuit can beimplemented using Ex-ORand AND gateas shown below.

Fig1:HalfAdderLogiccircuit

ThiscircuitiscalledHalf-Adder,becauseitcannotacceptaCARRY-
INfrompreviousadditions.Thisisthereasonthathalf–

Dept. of ECE/SJBIT Page 5

Digital Communication 18EC61

addercircuitcanbeusedforbinaryadditionoflowermostbitsonly.Forhigher ordercolumns
weusea3-input adder called full-adder

FULL–ADDER

A combinational logic circuit for adding three bits. As seen, a half-adder has only two
inputsandthereisnoprovisiontoaddcarrycomingfromthelowerbitorderwhenmultibitaddition
isperformed.Forthispurposeweusealogiccircuitthatcanaddthreebits,thethirdbitisthecarry
from the lower column. This implies that we need a logic circuit with 3 inputs and 2
outputs.Suchacircuit iscalledafull– adder.Thetruth table forthefull-adder isas shown
below.

As shown there are 8 possible input combinations for the three inputs and for each case
the Sand Cout values are listed. From the truth table, the logic expression for S can be
written bysummingup theinput combinations forwhich thesum outputis 1 as:

S=A′B′Cin+A′BC′in+AB′C′in+ABCin
=A′(B′Cin+BC′in) +A(B′C′in+BCin)
=A′(B⊕Cin)+A(B⊕Cin)′ Let
B⊕Cin = XNow,S=A′X+AX′=A ⊕X ReplacingXin theabove
expression we get

S= A⊕B⊕Cin

Dept. of ECE/SJBIT Page 6

Digital Communication 18EC61

Similarly the logic expression for Cout can be

written asCout= A′BCin+ AB′Cin +ABC′in
+ABCin

Cout=BCin+ ACin+ AB (using the map shown)

FromthesimplifiedexpressionsofSandCthefulladderCircuitcanbeimplementedusingtwo2-
input XOR gates, Three 2 –input AND gates and one 3-input OR gate a shown below fig
(a).Thelogicsymbol is also shown as fig (b).

Fig2:FullAdderLogic Circuit

The logic symbol has two inputs A and B plus a third input Cin called the Carry-in and
twooutputsSUMandtheCarrycalledCarryout,Coutgoingtothenexthighercolumn..Afulladde
rcanbemadeby using two halfadders and anOR gate asshown below.

Fig3:Fulladdercircuitusingtwohalfadders
Dept. of ECE/SJBIT Page 7
Digital Communication 18EC61

HALF–SUBTRACTOR

A logic circuit that subtracts Y (subtrahend) from X(minuend), where X and Y are 1-
bitnumbers, is known as a half-subtractor. It has two inputs X (minuend) and Y
(subtrahend) andtwooutputs D (difference) andB (borrow),as shownin theblock diagram.

The operation of this logic circuit is based on the rules of binary subtraction given in the
truthtablereproduced on the basis of thesubtraction process.

The difference output in the third column has the same logic pattern as when X is XORed
withY (same as in the case of sum). Hence an Ex-Or gate can be used to give difference
of two bits.The borrow output in the 4th column can be obtained by using a NOT gate
and AND gate, asshownin thecircuit diagram below.
Thelogicalequationsforthedifference D andborrowB are givenas

D = X′Y + XY′ = X ⊕ Y.

B= X′Y

Dept. of ECE/SJBIT Page 8

Digital Communication 18EC61

Fig4:HalfSubtractorLogiccircuit

FULL–SUBTRACTOR

Thefull-
subtractorisacombinationalcircuitwhichisusedtoperformsubtractionofthreesinglebits

The truth table for the full-subtractor is as shown below.

INPUT OUTPUT
X Y Z D B

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

Dept. of ECE/SJBIT Page 9

Digital Communication 18EC61

1 1 0 0 0

1 1 1 1 1

As shown there are 8 possible input combinations for the three inputs and for each case
the Dand B values are listed. From the truth table, the logic expression for D can be
written bysummingup theinput combinations forwhichtheDifference output is 1 as:
D=X’Y'Z +X’YZ’+XY’Z'+XYZ
=X’(Y’Z+YZ’) +X(Y’Z'+YZ)
X’(Y ⊕Z) + X(Y ⊕Z)’
D=X⊕Y⊕Z
B=X’Y'Z+X’YZ’+X’YZ+XYZ
=Z (X’Y+XY’)+ X’Y(Z’+Z)

B=Z(X⊕Y)+X’Y

Thecircuitdiagram forfullsubtractoris constructedfromhalfsubtractor andthe extensiontoit

,as shownbelow.

Fig 5: Full Subtractor Logic circuit

4- BITPARALLELADDER

Dept. of ECE/SJBIT Page 10

Digital Communication 18EC61

The 4-bit binary adder performs the addition of two 4-bit numbers. Let the 4-bit
binarynumbers, A=A3 A2 A1 A0 and B=B3 B2 B1 B0. We can implement 4-bit binary
adder in oneof thetwo following ways.

 Use one Half adder for doing the addition of two Least significant bits and three
Full adders for doing the addition of three higher significant bits.

 Use four Full adders for uniformity. Since, initial carry C0 is zero, the Full adder
which is used for adding the least significant bits becomes Half adder.

For the time being, we considered second approach. The block diagram of 4-bit binary
adder is shown in the following figure.

Fig 6: 4-Bit Binary Adder Circuit

Here, the 4 Full adders are cascaded. Each Full adder is getting the respective bits of two
parallel inputs A & B. The carry output of one Full adder will be the carry input of
subsequent higher order Full adder. This 4-bit binary adder produces the resultant sum
having at most 5 bits. So, carry out of last stage Full adder will be the MSB.

Dept. of ECE/SJBIT Page 11

Digital Communication 18EC61

In this way, we can implement any higher order binary adder just by cascading the
requirednumberofFulladders.Thisbinaryadderisalsocalledas ripplecarry(binary)adder
becausethecarry propagates (ripples)from one stagetothenextstage.

BINARYSUBTRACTOR

Thecircuit,whichperformsthesubtractionoftwobinarynumbersisknownas
Binarysubtractor.Wecan implement Binarysubtractor in following twomethods.

 CascadeFullsubtractors

 2’scomplementmethod

Infirstmethod,wewillgetann-
bitbinarysubtractorbycascading‘n’Fullsubtractors.So,firstyoucanimplementHalfsubtracto
randFullsubtractor,similartoHalfadder&Fulladder.Then,you can implement an n-bit
binary subtractor, by cascading ‘n’ Full subtractors. So, we will behavingtwoseparate
circuitsforbinaryaddition andsubtraction oftwo binarynumbers.

In second method, we can use same binary adder for subtracting two binary numbers
just bydoing some modifications in the second input. So, internally binary addition
operation takesplacebut, theoutput is resultant subtraction.

We know that the subtraction of two binary numbers A & B can be

written as,A−B=A+(2′s complementofB)

A−B=A+(2′scomplement ofB)

⇒A−B=A+(1′s complement ofB)+1

4-bitBinarySubtractor

The4-bitbinarysubtractorproducesthe subtractionoftwo4-
bitnumbers.Letthe4bitbinarynumbers, A = A3 A2 A1 A0 and B = B3 B2 B1 B0 .
Internally, the operation of 4-bit Binarysubtractor is similar to that of 4-bit Binary adder.
If the normal bits of binary number A, complemented bits of binary number B and initial

Dept. of ECE/SJBIT Page 12

Digital Communication 18EC61

carry (borrow), Cin as one are applied to 4-bit Binary adder, then it becomes 4-bit Binary
subtractor. The block diagram of 4-bit binarysubtractoris shown in the following
figure.

Fig7:4-Bit BinarySubtractorCircuit

This4-bitbinarysubtractorproducesanoutput,whichishavingatmost5bits.IfBinarynumberA
is greater than Binary number B, then MSB of the output is zero and the remaining bits
holdthe magnitude of A-B. If Binary number A is less than Binary number B, then MSB
of theoutputis one. So, takethe 2’scomplement ofoutputin order to get themagnitudeof
A-B.

Inthisway,wecanimplementanyhigherorderbinarysubtractorjustbycascadingtherequiredn
umberof Full adders with necessary modifications.

4-bit Binary Adder / Subtractor

The 4-bit binary adder / subtractor produces either the addition or the subtraction of two
4-bit numbers based on the value of initial carry or borrow, C0. Let the 4-bit binary
numbers, A = A3 A2 A1 A0 and B = B3 B2 B1 B0. The operation of 4-bit Binary
adder / subtractor is similar tothatof4-bit Binary adderand 4-bit Binarysubtractor.

Apply the normal bits of binary numbers A and B & initial carry or borrow, C0 from
externally to a 4-bit binary adder. The block diagram of 4-bit binary adder / subtractor is
shown in the following figure.

Dept. of ECE/SJBIT Page 13

Digital Communication 18EC61

Fig8:4-BitBinaryAdder/Subtractor Circuit

If initial carry, C0 is zero, then each full adder gets the normal bits of binary numbers A
& B.So,the4-bitbinaryadder/subtractorproducesanoutput,whichisthe
additionoftwobinarynumbersA & B.

If initial borrow, 𝐶0 is one, then each full adder gets the normal bits of binary number A
&complemented bits of binary number B. So, the 4-bit binary adder / subtractor
produces anoutput,which is thesubtraction oftwo binary numbersA &B.

Therefore, with the help of additional Ex-OR gates, the same circuit can be used for
bothadditionand subtractionof two binary numbers.

Fig9:4-BitCarryLookAheadAdderBlockDiagram

Dept. of ECE/SJBIT Page 14

Digital Communication 18EC61

Pi = Ai ⊕ Bi Carry

propagateGi = AiBBi

Carry generateFori=0

c1=g0+p0c

0Fori=1

c2=g1+p1c1

=g1+p1(g0+p0c0)

=g1+p1g0+p1p0c0

Fori=2

c3=g2+p2c2

=g2+p2g1+p2p1g0+p2p1p0c0F

ori=3

c4=g3+p3c3=g3+p3g2+p3p2g1+p3p2p1g0+p3p2p1p0c0

Dept. of ECE/SJBIT Page 15

Digital Communication 18EC61

Fig 10: 4-Bit Carry Look Ahead Adder Logic circuit

Dept. of ECE/SJBIT Page 16

Digital Communication 18EC61

ComplexProgrammableLogicDevices(CPLD’s)

As number of Boolean expression increases, designing a digital circuit using PLD’s becomes
difficult.

To overcome this problem, we can use complex programmable logic devices.

Using CPLDs we can implement more than 20 Boolean expression in a digital circuit.

Fig11: Block Diagramof CPLD

FeaturesofCPLD

• High Performance

• Fast connection of Switch matrix

• Programmable switching mode

Applicationsof CPLD

• It is used in a digital circuit where Number of input and output are > 32.

• Television and Automation Industries.

• Implementation of large digital circuits.

Dept. of ECE/SJBIT Page 17

Digital Communication 18EC61

FieldProgrammableGateArrays(FPGA)

• A Field-Programmable Gate Array is an integrated circuit silicon chip which has

array of logic gates and this array can be programmed in the field i.e. the user can
overwrite the existing configurations with its new defined configurations and can
create their own digital circuit on field. The FPGAs can be considered as blank
slate. FPGAs do nothing by itself whereas it is up to designers to create a
configuration file often called a bit file for the FPGA. The FPGA will behave like
the digital circuit once it is loaded with a bit file.

• Field Programmable Gate Arrays (FPGAs) are semiconductor devices that are
based around a matrix of configurable logic blocks (CLBs) connected via
programmable interconnects.

• FPGAs are particularly useful for prototyping application-specific integrated

circuits (ASICs) or processors.

• An FPGA can be reprogrammed until the processor design is final and bug-free.

FPGAArchitecture

• An FPGA has a regular structure of logic cells or modules and interlinks which is
under the developers and designers complete control. The FPGA is built with
mainly three major blocks such as Configurable Logic Block (CLB), I/O Blocks
or Pads and Switch Matrix/ Interconnection Wires. Each block will be discussed
below in brief.

CLB (Configurable Logic Block): These are the basic cells of FPGA. It consists
of one8-bitfunctiongenerator,two16-bitfunctiongenerators,tworegisters(flip-
flopsor latches), and reprogrammable routing controls (multiplexers). The CLBs
are applied toimplement other designed function and macros. Each CLBs have
inputs on each sidewhichmakes them flexileforthe mappingand partitioning of
logic.

• I/O Pads or Blocks: The Input/Output pads are used for the outside peripherals to
access the functions of FPGA and using the I/O pads it can also communicate
with FPGA for different applications using different peripherals.

Dept. of ECE/SJBIT Page 18

Digital Communication 18EC61

• Switch Matrix/ Interconnection Wires: Switch Matrix is used in FPGA to connect

the long and short interconnection wires together in flexible combination. It also
contains the transistors to turn on/off connections between different lines.

Fig12: Block Diagramof FPGA

Configurablelogicblocks:

EachConfigurablelogic block cangenerateaLogicfunction withmanyinputs.

InterconnectionSwitches:

Theyareusedto interconnectvariousblock withinput/outputblocks.

Application:

FPGAmostcommonlyused inDigitalsystemssuch assmartphones,Computer systemsetc.

Dept. of ECE/SJBIT Page 19

Digital Communication 18EC61

CPLD vs FPGA comparison summary

CPLD FPGA
1. Instant-on.CPLDsstartworkingassoonas Since FPGA has to load configuration
they arepoweredup datafromexternalROMandsetupthefabricbefor
e it can start functioning, there is a timedelay
between power ON and FPGA startsworking.
The time delay can be as large asseveraltens
of milliseconds.

2. Non- FPGAsusesSRAMbasedconfigurationstorage.
volatile.CPLDsremainprogrammed,and The contents of the memory is lost assoonas
retaintheir power is disconnected.
circuitafterpoweringdown.FPGAsgobla
nkassoon as powered-off.
3. Deterministic Timing Analysis. Size and complexity of FPGA logic can
SinceCPLDs are comparatively simpler behumongous compared to CPLDs. This
toFPGAs,andthenumberofinterconnects opensupthepossibilitylessdeterministicsignalr
areless,thetiminganalysiscanbedonemu outing and thus causing complicated
chmoreeasily. timingscenarios.Thankfullyimplementationto
olsprovided by FPGA vendors have
mechanismsto assist achieving deterministic
timing.
Butadditionalstepsbytheuserisusuallynecessar
yto achievethis.
4. Loweridlepowerconsumption.Newer Relativelyhigheridlepowerconsumption.
CPLDs such as CoolRunner-
IIusearound50 uA inidleconditions.

5. Mightbecheaperforimplementingsimple FPGAsaremuchmorecapablecomparedtoCPLD
rcircuits sbutcan bemore expensiveaswell.

6. More"secure"duetodesignstoragewithin FPGAs that use external memory can

built innon-volatile memory. exposethe IP externally. Many FPGA
vendors
offermechanismssuchasencryptiontocombatth

Dept. of ECE/SJBIT Page 20

Digital Communication 18EC61

is. Design specific protection

mechanismsalsocan beimplemented.
7. Verysmallamountoflogicresources. Massive amount logic and storage
elements,withwhichincrediblycomplexcircuit
scanbedesigned. FPGAs have thousands
times moreresources!
ThispointalonemakesFPGAsmorepopularthan
CPLDs.
8. Noon- Variety of on-die dedicated hardware such
diehardIPsavailabletooffloadprocessing asBlockRAM,DSPblocks,PLL,DCMs,Memor
fromthelogic fabric. yControllers,Multi-
GigabitTransceiversetcgiveimmenseflexibilit
y.Thisis not eventhinkable with CPLDs.

9. Powerdownandreprogrammingisalways FPGAs can change their circuit even

requiredinordertomodifydesignfunction whilerunning! (Since it is just a matter of
ality. updatingLUTs with different content) This is
calledPartialReconfiguration,andisveryuseful
when FPGAs need to keep running a
designandatthesametimeupdatetheitwithdiffer
entdesignasperrequirement.Thisfeatureiswide
lyusedinAcceleratedComputing.

Dept. of ECE/SJBIT Page 21