DESIGN OF 8 BIT RIPPLE CARRY ADDER

WITH D FLIP FLOP

8-Bit Ripple Carry Adder is designed by using 1 half adder, 7 full adders
which sum and carry output is stored in D flip flop.

LINTING

Superlint , cdc configurations, x-

propagation, formal verification.
Simulation done by Xcelium Simulator:
RTL CODING:
8-bit Ripple Carry Adder :
module Adder_8bit(input [7:0] A, input [7:0] B, input CLK,rstn,output [8:0]Q);

wire C0,C1,C2,C3,C4,C5,C6;

wire [7:0] S;wire C7;

half_adder HA0 (.a(A[0]), .b(B[0]),.su(S[0]),.c(C0));

full_adder_d FA1 ( .a(A[1]),.b(B[1]),.cin(C0),.sum(S[1]),.carry(C1));

full_adder_d FA2 ( .a(A[2]), .b(B[2]),.cin(C1),.sum(S[2]),.carry(C2));

full_adder_d FA3 ( .a(A[3]), .b(B[3]), .cin(C2),.sum(S[3]),.carry(C3));

full_adder_d FA4 ( .a(A[4]), .b(B[4]),.cin(C3),.sum(S[4]),.carry(C4));

full_adder_d FA5 ( .a(A[5]), .b(B[5]),.cin( C4),.sum(S[5]),.carry(C5));

full_adder_d FA6 ( .a(A[6]), .b(B[6]), .cin(C5),.sum(S[6]),.carry(C6));

full_adder_d FA7 ( .a(A[7]), .b(B[7]), .cin(C6),.sum(S[7]),.carry(C7));

dff d2(.d(S[0]),.CLK(CLK),.rstn(rstn),.q(Q[0]));

dff d3(.d(S[1]),.CLK(CLK),.rstn(rstn),.q(Q[1]));

dff d4(.d(S[2]),.CLK(CLK),.rstn(rstn),.q(Q[2]));

dff d5(.d(S[3]),.CLK(CLK),.rstn(rstn),.q(Q[3]));

dff d6(.d(S[4]),.CLK(CLK),.rstn(rstn),.q(Q[4]));

dff d7(.d(S[5]),.CLK(CLK),.rstn(rstn),.q(Q[5]));

dff d8(.d(S[6]),.CLK(CLK),.rstn(rstn),.q(Q[6]));

dff d9(.d(S[7]),.CLK(CLK),.rstn(rstn),.q(Q[7]));

dff d10(.d(C7),.CLK(CLK),.rstn(rstn),.q(Q[8]));

endmodule
D Flip Flop :
module dff(input d,CLK,rstn,output reg q);

always@(posedge CLK or negedge rstn)

begin

if(!rstn)

q<=0;

else

q<=d;

end

endmodule

Full Adder :
module full_adder_d (

input a,b,cin,

output sum,carry);

assign sum = a ^ b ^ cin;

assign carry = (a & b) | (b & cin) | (cin & a) ;

endmodule

Half Adder:
module half_adder (input a,b,

output su,c);

assign su = a ^ b;

assign c = a & b;

endmodule
Linting process is done by jaspergold tool. Superlint, CDC
configurations , formal verification, x-propagation process are done
by jaspergold tool which waivers are added in add waivers option and
export as a waiver file.
LOGIC SYNTHESIS:
IO Pad Instantiation:

module Adder_8Bit(
A_pad,
B_pad,
CLK_pad,
rstn_pad,
Q_pad

);

output [8:0] Q_pad;

input [7:0] A_pad;
input [7:0] B_pad;
input CLK_pad;
input rstn_pad;
wire [7:0]A;
wire [7:0]B;
wire [8:0]Q;
wire [7:0]S;
wire CLK,rstn;
wire C7;
wire C0,C1,C2,C3,C4,C5,C6;
pc3c01 pc3c01_1(.CCLK (CLK_pad), .CP (CLK));
pc3d01 pc3d01_1(.PAD(CLK_pad),.CIN(CLK));
pc3d01 pc3d01_2(.PAD(rstn_pad),.CIN(rstn));
pc3d01 pc3d01_3(.PAD(A_pad[7]),.CIN(A[7]));
pc3d01 pc3d01_4(.PAD(A_pad[6]),.CIN(A[6]));
pc3d01 pc3d01_5(.PAD(A_pad[5]),.CIN(A[5]));
pc3d01 pc3d01_6(.PAD(A_pad[4]),.CIN(A[4]));
pc3d01 pc3d01_7(.PAD(A_pad[3]),.CIN(A[3]));
pc3d01 pc3d01_8(.PAD(A_pad[2]),.CIN(A[2]));
pc3d01 pc3d01_9(.PAD(A_pad[1]),.CIN(A[1]));
pc3d01 pc3d01_10(.PAD(A_pad[0]),.CIN(A[0]));
pc3d01 pc3d01_11(.PAD(B_pad[7]),.CIN(B[7]));
pc3d01 pc3d01_12(.PAD(B_pad[6]),.CIN(B[6]));
pc3d01 pc3d01_13(.PAD(B_pad[5]),.CIN(B[5]));
pc3d01 pc3d01_14(.PAD(B_pad[4]),.CIN(B[4]));
pc3d01 pc3d01_15(.PAD(B_pad[3]),.CIN(B[3]));
pc3d01 pc3d01_16(.PAD(B_pad[2]),.CIN(B[2]));
pc3d01 pc3d01_17(.PAD(B_pad[1]),.CIN(B[1]));
pc3d01 pc3d01_18(.PAD(B_pad[0]),.CIN(B[0]));

pc3o05 pc3o05_1(.I(Q[8]),.PAD(Q_pad[8]));
pc3o05 pc3o05_2(.I(Q[7]),.PAD(Q_pad[7]));
pc3o05 pc3o05_3(.I(Q[6]),.PAD(Q_pad[6]));
pc3o05 pc3o05_4(.I(Q[5]),.PAD(Q_pad[5]));
pc3o05 pc3o05_5(.I(Q[4]),.PAD(Q_pad[4]));
pc3o05 pc3o05_6(.I(Q[3]),.PAD(Q_pad[3]));
pc3o05 pc3o05_7(.I(Q[2]),.PAD(Q_pad[2]));
pc3o05 pc3o05_8(.I(Q[1]),.PAD(Q_pad[1]));
pc3o05 pc3o05_9(.I(Q[0]),.PAD(Q_pad[0]));
 half_adder HA0 (.a(A[0]), .b(B[0]),.su(S[0]),.c(C0));
full_adder_d FA1 (.a(A[1]),.b(B[1]),.cin(C0),.sum(S[1]),.carry(C1));
full_adder_d FA2 (.a(A[2]),.b(B[2]),.cin(C1),.sum(S[2]),.carry(C2));
full_adder_d FA3 (.a(A[3]),.b(B[3]),.cin(C2),.sum(S[3]),.carry(C3));
full_adder_d FA4 (.a(A[4]),.b(B[4]),.cin(C3),.sum(S[4]),.carry(C4));
full_adder_d FA5 (.a(A[5]),.b(B[5]),.cin(C4),.sum(S[5]),.carry(C5));
full_adder_d FA6 (.a(A[6]),.b(B[6]),.cin(C5),.sum(S[6]),.carry(C6));
full_adder_d FA7 (.a(A[7]),.b(B[7]),.cin(C6),.sum(S[7]),.carry(C7));

dff d2(.d(S[0]),.CLK(CLK),.rstn(rstn),.q(Q[0]));
dff d3(.d(S[1]),.CLK(CLK),.rstn(rstn),.q(Q[1]));
dff d4(.d(S[2]),.CLK(CLK),.rstn(rstn),.q(Q[2]));
dff d5(.d(S[3]),.CLK(CLK),.rstn(rstn),.q(Q[3]));
dff d6(.d(S[4]),.CLK(CLK),.rstn(rstn),.q(Q[4]));
dff d7(.d(S[5]),.CLK(CLK),.rstn(rstn),.q(Q[5]));
dff d8(.d(S[6]),.CLK(CLK),.rstn(rstn),.q(Q[6]));
dff d9(.d(S[7]),.CLK(CLK),.rstn(rstn),.q(Q[7]));
dff d10(.d(C7),.CLK(CLK),.rstn(rstn),.q(Q[8]));
endmodule
Constraint File Creation:

######### SDC CONSTRAINTS #############

########## PARAMETERS ############
set_units-time 1.0ns;
set_units-capacitance 1.0pF;
#### Clock constraints ########
set CLOCK_PERIOD 10;
set CLOCK_NAME CLK;

set SKEW_setup [expr $CLOCK_PERIOD*0.025];

set SKEW_hold [expr $CLOCK_PERIOD*0.025];
set MINRISE [expr $CLOCK_PERIOD*0.125];
set MAXRISE [expr $CLOCK_PERIOD*0.2];
set MINFALL [expr $CLOCK_PERIOD*0.125];
set MAXFALL [expr $CLOCK_PERIOD*0.2];

####### CLOCK CONSTRAINTS #########

create_clock -name "$CLOCK_NAME" \
-period "$CLOCK_PERIOD" \
-waveform '0 [expr $CLOCK_PERIOD/2]" \
[get_ports "CLK_pad"]

##Virtual Clock Constraints

create_clock -name vir_clk -period 10

##Clock source latency

set_clock_latency -source -max 1.25 -late [get_clocks CLK]
set_clock_latency -source -min 0.75 -late [get_clocks CLK]
set_clock_latency -source -max 1.0 -early [get_clocks CLK]
set_clock_latency -source -min 1.25 -early [get_clocks CLK]

#Clock transition
set_clock_transition -rise -min $MINRISE [get_clocks CLK]
set_clock_transition -rise -max $MAXRISE [get_clocks CLK]
set_clock_transition -fall -min $MINRISE [get_clocks CLK]
set_clock_transition -fall -max $MAXRISE [get_clocks CLK]

#Input transition
set_input_transition -max $MAX_PORT [get_ports A_pad[7]]
set_input_transition -max $MAX_PORT [get_ports A_pad[6]]
set_input_transition -max $MAX_PORT [get_ports A_pad[5]]
set_input_transition -max $MAX_PORT [get_ports A_pad[4]]
set_input_transition -max $MAX_PORT [get_ports A_pad[3]]
set_input_transition -max $MAX_PORT [get_ports A_pad[2]]
set_input_transition -max $MAX_PORT [get_ports A_pad[1]]
set_input_transition -max $MAX_PORT [get_ports A_pad[0]]
set_input_transition -max $MAX_PORT [get_ports B_pad[7]]
set_input_transition -max $MAX_PORT [get_ports B_pad[6]]
set_input_transition -max $MAX_PORT [get_ports B_pad[5]]
set_input_transition -max $MAX_PORT [get_ports B_pad[4]]
set_input_transition -max $MAX_PORT [get_ports B_pad[3]]
set_input_transition -max $MAX_PORT [get_ports B_pad[2]]
set_input_transition -max $MAX_PORT [get_ports B_pad[1]]
set_input_transition -max $MAX_PORT [get_ports B_pad[0]]

# clock uncertainty
set_clock_uncertainty -setup $SKEW_setup [get_clocks CLK]
set_clock_uncertainty -hold $SKEW_hold [get_clocks CLK]

set_input_delay -add_delay -clock vir_clk -max 7.75 [get_ports A_pad[7]]

set_input_delay -add_delay -clock vir_clk -max 7.75 [get_ports A_pad[6]]
set_input_delay -add_delay -clock vir_clk -max 7.75 [get_ports A_pad[5]]
set_input_delay -add_delay -clock vir_clk -max 7.75 [get_ports A_pad[4]]
set_input_delay -add_delay -clock vir_clk -max 7.75 [get_ports A_pad[3]]
set_input_delay -add_delay -clock vir_clk -max 7.75 [get_ports A_pad[2]]
set_input_delay -add_delay -clock vir_clk -max 7.75 [get_ports A_pad[1]]
set_input_delay -add_delay -clock vir_clk -max 7.75 [get_ports A_pad[0]]
set_input_delay -add_delay -clock vir_clk -max 7.75 [get_ports B_pad[7]]
set_input_delay -add_delay -clock vir_clk -max 7.75 [get_ports B_pad[6]]
set_input_delay -add_delay -clock vir_clk -max 7.75 [get_ports B_pad[5]]
set_input_delay -add_delay -clock vir_clk -max 7.75 [get_ports B_pad[4]]
set_input_delay -add_delay -clock vir_clk -max 7.75 [get_ports B_pad[3]]
set_input_delay -add_delay -clock vir_clk -max 7.75 [get_ports B_pad[2]]
set_input_delay -add_delay -clock vir_clk -max 7.75 [get_ports B_pad[1]]
set_input_delay -add_delay -clock vir_clk -max 7.75 [get_ports B_pad[0]]

#Output port delay

set_output_delay -clock vir_clk -min 2.628 [get_ports Q_pad[8]] -add_delay
set_output_delay -clock vir_clk -min 2.628 [get_ports Q_pad[7]] -add_delay
set_output_delay -clock vir_clk -min 2.628 [get_ports Q_pad[6]] -add_delay
set_output_delay -clock vir_clk -min 2.628 [get_ports Q_pad[5]] -add_delay
set_output_delay -clock vir_clk -min 2.628 [get_ports Q_pad[4]] -add_delay
set_output_delay -clock vir_clk -min 2.628 [get_ports Q_pad[3]] -add_delay
set_output_delay -clock vir_clk -min 2.628 [get_ports Q_pad[2]] -add_delay
set_output_delay -clock vir_clk -min 2.628 [get_ports Q_pad[1]] -add_delay
set_output_delay -clock vir_clk -min 2.628 [get_ports Q_pad[0]] -add_delay

# Input transition
set_input_transition -max $MAX_PORT [get_ports rstn_pad]
set_input_transition -min $MIN_PORT [get_ports rstn_pad]

######### LOAD SPECIFICATIONS ###########

set_load 5 [get_ports S_pad]

############## FALSE PATHS ######################

set_false_path -from [get_clocks CLK] -to [get_clocks CLK]
set_false_path -from [get_clocks CLK] -to [get_clocks vir_clk]
set_false_path -from [get_ports rstn_pad] -to [all_registers]

########## GROUP PATHS #########

group_path -name I2R -from [all_inputs] -to [all_registers]

group_path -name R2O -from [all_registers] -to [all_outputs]
group_path -name R2R -from [all_registers] -to [all_registers]
group_path -name I2O -from [all_inputs] -to [all_outputs]
Preparation of script file:

### Template Script for RTL->Gate-Level Flow

## Preset global variables and attributes
################################################################
###############
set DESIGN Adder_8Bit
set GEN_EFF medium
set MAP_OPT_EFF high
set clockname CLK
set DATE [clock format [clock seconds] -format "%b%d-%T"]
set _OUTPUTS_PATH output_files
set _REPORTS_PATH report_files
set _LOG_PATH logs_${DATE}
##set ET_WORKDIR <ET work directory>
set_db / .init_lib_search_path {
/home/install/scl_pdk_v2/stdlib/fs120/liberty/lib_flow_ss
./home/install/scl_pdk_v2/stdlib/fs120/liberty/lib_flow_ff}
set_db / .script_search_path {. ./Scripts}
set_db / .init_hdl_search_path {. ./RTL_source}
set_db auto_ungroup none
##Uncomment and specify machine names to enable super-threading.
##set_db / .super_thread_servers {<machine names>}
##For design size of 1.5M - 5M gates, use 8 to 16 CPUs. For designs > 5M
gates, use 16 to 32 CPUs
##set_db / .max_cpus_per_server 8
##Default undriven/unconnected setting is 'none'.
##set_db / .hdl_unconnected_value 0 | 1 | x | none

set_db / .information_level 7

###############################################################
## Library setup
###############################################################

set_db / .library {
/home/install/scl_pdk_v2/stdlib/fs120/liberty/lib_flow_ss/tsl18fs120_scl_ss.lib
/home/install/scl_pdk_v2/iolib/cio150/synopsys/2002.05/models/tsl18cio150_m
ax.lib
/home/install/scl_pdk_v2/stdlib/fs120/liberty/lib_flow_ff/tsl18fs120_scl_ff.lib
/home/install/scl_pdk_v2/iolib/cio150/synopsys/2002.05/models/tsl18cio150_m
in.lib}
#set_db / .lef_library {../lef/tsl18fs120_scl.lef}
read_libs -max_libs {
/home/install/scl_pdk_v2/stdlib/fs120/liberty/lib_flow_ss/tsl18fs120_scl_ss.lib
/home/install/scl_pdk_v2/iolib/cio150/synopsys/2002.05/models/tsl18cio150_m
ax.lib} \
-min_libs {
/home/install/scl_pdk_v2/stdlib/fs120/liberty/lib_flow_ff/tsl18fs120_scl_ff.lib
/home/install/scl_pdk_v2/iolib/cio150/synopsys/2002.05/models/tsl18cio150_m
in.lib}
#lib_cell_list gcnfnn1 gcnfnn2 gcnfnn4 gcnfnn7 gcnfnna gcnrnn1 gcnrnn2
gcnrnn4 gcnrnn7 gcnrnna mx08*
#set_dont_use lib_cell_lists [ gcnfnn1 gcnfnn2 gcnfnn4 gcnfnn7 gcnfnna
gcnrnn1 gcnrnn2 gcnrnn4 gcnrnn7 gcnrnna mx08*]
################################################################
####
## Load Design
################################################################
####

puts "load RTL"

set FILE_LIST {adder8bit.v dff.v fa.v ha.v}
read_hdl $FILE_LIST

puts "elobrate design"

elaborate $DESIGN
puts "Runtime & Memory after 'read_hdl'"
time_info Elaboration
check_design -unresolved

################################################################
####
## Constraints Setup
################################################################
####
read_sdc ./constraints/adder_constraints.sdc
path_adjust -from [all_inputs] -to [all_outputs] -delay -1300 -name PA_I2O
path_adjust -from [all_inputs] -to [all_register] -delay -1500 -name PA_I2C
path_adjust -from [all_register] -to [all_outputs] -delay -1500 -name PA_C2O
path_adjust -from [all_register] -to [all_register] -delay -1500 -name PA_C2C
report_timing -unconstrained
set_db timing_report_unconstrained true
#break
puts "The number of exceptions is [llength [vfind "design:$DESIGN" -
exception *]]"
if {![file exists ${_OUTPUTS_PATH}]} {
file mkdir ${_OUTPUTS_PATH}
puts "Creating directory ${_OUTPUTS_PATH}"
}

if {![file exists ${_REPORTS_PATH}]} {

file mkdir ${_REPORTS_PATH}
puts "Creating directory ${_REPORTS_PATH}"
}

set_db lp_power_analysis_effort high

################################################################
####################################
## Synthesizing to generic
################################################################
####################################

set_db / .syn_generic_effort $GEN_EFF

syn_generic
puts "Runtime & Memory after 'syn_generic'"
time_info GENERIC
report_dp > $_REPORTS_PATH/generic/${DESIGN}_datapath.rpt
write_snapshot -outdir $_REPORTS_PATH -tag generic
report_summary -directory $_REPORTS_PATH
write_hdl > ${_OUTPUTS_PATH}/${DESIGN}_generic.v
write_sdc > ${_OUTPUTS_PATH}/${DESIGN}_generic.sdc
#break

################################################################
####################################
## Synthesizing to gates
################################################################
####################################

set_db / .syn_map_effort $MAP_OPT_EFF

syn_map
puts "Runtime & Memory after 'syn_map'"
time_info MAPPED
write_snapshot -outdir $_REPORTS_PATH -tag map
report_summary -directory $_REPORTS_PATH
report_dp > $_REPORTS_PATH/map/${DESIGN}_datapath.rpt
write_hdl > ${_OUTPUTS_PATH}/${DESIGN}_map.v
write_sdc > ${_OUTPUTS_PATH}/${DESIGN}_map.sdc

write_do_lec -revised_design fv_map -logfile

${_LOG_PATH}/rtl2intermediate.lec.log >
${_OUTPUTS_PATH}/rtl2intermediate.lec.do
################################################################
#######################################
## Optimize Netlist
################################################################
#######################################

set_db / .syn_opt_effort $MAP_OPT_EFF

syn_opt
write_snapshot -outdir $_REPORTS_PATH -tag syn_opt
report_summary -directory $_REPORTS_PATH

puts "Runtime & Memory after 'syn_opt'"

time_info OPT

write_snapshot -outdir $_REPORTS_PATH -tag final

report_summary -directory $_REPORTS_PATH
write_hdl > ${_OUTPUTS_PATH}/${DESIGN}_incremental.v
## write_script > ${_OUTPUTS_PATH}/${DESIGN}_m.script
write_sdc > ${_OUTPUTS_PATH}/${DESIGN}_incremental.sdc

###### SDF file Generation ############

write_sdf -version 2.1 -recrem split -setuphold merge_when_paired -edges
check_edge > ${_OUTPUTS_PATH}/async_adder_synth.sdf

#################################
### write_do_lec
#################################

write_do_lec -golden_design fv_map -revised_design

${_OUTPUTS_PATH}/${DESIGN}_incremental.v -logfile
${_LOG_PATH}/intermediate2final.lec.log >
${_OUTPUTS_PATH}/intermediate2final.lec.do
##Uncomment if the RTL is to be compared with the final netlist..
 #write_do_lec -revised_design fv_map -logfile
${_LOG_PATH}/rtl2intermediate.lec.log >
${_OUTPUTS_PATH}/rtl2intermediate.lec.do

puts "Final Runtime & Memory."

time_info FINAL
puts "============================"

puts "Synthesis Finished ........."

puts "============================"

 open genus gui and synthesis is doing by this following command:

source ./Scripts/run.tcl
 Post synthesis Logic Eqivalence check and Gate level simulation is
done by using conformal LEC & Simulator(xcelium or NClaunch)
 Floorplanning and power placement steps are done by using
innovus tool.

Clock tree synthesis :

Config.tcl file:

##################################################################################
#################

## CCOPT CONFIGRATION ##

##################################################################################
#################

##set_ccopt_mode -integration native

## CPPR Removal for Incremental delays (optional)

#set_global timing_enable_si_cppr true

## Decide what Timing Tool you will be signing off on & set the engine to match (this is the default)

#setSIMode -analysisType aae

## Ensure SI Delay Cal is on (this is the default)

#setDelayCalMode -SIAware true

##################################################################################
#################

## To load postCTS timing constraints

##################################################################################
#################

#update_constraint_mode -name top_chip_wrapper_constraints -sdc_files [list

top_chip_wrapper_incremental.sdc]

##################################################################################
#################

## To ensure that sufficient analysis views are active

##################################################################################
#################

set_analysis_view -setup {worst} -hold {best}

##################################################################################
#################

## GigaOpt technology for the postRoute flow.

##################################################################################
#################
setAnalysisMode -analysisType onChipVariation -cppr both

setNanoRouteMode -drouteUseMultiCutViaEffort "high"

##################################################################################
#################

## Configure library cells for CTS to beused

##################################################################################
#################

set_ccopt_property buffer_cells {bufbd1 bufbd2 bufbd3 bufbd4 bufbd7 bufbda bufbdf bufbdk}

set_ccopt_property inverter_cells {invbd2 invbd4 invbd7 invbda invbdf invbdk}

#set_ccopt_property clock_gating_cells {**}

## Include this setting to use inverters in preference to buffers

#set_ccopt_property use_inverters true

setRouteMode -earlyGlobalMaxRouteLayer 4

##################################################################################
#################

## Define route types to binds a non-default routing rule, preferred routing layers, and shielding

## specification together.
##################################################################################
#################

create_route_type -name leaf_rule -top_preferred_layer 2 -bottom_preferred_layer 1 -

preferred_routing_layer_effort high

create_route_type -name trunk_rule -top_preferred_layer 3 -bottom_preferred_layer 2 -

preferred_routing_layer_effort high

##################################################################################
#################

## Specify that the route types defined above will be used for leaf, trunk, and top nets.

##################################################################################
#################

set_ccopt_property -net_type leaf route_type leaf_rule

set_ccopt_property -net_type trunk route_type trunk_rule

set_ccopt_property -net_type top route_type trunk_rule

##################################################################################
#################

## Specify top routing rules will be used for any clock tree net with a transitive sink fanout count

##################################################################################
#################

#set_ccopt_property routing_top_min_fanout 1
##################################################################################
#################

## Specify top routing rules will be used for any clock tree net with a transitive sink fanout count

##################################################################################
#################

## Include this setting to use inverters in preference to buffers

#set_ccopt_property use_inverters true

##################################################################################
#################

##

##################################################################################
#################

set_ccopt_property primary_delay_corner max_delay

set_ccopt_property route_type_autotrim false

cts.tcl file:

##################################################################################
#################

## CLOCK TREE SYNTHESIS ##

##################################################################################
#################

set_global report_timing_format {instance arc net cell slew delay arrival required}
##################################################################################
#################

## To read cts configuration file and generate cts optimization specification file

## create_ccopt_clock_tree_spec: Creates a clock tree network with associated skew groups and
other

## clock tree synthesis (CTS) configuration settings such as ignore pins, case analysis, maxTrans,

## and so on based on a multi-mode timing configuration in the common timing engine (CTE).

## one skew group will be created for each SDC clock in each constraint mode.

## ctd_win : Opens a Clock Tree Debugger (CTD) window.

##################################################################################
#################

source ./config.tcl

create_ccopt_clock_tree_spec -file ./ClockTreeSynthesis/${init_top_cell}_ccopt.spec

source ./ClockTreeSynthesis/${init_top_cell}_ccopt.spec

ctd_win -id before_ccopt

##################################################################################
#################

## set_ccopt_property :

## This command is used to set the values of various CCOpt object properties.

## target_max_trans: Configure the maximum transition target,

##################################################################################
#################
set_ccopt_property -delay_corner max_delay -net_type top target_max_trans 2

set_ccopt_property -delay_corner min_delay -net_type top target_max_trans 2

set_ccopt_property -delay_corner max_delay -net_type trunk target_max_trans 2

set_ccopt_property -delay_corner min_delay -net_type trunk target_max_trans 2

set_ccopt_property -delay_corner max_delay -net_type leaf target_max_trans 2

set_ccopt_property -delay_corner min_delay -net_type leaf target_max_trans 2

##################################################################################
#################

## target_skew: Configure a skew target for CCOpt-CTS (Ignored in only

CCopt)

## source_driver : Specifies the library pin which is assumed to drive this clock
tree. By default this is generated from clock tree extraction.

##################################################################################
#################

set_ccopt_property -skew_group CLK/all -delay_corner min_delay target_skew 0.5

set_ccopt_property -delay_corner min_delay target_skew 0.5

set_ccopt_property source_driver pc3d01/CIN -clock_tree CLK

##################################################################################
#################

## ccopt_design :- Performs clock concurrent optimization (CCOpt) on the current loaded

design in

## Innovus. CCOpt optimizes both the clock tree and the datapath to meet global timing constraints.

## -cts : Turns off clock concurrent optimization, and performs only clock tree synthesis (CTS)
## using the CCOpt engine. It does not perform any datapath optimization or useful
skew.

## Cluster mode : Physically implements the clock tree, but stops before performing any balancing

## or optimization of the clock tree,

## Trial Mode : physically implements the clock tree and uses virtual delays to approximate how

## full CTS will balance clock trees, but does not perform any
optimization,

## Full Mode : A full CTS is performed with balance and optimized clock trees.

##################################################################################
#################

set_ccopt_property balance_mode cluster

#ccopt_design

ccopt_design -cts

ctd_win -id cluster_mode

set_ccopt_property balance_mode trial

#ccopt_design

ccopt_design -cts

ctd_win -id trial_mode

set_ccopt_property balance_mode full

#ccopt_design

ccopt_design -cts

ctd_win -id full_mode

##################################################################################
#################

## report_ccopt_clock_trees: Reports a summary of all defined clock trees. This report provides a

## summary of numbers of clock gates at different

depths in each clock tree.

## report_ccopt_skew_groups: Displays information about skew and insertion delay in skew groups.

##################################################################################
#################

report_ccopt_clock_trees -summary -file ./ClockTreeSynthesis/${init_top_cell}_clock_trees.rpt

report_ccopt_skew_groups -summary -file ./ClockTreeSynthesis/${init_top_cell}_skew_group.rpt

reportCongestion -overflow -hotSpot > ./ClockTreeSynthesis/${init_top_cell}_congestion.rpt

saveDesign ./ClockTreeSynthesis/${init_top_cell}_CTS_ccopt.enc

cts.tcl and config file is not run properly. It shows the error.
The error is shown in the above picture. Please resolve this error and give a
suggestions to proceed next levl.
Virtual clock is assigned in constraint file which is match with skew group.
But CLK is declared as clock signal in RTL coding which is not match in
skew group. Please give a suggestions to make a correct constraint for pre
cts and post cts .