CENG 3420

Computer Organization & Design

Lecture 09: Datapath
Bei Yu
CSE Department, CUHK
[email protected]

(Textbook: Chapters 4.1 – 4.4)

Spring 2022
 The Processor: Datapath & Control

• We’re ready to look at an implementation of RISC-V

• Simplified to contain only:
• Memory-reference instructions: lw, sw
• Arithmetic-logical instructions: add, addu, sub, subu, and, or, xor,
nor, slt, sltu
• Arithmetic-logical immediate instructions: addi, addiu, andi, ori,
xori, slti, sltiu
• Control flow instructions: beq, j

• Generic implementation:
Fetch
• Use the program counter (PC) PC = PC+4
• To supply the instruction address and fetch the instruction
from memory (and update the PC) Exec Decode
• Decode the instruction (and read registers)
• Execute the instruction

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Abstract Implementation View

• Two types of functional units:

• elements that operate on data values (combinational)
• elements that contain state (sequential)
PCSrc

M
Add U
Add
X
4 Shift MemWrite
Left 1

RegWrite ALUSrc

ALU Op
Read
Address
Read zero data
Instruction register 1
Memory Read M
Read data 1 U
PC Read register 2 Write X
Instruction ALU Data
address Read data
Write Memory
data 2 M
register U
Write X
data Registers
MemRead

Imm 32
Gen

• Single cycle operation

• Split memory (Harvard) model - one memory for instructions and one for data
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Fetching Instructions

1 Reading the instruction from the Instruction Memory

2 Updating the PC value to be the address of the next (sequential) instruction
3 PC is updated every clock cycle, so it does not need an explicit write control signal
4 Instruction Memory is read every clock cycle, so it doesn’t need an explicit read
control signal

Add
clock 4

Fetch Instruction
PC = PC+4 Memory
Read
PC Instruction
Address
Exec Decode

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Decoding Instructions

1 Sending the fetched instruction’s opcode and function field bits to the control unit
2 Reading two values from the Register File
3 (Register File addresses are contained in the instruction)

Control

Fetch Unit

PC = PC+4
Read Addr 1
Register Read
Read Addr 2 Data 1
Exec Decode Instruction
File
Write Addr Read
Data 2
Write Data

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Reading Registers “Just in Case”

• Both RegFile read ports are active for all instructions during the Decode cycle
• Using the rs1 and rs2 instruction field addresses
• Since haven’t decoded the instruction yet, don’t know what the instruction is
• Just in case the instruction uses values from the RegFile do “work ahead” by reading
the two source operands

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 Reading Registers “Just in Case”

• Both RegFile read ports are active for all instructions during the Decode cycle
• Using the rs1 and rs2 instruction field addresses
• Since haven’t decoded the instruction yet, don’t know what the instruction is
• Just in case the instruction uses values from the RegFile do “work ahead” by reading
the two source operands

Question
Which instructions do make use of the RegFile values?

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EX-1
All instructions (except j) use the ALU after reading the registers. Please analyze
memory-reference, arithmetic, and control flow instructions.

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Executing R Format Operations
R format operations: add, sub, sll, slt, xor, srl, sra, or, and

• Perform operation (op, funct3 or funct7) on values in rs1 and rs2

• Store the result back into the Register File (into location rd)
• Note that Register File is not written every cycle (e.g. sw), so we need an explicit
write control signal for the Register File

RegWrite ALU control

Read Addr 1
Register Read
Instruction Read Addr 2 Data 1 overflow
Fetch File zero
ALU
PC = PC+4 Write Addr
Read
Data 2
Write Data
Exec Decode

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Consider the slt Instruction

• Remember the R format instruction slt

slt t0, s0, s1 # if s0 < s1

# then t0 = 1
# else t0 = 0

• Where does the 1 (or 0) come from to store into t0 in the Register File at the end of
the execute cycle?
PC from instruction datapath

Add Sum Branch target

RegWrite
Shift
Read Left 1
Instruction register 1

Read Read
register 2 data 1
Add Zero To branch control logic
Write Read
register data 2

Write ALU Operation

data Registers
4

Imm 32
Gen

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 Executing Load and Store Operations

Load and store operations have to

• compute a memory address by adding the base register (in rs1) to the 12-bit signed
offset field in the instruction
• base register was read from the Register File during decode
• offset value in the low order 12 bits of the instruction must be sign extended to
create a 32-bit signed value
• store value, read from the Register File during decode, must be written to the Data
Memory
• load value, read from the Data Memory, must be stored in the Register File

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Executing Load and Store Operations (cont.)

PCSrc

M
Add U
Add
X
4 Shift MemWrite
Left 1

RegWrite ALUSrc

ALU Op
Read
Address
Read zero data
Instruction register 1
Memory Read M
Read data 1 U
PC Read register 2 Write X
Instruction ALU Data
address Read data
Write Memory
data 2 M
register U
Write X
data Registers
MemRead

Imm 32
Gen

11/28
 Executing Branch Operations

Branch operations have to

• compare the operands read from the Register File during decode (rs1 and rs2
values) for equality (zero ALU output)
• The 12-bit B-immediate encodes signed offsets in multiples of 2 bytes.
• The 12-bit immediate offset is sign-extended and added to the address of the branch
instruction to give the target address.

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Executing Branch Operations (cont.)

PC from instruction datapath

Add Sum Branch target

RegWrite
Shift
Read Left 1
Instruction register 1

Read Read
register 2 data 1
Add Zero To branch control logic
Write Read
register data 2

Write ALU Operation

data Registers
4

Imm 32
Gen

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Executing Jump Operations

• jal
• The J-immediate encodes a signed offset in multiples of 2 bytes.
• The offset is sign-extended and added to the address of the jump instruction to form
the jump target address.

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Creating a Single Datapath from the Parts

• Assemble the datapath elements, add control lines as needed, and design the control
path
• Fetch, decode and execute each instruction in one clock cycle – single cycle design
• no datapath resource can be used more than once per instruction, so some must
be duplicated (e.g., why we have a separate Instruction Memory and Data
Memory)
• to share datapath elements between two different instruction classes will need
multiplexors at the input of the shared elements with control lines to do the
selection
• Cycle time is determined by length of the longest path

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Multiplex Insertion

Add
MemWrite

4 RegWrite

ALU Control
Read
Address
Read zero data
Instruction register 1
Memory Read
Read data 1
PC Read register 2 Write
Instruction ALU Data
address Read data
Write Memory
data 2
register
Write
data Registers
MemRead

Imm 32
Gen

16/28
Multiplex Insertion

Add MemWrite
MemToReg
4 RegWrite ALUSrc

ALU Control
Read
Address
Read zero data
Instruction register 1
Memory Read M
Read data 1 U
PC Read register 2 Write X
Instruction ALU Data
address Read data
Write Memory
data 2 M
register U
Write X
data Registers
MemRead

Imm 32
Gen

16/28
Clock Distribution

System Clock

Clock Cycle

MemWrite

RegWrite
Add
MemToReg
4 ALUSrc

ALU Control
Read
Address
Read zero data
Instruction register 1
Memory Read M
Read data 1 U
PC Read register 2 Write X
Instruction ALU Data
address Read data
Write Memory
data 2 M
register U
Write X
data Registers
MemRead

Imm 32
Gen

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Adding the Branch Portion

PCSrc

M
Add U
Add
X
4 Shift MemWrite
Left 1
MemToReg
RegWrite ALUSrc

ALU Control
Read
Address
Read zero data
Instruction register 1
Memory Read M
Read data 1 U
PC Read register 2 Write X
Instruction ALU Data
address Read data
Write Memory
data 2 M
register U
Write X
data Registers
MemRead

Imm 32
Gen

18/28
Our Simple Control Structure

• We wait for everything to settle down

• ALU might not produce "right answer" right away
• Memory and RegFile reads are combinational (as are ALU, adders, muxes,
shifter, signextender)
• Use write signals along with the clock edge to determine when to write to the
sequential elements (to the PC, to the Register File and to the Data Memory)
• The clock cycle time is determined by the logic delay through the longest path
• (We are ignoring some details like register setup and hold times)

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 Summary: Adding the Control

• Selecting the operations to perform (ALU, Register File and Memory read/write)
• Controlling the flow of data (multiplexor inputs)
• Information comes from the 32 bits of the instruction

Observations:
• opcode field always in bits 6-0
• address of two registers to be read are always specified by the rs1 and rs2 fields
(bits 19–15 and 24–20)
• base register for lw and sw always in rs1 (bits 19–15)

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(Almost) Complete Single Cycle Datapath

PCSrc

M
Add U
Add
X
4 Shift MemWrite
Left 1
MemToReg
RegWrite ALUSrc

ALU Control
Read
Address
Read zero data
Instruction register 1
Memory Read M
Read data 1 U
PC Read register 2 Write X
Instruction ALU Data
address Read data
Write Memory
data 2 M
register U
Write X
data Registers
MemRead

Imm 32
Gen

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(Almost) Complete Single Cycle Datapath

PCSrc

M
Add U
Add
X
4 Shift MemWrite
Left 1
MemToReg
RegWrite ALUSrc

ALU Control
Read
Instruction Address
[19-15] Read zero data
Instruction register 1
Memory Instruction Read M
[24-20] Read data 1 U
PC Read register 2 Write X
Instruction ALU Data
address Instruction Read data
Write Memory
[11-7]
data 2 M
register U
Write X
data Registers
MemRead

Instruction
[31-0] Imm 32 ALU
Control
Gen ALUOp

Instruction [30, 14-12]

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 ALU Control

ALU’s operation based on instruction type and function code1

ALU control Function

input
0000 and
0001 or
0010 xor
0011 nor
0110 add
1110 subtract
1111 set on less than

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Notice that we are using different encodings than in the book
 EX: ALU Control
Controlling the ALU uses of multiple decoding levels
• main control unit generates the ALUOp bits
• ALU control unit generates ALUcontrol bits

Instr op funct ALUOp action ALUcontrol

lw xxxxxx 00 add 0110
sw xxxxxx 00 add 0110
beq xxxxxx 01 subtract 1110
add 100000 10 add 0110
subt 100010 10 subtract 1110
and 100100 10 and 0000
or 100101 10 or 0001
xor 100110 10 xor 0010
nor 100111 10 nor 0011
slt 101010 10 slt 1111
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ALU Control Truth Table

F5 F4 F3 F2 F1 F0 ALU ALU ALU ALU ALU ALU

Op1 Op0 control3 control2 control1 control0
X X X X X X 0 0 0 1 1 0
X X X X X X 0 1 1 1 1 0
X X 0 0 0 0 1 0 0 1 1 0
X X 0 0 1 0 1 0 1 1 1 0
X X 0 1 0 0 1 0 0 0 0 0
X X 0 1 0 1 1 0 0 0 0 1
X X 0 1 1 0 1 0 0 0 1 0
X X 0 1 1 1 1 0 0 0 1 1
X X 1 0 1 0 1 0 1 1 1 1

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ALU Control Truth Table

F5 F4 F3 F2 F1 F0 ALU ALU ALU ALU ALU ALU

Op1 Op0 control3 control2 control1 control0
X X X X X X 0 0 0 1 1 0
X X X X X X 0 1 1 1 1 0
X X 0 0 0 0 1 0 0 1 1 0
X X 0 0 1 0 1 0 1 1 1 0
X X 0 1 0 0 1 0 0 0 0 0
X X 0 1 0 1 1 0 0 0 0 1
X X 0 1 1 0 1 0 0 0 1 0
X X 0 1 1 1 1 0 0 0 1 1
X X 1 0 1 0 1 0 1 1 1 1
Add/subt Mux control

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 ALU Control Logic

From the truth table can design the ALU Control logic

Instr[3]
Instr[2]
Instr[1]
Instr[0]
ALUOp1
ALUOp0

ALUcontrol3

ALUcontrol2

ALUcontrol1

ALUcontrol0

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(Almost) Complete Datapath with Control Unit

0
Add
M
4 U
X
Add Sum
Shift 1
Left 1 PCSrc
Branch

Instruction [6-0]
Control
ALUOp MemtoReg

ALUSrc MemWrite
RegWrite

Instruction [19-15] Read

PC Read address
register 1
Instruction [31-0] Read
Instruction [24-20] Read data 1
Instruction Zero
register 2
Memory
0 ALU 1
Instruction [11-7] Write Read
M
ALU Address Read data M
data 2 Result
register
U U
Write X X
4 0
data Registers 1

Write data Data

Memory
Instruction
[31-0] Imm 32
Gen ALU
Control MemRead

Instruction [30, 14-12]

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(Almost) Complete Datapath with Control Unit

0
Add
M
4 U
X
Add Sum
Shift 1
Left 1 PCSrc
Branch

Instruction [6-0]
Control
ALUOp MemtoReg

ALUSrc MemWrite

1 RegWrite

Instruction [19-15] Read

PC Read address
register 1
Instruction [31-0] Read 0
Instruction [24-20] Read data 1
Instruction Zero
register 2
Memory
0 ALU 1
Instruction [11-7] Write Read
M
ALU Address Read data M
data 2 Result
register
U U
Write X X
4 0
data Registers 1

Write data Data

Memory
Instruction
[31-0] Imm 32
Gen ALU
Control
0
MemRead

Instruction [30, 14-12]

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(Almost) Complete Datapath with Control Unit

0
Add
M
4 U
X
Add Sum
Shift 1
Left 1 PCSrc
Branch

Instruction [6-0]
Control
ALUOp MemtoReg

ALUSrc MemWrite

1 RegWrite

Instruction [19-15] Read

PC Read address
register 1
Instruction [31-0] Read 0
Instruction [24-20] Read data 1
Instruction Zero
register 2
Memory
0 ALU 1
Instruction [11-7] Write Read
M
ALU Address Read data M
data 2 Result
register
U U
Write X X
4 0
data Registers 1

Write data Data

Memory
Instruction
[31-0] Imm 32
Gen ALU
Control
1
MemRead

Instruction [30, 14-12]

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(Almost) Complete Datapath with Control Unit

0
Add
M
4 U
X
Add Sum
Shift 1
Left 1 PCSrc
Branch

Instruction [6-0]
Control
ALUOp MemtoReg

ALUSrc MemWrite

0 RegWrite

Instruction [19-15] Read

PC Read address
register 1
Instruction [31-0] Read 1
Instruction [24-20] Read data 1
Instruction Zero
register 2
Memory
0 ALU 1
Instruction [11-7] Write Read
M
ALU Address Read data M
data 2 Result
register
U U
Write X X
4 0
data Registers 1

Write data Data

Memory
Instruction
[31-0] Imm 32
Gen ALU
Control
0
MemRead

Instruction [30, 14-12]

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(Almost) Complete Datapath with Control Unit

0
Add
M
4 U
X
Add Sum
Shift 1
Left 1 PCSrc
Branch

Instruction [6-0]
Control
ALUOp MemtoReg

ALUSrc MemWrite

0 RegWrite

Instruction [19-15] Read

PC Read address
register 1
Instruction [31-0] Read 0
Instruction [24-20] Read data 1
Instruction Zero
register 2
Memory
0 ALU 1
Instruction [11-7] Write Read
M
ALU Address Read data M
data 2 Result
register
U U
Write X X
4 0
data Registers 1

Write data Data

Memory
Instruction
[31-0] Imm 32
Gen ALU
Control
0
MemRead

Instruction [30, 14-12]

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Main Control Unit

Instr RegDst ALUSrc MemReg RegWr MemRd MemWr Branch ALUOp

R-type 1 0 0 1 0 0 0 10
000000
lw 0 1 1 1 1 0 0 00
100011
sw X 1 X 0 0 1 0 00
101011
beq X 0 X 0 0 0 1 01
000100

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Control Unit Logic

Instr[31]
Instr[30]
Instr[29]
Instr[28]
Instr[27]
Instr[26]

R-type lw sw beq
RegDst

ALUSrc
MemtoReg
RegWrite
MemRead
MemWrite
Branch
ALUOp1
ALUOp0

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