Bihar Engineering Un

iversity, Patna
End Semester Examinat
ion ~ 2023
a ode 10stne Semester.JV Time: @3 fours
ene ~ ed Subject: Computer Organization and Architecture Full Marks: 70
Instructions:-
@ The mark
s are indicated in the
(i i) There are NINE right-hand margin,
questions in this paper
(iii) Attempt FIVE que
stions in all.
fiv) Question No. 7 is com
pulsory.
“Ql ane cot rect option of the following (any seven only):
a A pipeline stage {2x7 = f4j
(i) Is sequential circuit
(ii) fs combination circuit
Asi) Consists of both sequentia and
l combinationa( circuit
(iv) None of these
(b) A direct mapped cache memory with n blocks is nothin but
g which of the following set
associative cache memory ori
ginations
(i) 0-way set associative (ii) l-way set associative
(ili) 2-way set associative
(iv) n-way set associative
(c) The performance of a Pipelined processor suffer
s if
(i) The pipeline stages have different del
ays
(ii) Consecutive instruction are dep
endent on each other
(iil) The pip eline stages share hardware resources
Gv) All of these . 1000 ns
(¢) A computer with cache access time of {00.ns, a main memory access time of :
and a hit ratio of 0.9 produces an average access time of
i (ii) 200 ns
tito 190 5s ; (iv) None of these
Which of the following has no practical usage? -
(i) SISD (i) SIMD
(iii) MISD. (iv) MIMD
A micro programmed control uait
(i) Is faster than a hardwired control unit
(ii)Facilitates easy implementation of new instructions
(ii fs useful when every small program is to be run
(iv) Usually refers to the control unit of the microprocessor
In memory- mapped I/O..........
(i) The I/O devices and the memory share the same address space.
ii O device have a separate address space
ey Thee mesuory and I/O device have an associated address space
(iv) A part of the memory is specifically set aside for the I/O operation
man 28x8 b i t RAMs are required to design 32 k ?Hf
How i i x 32 bit RAM

; ii) 128
(i) 512 i wocessor due to the unavailability
lability of of the
the instruction
ins is called as
The ane ha Pe (ii) Structural hazard
@) soa rena (iv) None of the above
The addressing mode, where you directly specify the operand value is
; ; / Sit} Direct
(i Immediate
(iii) Definite (iv) Relative
able E (7[
( : Explain its types with suit
(23
What are the hazards in pipeline architecture?
A
hat J ? mode techniques? 7]
(b
e? Why comput
dowhich ers use addressing
explain two modes
x 1 : addressin g with
mod example, do not use address fields.
‘9
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 * (a) A 4- Way ;set associ
SSOCIA

address space is 4(3)3.

‘ we .
at;
IIVE

J ‘
PUNE
car .
using a block size of 8 we de he memory unit with a capacity af 16 KB is buill
The word length is 32 bits. The size of the physical
Me tig . . - gp
; ;
17)
in the address generated by CPL. imber of bits for TAG, SET, and WORD fields
(b) How is the virtualaddressSS Mapped into
: of writing into
methods cache? pe physi al address? 9 What are the different
o physic 17|

© (a)
(b}
What are the different types of instruction formats?
Discuss the different Mapping techniques used in cache memories and their
relative merits and demerits.

K (a)
(b)
Design a 4-bit carry ~look ahead adder and explain its operation with an exampte.
Consider a direct mapped cache with 8 cache blocks (numbered 0-7).If the
memory block requests are in the following order 3, 5, 2, 8, 0, 63, 9, 16, 20, 17.
25, 18, 30, 24, 2, 63, 5, 82, 17, 24.What would be the status of cache blocks (
block numbers residing in cache) at the end of the sequence.

® (a)
(b)
What is DMA? Describe how DMA is used to transfer data from peripherals.
Differentiate between hardwired and micro_progyamamed control unit. Explain
each component of hardwired control unit organization.

€”) (a) What do you mean by asynchronous data transfer? Explain strobe control and
hand shaking mechanism.
(b) Show the systematic multiplication process of (20) x (-I9) using Booth’s
algorithm

ad (a) The stage delays in a four stages pipeline are 800, 500, 400 and 300 picoseconds.
The first stage (with delay 800 picoseconds) is replaced with a functionally
equivalent design involving two stages with respective delays 600 and 350
picoseconds. What would be the throughput increases (in percentage) of the
pipeline?
(x Explain IEEE standard for floating point representation with example. [7]

@) Write short notes on any two of the following :

(a) Paging
{7x2=14]

(b) Memory interleaving

(c) Privileged and non- privileged instructions
(d) Locality of reference
ee oe

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