S-82B2A/B Series

www.ablic.com
BATTERY PROTECTION IC
FOR 2-SERIAL-CELL PACK
© ABLIC Inc., 2021-2023 Rev.2.3_00

This IC is a protection IC for lithium-ion / lithium polymer rechargeable batteries, which includes high-accuracy voltage
detection circuits and delay circuits. It is suitable for protecting 2-serial-cell lithium-ion / lithium polymer rechargeable battery
packs from overcharge, overdischarge, and overcurrent.
Use of an external overcurrent detection resistor enables this IC to provide high-accuracy overcurrent protection with less
impact from temperature changes.
The S-82B2A Series has an input pin for charge-discharge control signal (CTL pin), allowing for charge-discharge control
with an external signal. The S-82B2B Series has an input pin for power-saving signal (PS pin), allowing for reduction of
current consumption by using an external signal to start the power-saving function.

 Features
• High-accuracy voltage detection circuit
Overcharge detection voltage n 3.500 V to 4.800 V (5 mV step) Accuracy ±20 mV
Overcharge release voltage n 3.100 V to 4.800 V*1 Accuracy ±50 mV
Overdischarge detection voltage n 2.000 V to 3.000 V (10 mV step) Accuracy ±50 mV
Overdischarge release voltage n 2.000 V to 3.400 V*2 Accuracy ±75 mV
Discharge overcurrent 1 detection voltage 3 mV to 100 mV (0.5 mV step) Accuracy ±3.0 mV
Discharge overcurrent 2 detection voltage 10 mV to 100 mV (1 mV step) Accuracy ±5 mV
Load short-circuiting detection voltage 20 mV to 100 mV (1 mV step) Accuracy ±10 mV
Charge overcurrent detection voltage −100 mV to −3 mV (0.5 mV step) Accuracy ±3.0 mV
• Detection delay times are generated only by an internal circuit (external capacitors are unnecessary).
• Charge-discharge control function (S-82B2A Series)
CTL pin control logic: Active "H", active "L"
CTL pin internal resistance connection: Pull-up, pull-down
CTL pin internal resistance value: 1 MΩ to 10 MΩ (1 MΩ step)
• Power-saving function (S-82B2B Series)
PS pin control logic: Active "H", active "L"
PS pin internal resistance value: 1 MΩ to 10 MΩ (1 MΩ step)
• 0 V battery charge: Enabled, inhibited
• Power-down function: S-82B2A Series: Available, unavailable
S-82B2B Series: Available
• High-withstand voltage: VM pin and CO pin: Absolute maximum rating 28 V
• Wide operation temperature range: Ta = −40°C to +85°C
• Low current consumption
During operation: 3.0 μA typ., 6.0 μA max. (Ta = +25°C)
During power-down: 50 nA max. (Ta = +25°C)
During overdischarge: 1.0 μA max. (Ta = +25°C)
During power-saving (S-82B2B Series): 50 nA max. (Ta = +25°C)
• Lead-free (Sn 100%), halogen-free
*1. Overcharge release voltage = Overcharge detection voltage − Overcharge hysteresis voltage
(Overcharge hysteresis voltage can be selected as 0 V or from a range of 0.1 V to 0.4 V in 50 mV step.)
*2. Overdischarge release voltage = Overdischarge detection voltage + Overdischarge hysteresis voltage
(Overdischarge hysteresis voltage can be selected as 0 V or from a range of 0.1 V to 0.7 V in 100 mV step.)

Remark n = 1, 2

 Applications
• Lithium-ion rechargeable battery pack
• Lithium polymer rechargeable battery pack

 Packages
• SNT-8A
• HSNT-8(1616)

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BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-82B2A/B Series Rev.2.3_00

 Block Diagram
1. S-82B2A Series

VDD
Overdischarge
detection
comparator 1
DO
Overcharge
detection
comparator 1

VC
Overdischarge
detection
comparator 2

Overcharge
detection
comparator 2

VSS Discharge
overcurrent 1 detection
comparator Control logic

Delay circuit
Discharge
overcurrent 2 detection Oscillator
comparator

Load short-circuiting
detection
comparator

Charge overcurrent
detection
VINI comparator

Charger detection
comparator

Pull-up / pull-down CO
CTL selection circuit

VM

Figure 1

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 BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
Rev.2.3_00 S-82B2A/B Series

2. S-82B2B Series

VDD
Overdischarge
detection
comparator 1
DO
Overcharge
detection
comparator 1

VC
Overdischarge
detection
comparator 2

Overcharge
detection
comparator 2

VSS Discharge
overcurrent 1 detection
comparator Control logic

Delay circuit
Discharge
overcurrent 2 detection Oscillator
comparator

Load short-circuiting
detection
comparator

Charge overcurrent
detection
VINI comparator

Charger detection
comparator

Pull-up / pull-down CO
PS selection circuit

VM

Figure 2

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BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-82B2A/B Series Rev.2.3_00

 Product Name Structure

1. Product name
S-82B2 x xx - xxxx U 7

Environmental code
U: Lead-free (Sn 100%), halogen-free

Package abbreviation and IC packing specifications*1

I8T1: SNT-8A, Tape
A8T2: HSNT-8(1616), Tape

Serial code*2
Sequentially set from AA to ZZ

Product type
A: Charge-discharge control function
B: Power-saving function

*1. Refer to the tape drawing.

*2. Refer to "3. Product name list".

2. Package
Table 1 Package Drawing Codes

Package Name Dimension Tape Reel Land

SNT-8A PH008-A-P-SD PH008-A-C-SD PH008-A-R-SD PH008-A-L-SD
HSNT-8(1616) PY008-A-P-SD PY008-A-C-SD PY008-A-R-SD PY008-A-L-SD

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 BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
Rev.2.3_00 S-82B2A/B Series

3. Product name list

3. 1 S-82B2A Series

3. 1. 1 SNT-8A

Table 2 (1 / 3)

Discharge Discharge Load Short- Charge

Overcharge Overcharge Overdischarge Overdischarge
Overcurrent 1 Overcurrent 2 circuiting Overcurrent
Detection Release Detection Release
Product Name Detection Detection Detection Detection
Voltage Voltage Voltage Voltage
Voltage Voltage Voltage Voltage
[VCU] [VCL] [VDL] [VDU]
[VDIOV1] [VDIOV2] [VSHORT] [VCIOV]
S-82B2AAA-I8T1U7 4.230 V 4.080 V 2.700 V 2.900 V 25.0 mV 50 mV 100 mV −15.0 mV

Table 2 (2 / 3)

Discharge Discharge Load Short- Charge

Overcharge Overdischarge Charge-discharge
Overcurrent 1 Overcurrent 2 circuiting Overcurrent
Detection Detection Inhibition Delay
Product Name Detection Detection Detection Detection
Delay Time Delay Time Time
Delay Time Delay Time Delay Time Delay Time
[tCU] [tDL] [tCTL]
[tDIOV1] [tDIOV2] [tSHORT] [tCIOV]
S-82B2AAA-I8T1U7 1.0 s 128 ms 512 ms 16 ms 280 μs 8 ms 48 ms

Table 2 (3 / 3)

CTL Pin Internal CTL Pin Internal CTL Pin CTL Pin
CTL Pin 0 V Battery Power-down
Product Name Resistance Resistance Value*3 Voltage "H"*4 Voltage "L"*5
Control Logic*1 Charge*6 Function*7
Connection*2 [RCTL] [VCTLH] [VCTLL]
S-82B2AAA-I8T1U7 Active "H" Pull-down 3 MΩ VDD − 0.90 V VSS + 0.70 V Inhibited Available

*1. CTL pin control logic: Active "H", active "L"

*2. CTL pin internal resistance connection: Pull-up, pull-down
*3. CTL pin internal resistance value: 1 MΩ to 10 MΩ (1 MΩ step)
*4. CTL pin voltage "H": VSS + 0.75 V, VDD − 0.90 V
*5. CTL pin voltage "L": VSS + 0.70 V, VDD − 0.95 V
*6. 0 V battery charge: Enabled, inhibited
*7. Power-down function: Available, unavailable

Remark 1. Please contact our sales representatives for products other than the above.
2. The delay times can be changed within the range listed in Table 6.
For details, please contact our sales representatives.

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BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-82B2A/B Series Rev.2.3_00

3. 1. 2 HSNT-8(1616)

Table 3 (1 / 3)

Discharge Discharge Load Short- Charge

Overcharge Overcharge Overdischarge Overdischarge
Overcurrent 1 Overcurrent 2 circuiting Overcurrent
Detection Release Detection Release
Product Name Detection Detection Detection Detection
Voltage Voltage Voltage Voltage
Voltage Voltage Voltage Voltage
[VCU] [VCL] [VDL] [VDU]
[VDIOV1] [VDIOV2] [VSHORT] [VCIOV]
S-82B2AAA-A8T2U7 4.230 V 4.080 V 2.700 V 2.900 V 25.0 mV 50 mV 100 mV −15.0 mV
S-82B2AAB-A8T2U7 4.160 V 4.060 V 2.700 V 2.900 V 25.0 mV 50 mV 100 mV −15.0 mV

Table 3 (2 / 3)

Discharge Discharge Load Short- Charge

Overcharge Overdischarge Charge-discharge
Overcurrent 1 Overcurrent 2 circuiting Overcurrent
Detection Detection Inhibition Delay
Product Name Detection Detection Detection Detection
Delay Time Delay Time Time
Delay Time Delay Time Delay Time Delay Time
[tCU] [tDL] [tCTL]
[tDIOV1] [tDIOV2] [tSHORT] [tCIOV]
S-82B2AAA-A8T2U7 1.0 s 128 ms 512 ms 16 ms 280 μs 8 ms 48 ms
S-82B2AAB-A8T2U7 1.0 s 128 ms 512 ms 16 ms 280 μs 8 ms 48 ms

Table 3 (3 / 3)

CTL Pin Internal CTL Pin Internal CTL Pin CTL Pin
CTL Pin 0 V Battery Power-down
Product Name Resistance Resistance Value*3 Voltage "H"*4 Voltage "L"*5
Control Logic*1 *2
Charge*6 Function*7
Connection [RCTL] [VCTLH] [VCTLL]
S-82B2AAA-A8T2U7 Active "H" Pull-down 3 MΩ VDD − 0.90 V VSS + 0.70 V Inhibited Available
S-82B2AAB-A8T2U7 Active "H" Pull-down 3 MΩ VDD − 0.90 V VSS + 0.70 V Inhibited Available

*1. CTL pin control logic: Active "H", active "L"

*2. CTL pin internal resistance connection: Pull-up, pull-down
*3. CTL pin internal resistance value: 1 MΩ to 10 MΩ (1 MΩ step)
*4. CTL pin voltage "H": VSS + 0.75 V, VDD − 0.90 V
*5. CTL pin voltage "L": VSS + 0.70 V, VDD − 0.95 V
*6. 0 V battery charge: Enabled, inhibited
*7. Power-down function: Available, unavailable

Remark 1. Please contact our sales representatives for products other than the above.
2. The delay times can be changed within the range listed in Table 6.
For details, please contact our sales representatives.

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 BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
Rev.2.3_00 S-82B2A/B Series

3. 2 S-82B2B Series

3. 2. 1 SNT-8A

Table 4 (1 / 3)

Discharge Discharge Load Short- Charge

Overcharge Overcharge Overdischarge Overdischarge
Overcurrent 1 Overcurrent 2 circuiting Overcurrent
Detection Release Detection Release
Product Name Detection Detection Detection Detection
Voltage Voltage Voltage Voltage
Voltage Voltage Voltage Voltage
[VCU] [VCL] [VDL] [VDU]
[VDIOV1] [VDIOV2] [VSHORT] [VCIOV]
S-82B2BAA-I8T1U7 4.475 V 4.325 V 2.100 V 2.300 V 7.0 mV 15 mV 30 mV −7.0 mV

Table 4 (2 / 3)

Discharge Discharge Load Short- Charge

Overcharge Overdischarge
Overcurrent 1 Overcurrent 2 circuiting Overcurrent Power-saving
Detection Detection
Product Name Detection Detection Detection Detection Delay Time
Delay Time Delay Time
Delay Time Delay Time Delay Time Delay Time [tPS]
[tCU] [tDL]
[tDIOV1] [tDIOV2] [tSHORT] [tCIOV]
S-82B2BAA-I8T1U7 1.0 s 64 ms 3.75 s 16 ms 280 μs 16 ms 2 ms

Table 4 (3 / 3)

PS Pin PS Pin Internal Resistance PS Pin Voltage "H"*3 PS Pin Voltage "L"*4 0 V Battery
Product Name
Control Logic*1 Value*2 [RPS] [VPSH] [VPSL] Charge*5
S-82B2BAA-I8T1U7 Active "H" 5 MΩ VDD − 0.90 V VSS + 0.70 V Inhibited

*1. PS pin control logic: Active "H", active "L"

*2. PS pin internal resistance value: 1 MΩ to 10 MΩ (1 MΩ step)
*3. PS pin voltage "H": VSS + 0.75 V, VDD − 0.90 V
*4. PS pin voltage "L": VSS + 0.70 V, VDD − 0.95 V
*5. 0 V battery charge: Enabled, inhibited

Remark 1. Please contact our sales representatives for products other than the above.
2. The delay times can be changed within the range listed in Table 6.
For details, please contact our sales representatives.

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BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-82B2A/B Series Rev.2.3_00

3. 2. 2 HSNT-8(1616)

Table 5 (1 / 3)

Discharge Discharge Load Short- Charge

Overcharge Overcharge Overdischarge Overdischarge
Overcurrent 1 Overcurrent 2 circuiting Overcurrent
Detection Release Detection Release
Product Name Detection Detection Detection Detection
Voltage Voltage Voltage Voltage
Voltage Voltage Voltage Voltage
[VCU] [VCL] [VDL] [VDU]
[VDIOV1] [VDIOV2] [VSHORT] [VCIOV]
S-82B2BAA-A8T2U7 4.475 V 4.325 V 2.100 V 2.300 V 7.0 mV 15 mV 30 mV −7.0 mV

Table 5 (2 / 3)

Discharge Discharge Load Short- Charge

Overcharge Overdischarge
Overcurrent 1 Overcurrent 2 circuiting Overcurrent Power-saving
Detection Detection
Product Name Detection Detection Detection Detection Delay Time
Delay Time Delay Time
Delay Time Delay Time Delay Time Delay Time [tPS]
[tCU] [tDL]
[tDIOV1] [tDIOV2] [tSHORT] [tCIOV]
S-82B2BAA-A8T2U7 1.0 s 64 ms 3.75 s 16 ms 280 μs 16 ms 2 ms

Table 5 (3 / 3)

PS Pin PS Pin Internal Resistance PS Pin Voltage "H"*3 PS Pin Voltage "L"*4 0 V Battery
Product Name
Control Logic*1 Value*2 [RPS] [VPSH] [VPSL] Charge*5
S-82B2BAA-A8T2U7 Active "H" 5 MΩ VDD − 0.90 V VSS + 0.70 V Inhibited

*1. PS pin control logic: Active "H", active "L"

*2. PS pin internal resistance value: 1 MΩ to 10 MΩ (1 MΩ step)
*3. PS pin voltage "H": VSS + 0.75 V, VDD − 0.90 V
*4. PS pin voltage "L": VSS + 0.70 V, VDD − 0.95 V
*5. 0 V battery charge: Enabled, inhibited

Remark 1. Please contact our sales representatives for products other than the above.
2. The delay times can be changed within the range listed in Table 6.
For details, please contact our sales representatives.

Table 6

Delay Time Symbol Selection Range Remark

Overcharge detection delay time tCU 256 ms 512 ms 1.0 s − − − Select a value from the left.
Overdischarge detection delay time tDL 32 ms 64 ms 128 ms − − − Select a value from the left.
8 ms 16 ms 32 ms 64 ms 128 ms 256 ms
Discharge overcurrent 1 detection
tDIOV1 512 ms 1.0 s 1.28 s 2.0 s 3.0 s 3.75 s Select a value from the left.
delay time
4.0 s − − − − −
Discharge overcurrent 2 detection
tDIOV2 4 ms 8 ms 16 ms 32 ms 64 ms 128 ms Select a value from the left.
delay time
Load short-circuiting detection delay time tSHORT 280 μs 530 μs − − − − Select a value from the left.
Charge overcurrent detection delay time tCIOV 4 ms 8 ms 16 ms 32 ms 64 ms 128 ms Select a value from the left.
Charge-discharge inhibition delay time tCTL 2 ms 4 ms 48 ms 64 ms 128 ms 256 ms Select a value from the left.
Power-saving delay time tPS 2 ms 4 ms 48 ms 64 ms 128 ms 256 ms Select a value from the left.

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 BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
Rev.2.3_00 S-82B2A/B Series

 Pin Configuration
1. SNT-8A
Table 7 S-82B2A Series
Top view
Pin No. Symbol Description
1 8
2 7 1 CTL Input pin for charge-discharge control signal
3 6 2 VM Input pin for external negative voltage
4 5
3 CO Connection pin of charge control FET gate (CMOS output)
4 DO Connection pin of discharge control FET gate (CMOS output)
Figure 3
5 VINI Overcurrent detection pin
Input pin for negative power supply,
6 VSS
connection pin for negative voltage of battery 2
Connection pin for negative voltage of battery 1,
7 VC
connection pin for positive voltage of battery 2
Input pin for positive power supply,
8 VDD
connection pin for positive voltage of battery 1

Table 8 S-82B2B Series

Pin No. Symbol Description

1 PS Input pin for power-saving signal
2 VM Input pin for external negative voltage
3 CO Connection pin of charge control FET gate (CMOS output)
4 DO Connection pin of discharge control FET gate (CMOS output)
5 VINI Overcurrent detection pin
Input pin for negative power supply,
6 VSS
connection pin for negative voltage of battery 2
Connection pin for negative voltage of battery 1,
7 VC
connection pin for positive voltage of battery 2
Input pin for positive power supply,
8 VDD
connection pin for positive voltage of battery 1

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BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-82B2A/B Series Rev.2.3_00

2. HSNT-8(1616)
Table 9 S-82B2A Series
Top view
Pin No. Symbol Description
1 8
1 CTL Input pin for charge-discharge control signal
4 5 2 VM Input pin for external negative voltage
3 CO Connection pin of charge control FET gate (CMOS output)
Bottom view 4 DO Connection pin of discharge control FET gate (CMOS output)
8 1 5 VINI Overcurrent detection pin
Input pin for negative power supply,
5 4 6 VSS
connection pin for negative voltage of battery 2
*1 Connection pin for negative voltage of battery 1,
7 VC
Figure 4 connection pin for positive voltage of battery 2
Input pin for positive power supply,
8 VDD
connection pin for positive voltage of battery 1

Table 10 S-82B2B Series

Pin No. Symbol Description

1 PS Input pin for power-saving signal
2 VM Input pin for external negative voltage
3 CO Connection pin of charge control FET gate (CMOS output)
4 DO Connection pin of discharge control FET gate (CMOS output)
5 VINI Overcurrent detection pin
Input pin for negative power supply,
6 VSS
connection pin for negative voltage of battery 2
Connection pin for negative voltage of battery 1,
7 VC
connection pin for positive voltage of battery 2
Input pin for positive power supply,
8 VDD
connection pin for positive voltage of battery 1

*1. Connect the heat sink of backside at shadowed area to the board, and set electric potential open or VDD.
However, do not use it as the function of electrode.

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 BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
Rev.2.3_00 S-82B2A/B Series

 Absolute Maximum Ratings

Table 11
(Ta = +25°C unless otherwise specified)
Item Symbol Applied Pin Absolute Maximum Rating Unit
Input voltage between VDD pin and VSS pin VDS VDD VSS − 0.3 to VSS + 12 V
VC pin input voltage VVC VC VDD − 12 to VDD + 0.3 V
VINI pin input voltage VVINI VINI VDD − 12 to VDD + 0.3 V
CTL pin input voltage (S-82B2A Series) VCTL CTL VDD − 12 to VDD + 0.3 V
PS pin input voltage (S-82B2B Series) VPS PS VDD − 12 to VDD + 0.3 V
VM pin input voltage VVM VM VDD − 28 to VDD + 0.3 V
DO pin output voltage VDO DO VSS − 0.3 to VDD + 0.3 V
CO pin output voltage VCO CO VVM − 0.3 to VDD + 0.3 V
Operation ambient temperature Topr − −40 to +85 °C
Storage temperature Tstg − −55 to +125 °C
Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage.
These values must therefore not be exceeded under any conditions.

 Thermal Resistance Value

Table 12

Item Symbol Condition Min. Typ. Max. Unit

Board A − 211 − °C/W
Board B − 173 − °C/W
SNT-8A Board C − − − °C/W
Board D − − − °C/W
Board E − − − °C/W
Junction-to-ambient thermal resistance*1 θJA
Board A − 214 − °C/W
Board B − 172 − °C/W
HSNT-8(1616) Board C − − − °C/W
Board D − − − °C/W
Board E − − − °C/W
*1. Test environment: compliance with JEDEC STANDARD JESD51-2A

Remark Refer to " Power Dissipation" and "Test Board" for details.

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BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-82B2A/B Series Rev.2.3_00

 Electrical Characteristics
1. Ta = +25°C
Table 13 (1 / 2)
(Ta = +25°C unless otherwise specified)
Test
Item Symbol Condition Min. Typ. Max. Unit
Circuit
Detection Voltage
Overcharge detection voltage n VCUn − VCU − 0.020 VCU VCU + 0.020 V 1
VCL ≠ VCU VCL − 0.050 VCL VCL + 0.050 V 1
Overcharge release voltage n VCLn
VCL = VCU VCL − 0.025 VCL VCL + 0.020 V 1
Overdischarge detection voltage n VDLn − VDL − 0.050 VDL VDL + 0.050 V 2
VDL ≠ VDU VDU − 0.075 VDU VDU + 0.075 V 2
Overdischarge release voltage n VDUn
VDL = VDU VDU − 0.050 VDU VDU + 0.050 V 2
Discharge overcurrent 1
VDIOV1 − VDIOV1 − 3 VDIOV1 VDIOV1 + 3 mV 5
detection voltage
Discharge overcurrent 2
VDIOV2 − VDIOV2 − 5 VDIOV2 VDIOV2 + 5 mV 2
detection voltage
Load short-circuiting
VSHORT − VSHORT − 10 VSHORT VSHORT + 10 mV 2
detection voltage
Load short-circuiting 2
VSHORT2 − VDD − 1.2 VDD − 0.9 VDD − 0.6 V 2
detection voltage
Charge overcurrent
VCIOV − VCIOV − 3 VCIOV VCIOV + 3 mV 2
detection voltage
Discharge overcurrent
VRIOV V1 = V2 = 3.4 V VDD − 1.3 VDD − 1.2 VDD − 1.1 V 5
release voltage
0 V Battery Charge
0 V battery charge starting charger 0 V battery charge
V0CHA 0.7 1.1 1.5 V 4
voltage enabled
0 V battery charge inhibition 0 V battery charge
V0INHn 1.00 1.25 1.40 V 2
battery voltage n inhibited
Internal Resistance
Resistance between VDD pin and V1 = V2 = 1.8 V,
RVMD 1000 2500 5000 kΩ 3
VM pin VVM = 0 V
Resistance between VDD pin and
RVMD2 S-82B2B Series 12 18 24 kΩ 3
VM pin 2
Resistance between VM pin and V1 = V2 = 3.4 V,
RVMS 3.5 7 14 kΩ 3
VSS pin VVM = 1.0 V
CTL pin internal resistance RCTL S-82B2A Series RCTL × 0.5 RCTL RCTL × 2.0 MΩ 3
PS pin internal resistance RPS S-82B2B Series RPS × 0.5 RPS RPS × 2.0 MΩ 3
Input Voltage
Operation voltage between VDD
VDSOP1 − 1.5 − 10 V −
pin and VSS pin
Operation voltage between VDD
VDSOP2 − 1.5 − 28 V −
pin and VM pin
CTL pin voltage "H" VCTLH S-82B2A Series VCTLH − 0.3 VCTLH VCTLH + 0.3 V 2
CTL pin voltage "L" VCTLL S-82B2A Series VCTLL − 0.3 VCTLL VCTLL + 0.3 V 2
PS pin voltage "H" VPSH S-82B2B Series VPSH − 0.3 VPSH VPSH + 0.3 V 2
PS pin voltage "L" VPSL S-82B2B Series VPSL − 0.3 VPSL VPSL + 0.3 V 2

Remark n = 1, 2

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 BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
Rev.2.3_00 S-82B2A/B Series

Table 13 (2 / 2)
(Ta = +25°C unless otherwise specified)
Test
Item Symbol Condition Min. Typ. Max. Unit
Circuit
Input Current
Current consumption during V1 = V2 = 3.4 V,
IOPE − 3.0 6.0 μA 3
operation VVM = 0 V
V1 = V2 = 3.4 V,
VC pin current IVC −0.1 0.0 0.1 μA 3
VVM = 0 V
Current consumption during V1 = V2 = 1.5 V,
IPDN − − 50 nA 3
power-down VVM = 3.0 V
Current consumption during V1 = V2 = 1.5 V,
IOPED − − 1.0 μA 3
overdischarge VVM = 3.0 V
Current consumption during
IPS S-82B2B Series − − 50 nA 3
power-saving
Output Resistance
CO pin resistance "H" RCOH − 3 6 12 kΩ 4
CO pin resistance "L" RCOL − 1.5 3 6 kΩ 4
DO pin resistance "H" RDOH − 3.5 7 14 kΩ 4
DO pin resistance "L" RDOL − 1 2 4 kΩ 4
Delay Time
Overcharge detection delay time tCU − tCU × 0.7 tCU tCU × 1.3 − 5
Overdischarge detection
tDL − tDL × 0.7 tDL tDL × 1.3 − 5
delay time
Discharge overcurrent 1
tDIOV1 − tDIOV1 × 0.75 tDIOV1 tDIOV1 × 1.25 − 5
detection delay time
Discharge overcurrent 2
tDIOV2 − tDIOV2 × 0.7 tDIOV2 tDIOV2 × 1.3 − 5
detection delay time
Load short-circuiting
tSHORT − tSHORT × 0.7 tSHORT tSHORT × 1.3 − 5
detection delay time
Charge overcurrent
tCIOV − tCIOV × 0.7 tCIOV tCIOV × 1.3 − 5
detection delay time
Charge-discharge inhibition
tCTL S-82B2A Series tCTL × 0.7 tCTL tCTL × 1.3 − 5
delay time
Power-saving delay time tPS S-82B2B Series tPS × 0.7 tPS tPS × 1.3 − 5

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BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-82B2A/B Series Rev.2.3_00

2. Ta = −20°C to +60°C*1
Table 14 (1 / 2)
(Ta = −20°C to +60°C*1 unless otherwise specified)
Test
Item Symbol Condition Min. Typ. Max. Unit
Circuit
Detection Voltage
Overcharge detection voltage n VCUn − VCU − 0.025 VCU VCU + 0.025 V 1
VCL ≠ VCU VCL − 0.065 VCL VCL + 0.057 V 1
Overcharge release voltage n VCLn
VCL = VCU VCL − 0.030 VCL VCL + 0.025 V 1
Overdischarge detection voltage n VDLn − VDL − 0.060 VDL VDL + 0.055 V 2
VDL ≠ VDU VDU − 0.085 VDU VDU + 0.080 V 2
Overdischarge release voltage n VDUn
VDL = VDU VDU − 0.060 VDU VDU + 0.055 V 2
Discharge overcurrent 1
VDIOV1 − VDIOV1 − 5 VDIOV1 VDIOV1 + 5 mV 5
detection voltage
Discharge overcurrent 2
VDIOV2 − VDIOV2 − 8 VDIOV2 VDIOV2 + 8 mV 2
detection voltage
Load short-circuiting
VSHORT − VSHORT − 20 VSHORT VSHORT + 20 mV 2
detection voltage
Load short-circuiting 2
VSHORT2 − VDD − 1.3 VDD − 0.9 VDD − 0.5 V 2
detection voltage
Charge overcurrent detection
VCIOV − VCIOV − 5 VCIOV VCIOV + 5 mV 2
voltage
Discharge overcurrent release
VRIOV V1 = V2 = 3.4 V VDD − 1.3 VDD − 1.2 VDD − 1.1 V 5
voltage
0 V Battery Charge
0 V battery charge starting charger 0 V battery charge
V0CHA 0.5 1.1 1.7 V 4
voltage enabled
0 V battery charge inhibition 0 V battery charge
V0INHn 1.00 1.25 1.40 V 2
battery voltage n inhibited
Internal Resistance
Resistance between VDD pin and V1 = V2 = 1.8 V,
RVMD 500 2500 7000 kΩ 3
VM pin VVM = 0 V
Resistance between VDD pin and
RVMD2 S-82B2B Series 8 18 30 kΩ 3
VM pin 2
Resistance between VM pin and V1 = V2 = 1.5 V,
RVMS 3.5 7 14 kΩ 3
VSS pin VVM = 3.0 V
CTL pin internal resistance RCTL S-82B2A Series RCTL × 0.25 RCTL RCTL × 3.0 MΩ 3
PS pin internal resistance RPS S-82B2B Series RPS × 0.25 RPS RPS × 3.0 MΩ 3
Input Voltage
Operation voltage between VDD
VDSOP1 − 1.5 − 10 V −
pin and VSS pin
Operation voltage between VDD
VDSOP2 − 1.5 − 28 V −
pin and VM pin
CTL pin voltage "H" VCTLH S-82B2A Series VCTLH − 0.4 VCTLH VCTLH + 0.4 V 2
CTL pin voltage "L" VCTLL S-82B2A Series VCTLL − 0.4 VCTLL VCTLL + 0.4 V 2
PS pin voltage "H" VPSH S-82B2B Series VPSH − 0.4 VPSH VPSH + 0.4 V 2
PS pin voltage "L" VPSL S-82B2B Series VPSL − 0.4 VPSL VPSL + 0.4 V 2

Remark n = 1, 2

14
 BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
Rev.2.3_00 S-82B2A/B Series

Table 14 (2 / 2)
(Ta = −20°C to +60°C*1 unless otherwise specified)
Test
Item Symbol Condition Min. Typ. Max. Unit
Circuit
Input Current
Current consumption during V1 = V2 = 3.4 V,
IOPE − 3.0 7.0 μA 3
operation VVM = 0 V
V1 = V2 = 3.4 V,
VC pin current IVC −0.1 0.0 0.1 μA 3
VVM = 0 V
Current consumption during V1 = V2 = 1.5 V,
IPDN − − 100 nA 3
power-down VVM = 3.0 V
Current consumption during V1 = V2 = 1.5 V,
IOPED − − 1.2 μA 3
overdischarge VVM = 3.0 V
Current consumption during
IPS S-82B2B Series − − 100 nA 3
power-saving
Output Resistance
CO pin resistance "H" RCOH − 1.5 6 18 kΩ 4
CO pin resistance "L" RCOL − 0.75 3 9 kΩ 4
DO pin resistance "H" RDOH − 1.8 7 21 kΩ 4
DO pin resistance "L" RDOL − 0.5 2 6 kΩ 4
Delay Time
Overcharge detection delay time tCU − tCU × 0.6 tCU tCU × 1.4 − 5
Overdischarge detection
tDL − tDL × 0.6 tDL tDL × 1.4 − 5
delay time
Discharge overcurrent 1
tDIOV1 − tDIOV1 × 0.65 tDIOV1 tDIOV1 × 1.35 − 5
detection delay time
Discharge overcurrent 2
tDIOV2 − tDIOV2 × 0.6 tDIOV2 tDIOV2 × 1.4 − 5
detection delay time
Load short-circuiting
tSHORT − tSHORT × 0.6 tSHORT tSHORT × 1.4 − 5
detection delay time
Charge overcurrent
tCIOV − tCIOV × 0.6 tCIOV tCIOV × 1.4 − 5
detection delay time
Charge-discharge inhibition
tCTL S-82B2A Series tCTL × 0.6 tCTL tCTL × 1.4 − 5
delay time
Power-saving delay time tPS S-82B2B Series tPS × 0.6 tPS tPS × 1.4 − 5
*1. Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed
by design, not tested in production.

15
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-82B2A/B Series Rev.2.3_00

3. Ta = −40°C to +85°C*1
Table 15 (1 / 2)
(Ta = −40°C to +85°C*1 unless otherwise specified)
Test
Item Symbol Condition Min. Typ. Max. Unit
Circuit
Detection Voltage
Overcharge detection voltage n VCUn − VCU − 0.050 VCU VCU + 0.035 V 1
VCL ≠ VCU VCL − 0.080 VCL VCL + 0.060 V 1
Overcharge release voltage n VCLn
VCL = VCU VCL − 0.055 VCL VCL + 0.035 V 1
Overdischarge detection voltage n VDLn − VDL − 0.060 VDL VDL + 0.060 V 2
VDL ≠ VDU VDU − 0.105 VDU VDU + 0.085 V 2
Overdischarge release voltage n VDUn
VDL = VDU VDU − 0.080 VDU VDU + 0.060 V 2
Discharge overcurrent 1
VDIOV1 − VDIOV1 − 5 VDIOV1 VDIOV1 + 5 mV 5
detection voltage
Discharge overcurrent 2
VDIOV2 − VDIOV2 − 8 VDIOV2 VDIOV2 + 8 mV 2
detection voltage
Load short-circuiting
VSHORT − VSHORT − 20 VSHORT VSHORT + 20 mV 2
detection voltage
Load short-circuiting 2
VSHORT2 − VDD − 1.4 VDD − 0.9 VDD − 0.3 V 2
detection voltage
Charge overcurrent detection
VCIOV − VCIOV − 5 VCIOV VCIOV + 5 mV 2
voltage
Discharge overcurrent release
VRIOV V1 = V2 = 3.4 V VDD − 1.3 VDD − 1.2 VDD − 1.1 V 5
voltage
0 V Battery Charge
0 V battery charge starting charger 0 V battery charge
V0CHA 0.5 1.1 1.7 V 4
voltage enabled
0 V battery charge inhibition 0 V battery charge
V0INHn 1.00 1.25 1.40 V 2
battery voltage n inhibited
Internal Resistance
Resistance between VDD pin and V1 = V2 = 1.8 V,
RVMD 500 2500 7000 kΩ 3
VM pin VVM = 0 V
Resistance between VDD pin and
RVMD2 S-82B2B Series 8 18 30 kΩ 3
VM pin 2
Resistance between VM pin and V1 = V2 = 1.5 V,
RVMS 3.5 7 14 kΩ 3
VSS pin VVM = 3.0 V
CTL pin internal resistance RCTL S-82B2A Series RCTL × 0.25 RCTL RCTL × 3.0 MΩ 3
PS pin internal resistance RPS S-82B2B Series RPS × 0.25 RPS RPS × 3.0 MΩ 3
Input Voltage
Operation voltage between VDD
VDSOP1 − 1.5 − 10 V −
pin and VSS pin
Operation voltage between VDD
VDSOP2 − 1.5 − 28 V −
pin and VM pin
CTL pin voltage "H" VCTLH S-82B2A Series VCTLH − 0.4 VCTLH VCTLH + 0.4 V 2
CTL pin voltage "L" VCTLL S-82B2A Series VCTLL − 0.4 VCTLL VCTLL + 0.4 V 2
PS pin voltage "H" VPSH S-82B2B Series VPSH − 0.4 VPSH VPSH + 0.4 V 2
PS pin voltage "L" VPSL S-82B2B Series VPSL − 0.4 VPSL VPSL + 0.4 V 2

Remark n = 1, 2

16
 BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
Rev.2.3_00 S-82B2A/B Series

Table 15 (2 / 2)
(Ta = −40°C to +85°C*1 unless otherwise specified)
Test
Item Symbol Condition Min. Typ. Max. Unit
Circuit
Input Current
Current consumption during V1 = V2 = 3.4 V,
IOPE − 3.0 7.0 μA 3
operation VVM = 0 V
V1 = V2 = 3.4 V,
VC pin current IVC −0.15 0.0 0.15 μA 3
VVM = 0 V
Current consumption during V1 = V2 = 1.5 V,
IPDN − − 150 nA 3
power-down VVM = 3.0 V
Current consumption during V1 = V2 = 1.5 V,
IOPED − − 1.2 μA 3
overdischarge VVM = 3.0 V
Current consumption during
IPS S-82B2B Series − − 150 nA 3
power-saving
Output Resistance
CO pin resistance "H" RCOH − 1.5 6 18 kΩ 4
CO pin resistance "L" RCOL − 0.75 3 9 kΩ 4
DO pin resistance "H" RDOH − 1.8 7 21 kΩ 4
DO pin resistance "L" RDOL − 0.5 2 6 kΩ 4
Delay Time
Overcharge detection delay time tCU − tCU × 0.4 tCU tCU × 1.6 − 5
Overdischarge detection
tDL − tDL × 0.4 tDL tDL × 1.6 − 5
delay time
Discharge overcurrent 1
tDIOV1 − tDIOV1 × 0.4 tDIOV1 tDIOV1 × 1.6 − 5
detection delay time
Discharge overcurrent 2
tDIOV2 − tDIOV2 × 0.4 tDIOV2 tDIOV2 × 1.6 − 5
detection delay time
Load short-circuiting
tSHORT − tSHORT × 0.4 tSHORT tSHORT × 1.6 − 5
detection delay time
Charge overcurrent
tCIOV − tCIOV × 0.4 tCIOV tCIOV × 1.6 − 5
detection delay time
Charge-discharge inhibition
tCTL S-82B2A Series tCTL × 0.4 tCTL tCTL × 1.6 − 5
delay time
Power-saving delay time tPS S-82B2B Series tPS × 0.4 tPS tPS × 1.6 − 5
*1. Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed
by design, not tested in production.

17
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-82B2A/B Series Rev.2.3_00

 Test Circuits
When CTL pin or PS pin control logic is active "H", SW1 and SW3 are turned off, SW2 and SW4 are turned on. When CTL
pin or PS pin control logic is active "L", SW1 and SW3 are turned on, SW2 and SW4 are turned off.

Caution Unless otherwise specified, the output voltage levels "H" and "L" at CO pin (VCO) and DO pin (VDO) are
judged by the threshold voltage (1.0 V) of the N-channel FET. Judge the CO pin level with respect to VVM
and the DO pin level with respect to VSS.

1. Overcharge detection voltage, overcharge release voltage

(Test circuit 1)
Overcharge detection voltage 1 (VCU1) is defined as the voltage V1 at which VCO goes from "H" to "L" when the voltage
V1 is gradually increased after setting V1 = V2 = VCU − 0.05 V. Overcharge release voltage 1 (VCL1) is defined as the
voltage V1 at which VCO goes from "L" to "H" when setting V2 = 3.4 V and when the voltage V1 is then gradually
decreased. Overcharge hysteresis voltage 1 (VHC1) is defined as the difference between VCU1 and VCL1.
Overcharge detection voltage 2 (VCU2), overcharge release voltage 2 (VCL2) and overcharge hysteresis voltage 2 (VHC2)
can be determined in the same way.

2. Overdischarge detection voltage, overdischarge release voltage

(Test circuit 2)
Overdischarge detection voltage 1 (VDL1) is defined as the voltage V1 at which VDO goes from "H" to "L" when the voltage
V1 is gradually decreased after setting V1 = V2 = 3.4 V, V3 = V6 = V7 = 0 V. Overdischarge release voltage 1 (VDU1) is
defined as the voltage V1 at which VDO goes from "L" to "H" when setting V3 = 0.01 V, V6 = V7 = 0 V and when the
voltage V1 is then gradually increased. Overdischarge hysteresis voltage 1 (VHD1) is defined as the difference between
VDU1 and VDL1.
Overdischarge detection voltage 2 (VDL2), overdischarge release voltage 2 (VDU2) and overdischarge hysteresis voltage
2 (VHD2) can be determined in the same way.

3. Discharge overcurrent 1 detection voltage, discharge overcurrent release voltage

(Test circuit 5)
Discharge overcurrent 1 detection voltage (VDIOV1) is defined as the voltage V6 at which delay time from when V6 is
increased after setting V1 = V2 = 3.4 V, V3 = 1.0 V, V6 = V7 = 0 V to when VDO goes from "H" to "L" is discharge
overcurrent 1 detection delay time (tDIOV1). Discharge overcurrent release voltage (VRIOV) is defined as the voltage V3 at
which VDO goes from "L" to "H" when setting V3 = 6.8 V, V6 = 0 V and when the voltage V3 is then gradually decreased.
When the voltage V3 falls below VRIOV, VDO will go to "H" after 1.0 ms typ. and maintain "H" during load short-circuiting
detection delay time (tSHORT).

4. Discharge overcurrent 2 detection voltage

(Test circuit 2)
Discharge overcurrent 2 detection voltage (VDIOV2) is defined as the voltage V6 at which delay time from when V6 is
increased after setting V1 = V2 = 3.4 V, V3 = 1.0 V, V6 = V7 = 0 V to when VDO goes from "H" to "L" is discharge
overcurrent 2 detection delay time (tDIOV2).

5. Load short-circuiting detection voltage

(Test circuit 2)
Load short-circuiting detection voltage (VSHORT) is defined as the voltage V6 at which delay time from when V6 is
increased after setting V1 = V2 = 3.4 V, V3 = 1.0 V, V6 = V7 = 0 V to when VDO goes from "H" to "L" is tSHORT.

6. Load short-circuiting 2 detection voltage

(Test circuit 2)
Load short-circuiting 2 detection voltage (VSHORT2) is defined as the voltage V3 at which delay time from when V3 is
increased after setting V1 = V2 = 3.4 V, V3 = V6 = V7 = 0 V to when VDO goes from "H" to "L" is tSHORT.

18
 BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
Rev.2.3_00 S-82B2A/B Series

7. Charge overcurrent detection voltage

(Test circuit 2)
Charge overcurrent detection voltage (VCIOV) is defined as the voltage V6 at which delay time from when V6 is decreased
after setting V1 = V2 = 3.4 V, V3 = V6 = V7 = 0 V to when VCO goes from "H" to "L" is charge overcurrent detection delay
time (tCIOV).

8. CTL pin voltage "H", CTL pin voltage "L" (S-82B2A Series)
(Test circuit 2)
8. 1 CTL pin control logic active "H"
The CTL pin voltage "H" (VCTLH) is defined as the voltage V7 at which VCO and VDO go from "H" to "L" when the voltage
V7 is gradually increased after setting V1 = V2 = 3.4 V, V3 = V6 = V7 = 0 V.
After that, the CTL pin voltage "L" (VCTLL) is defined as the voltage V7 at which VCO and VDO go from "L" to "H" after
V7 is gradually decreased.

8. 2 CTL pin control logic active "L"

VCTLL is defined as the voltage difference between the voltage V7 and the voltage V1 + V2 (V1 + V2 − V7) at which
VCO and VDO go from "H" to "L" when the voltage V7 is gradually increased after setting V1 = V2 = 3.4 V, V3 = V6 =
V7 = 0 V.
After that, VCTLH is defined as V1 + V2 − V7 at which VCO and VDO go from "L" to "H" after V7 is gradually decreased.

9. PS pin voltage "H", PS pin voltage "L" (S-82B2B Series)

(Test circuit 2)
9. 1 PS pin control logic active "H"
The PS pin voltage "H" (VPSH) is defined as the voltage V7 at which VCO and VDO go from "H" to "L" when the voltage
V7 is gradually increased after setting V1 = V2 = 3.4 V, V3 = V6 = V7 = 0 V.
After that, the PS pin voltage "L" (VPSL) is defined as the voltage V7 at which VCO and VDO go from "L" to "H" after V7
is gradually decreased.

9. 2 PS pin control logic active "L"

VPSL is defined as the voltage difference between the voltage V7 and the voltage V1 + V2 (V1 + V2 − V7) at which
VCO and VDO go from "H" to "L" when the voltage V7 is gradually increased after setting V1 = V2 = 3.4 V, V3 = V6 =
V7 = 0 V.
After that, VPSH is defined as V1 + V2 − V7 at which VCO and VDO go from "L" to "H" after V7 is gradually decreased.

10. Current consumption during operation

(Test circuit 3)
The current consumption during operation (IOPE) is the current that flows through the VDD pin (IDD) under the set
conditions of V1 = V2 = 3.4 V, V3 = V6 = V7 = 0 V. However, the current flowing through the CTL pin or the PS pin
internal resistance is excluded.

11. VC pin current

(Test circuit 3)
The VC pin current (IVC) is the current that flows through the VC pin under the set conditions of V1 = V2 = 3.4 V, V3 =
V6 = V7 = 0 V.

19
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-82B2A/B Series Rev.2.3_00

12. Current consumption during power-down, current consumption during overdischarge

(Test circuit 3)
12. 1 With power-down function
The current consumption during power-down (IPDN) is IDD under the set conditions of V1 = V2 = 1.5 V, V3 = 3.0 V, V6
= V7 = 0 V.

12. 2 Without power-down function

The current consumption during overdischarge (IOPED) is IDD under the set conditions of V1 = V2 = 1.5 V, V3 = 3.0 V,
V6 = V7 = 0 V.

13. Current consumption during power-saving (S-82B2B Series)

(Test circuit 3)
The current consumption during power-saving (IPS) is IDD under the set conditions of V1 = V2 = 3.4 V, V3 = 6.8 V, V6 =
0 V, V7 = 6.8 V.

14. Resistance between VDD pin and VM pin

(Test circuit 3)
RVMD is the resistance between VDD pin and VM pin under the set conditions of V1 = V2 = 1.8 V, V3 = V6 = V7 = 0 V.

15. Resistance between VDD pin and VM pin 2 (S-82B2B Series)

(Test circuit 3)
RVMD2 is the resistance between VDD pin and VM pin under the set conditions of V1 = V2 = 3.4 V, V3 = V6 = 0 V, V7 =
6.8 V.

16. Resistance between VM pin and VSS pin

(Test circuit 3)
RVMS is the resistance between VM pin and VSS pin when the voltage V6 is decreased to 0 V after setting V1 = V2 =
3.4 V, V3 = V6 = 1.0 V, V7 = 0 V.

17. CTL pin internal resistance (S-82B2A Series)

(Test circuit 3)
17. 1 CTL pin internal resistance connection "pull-up"
The CTL pin internal resistance (RCTL) is the resistance between CTL pin and VDD pin under the set conditions of V1
= V2 = 3.4 V, V3 = V6 = V7 = 0 V.

17. 2 CTL pin internal resistance connection "pull-down"

RCTL is the resistance between CTL pin and VSS pin under the set conditions of V1 = V2 = 3.4 V, V3 = V6 = 0 V, V7
= 6.8 V.

18. PS pin internal resistance (S-82B2B Series)

(Test circuit 3)
18. 1 PS pin control logic active "H"
The PS pin internal resistance (RPS) is the resistance between PS pin and VDD pin when the voltage V7 is decreased
to 3.4 V after setting V1 = V2 = 3.4 V, V3 = V6 = 0 V, V7 = 6.8 V.

18. 2 PS pin control logic active "L"

RPS is the resistance between PS pin and VSS pin when the voltage V7 is increased to 3.4 V after setting V1 = V2 =
3.4 V, V3 = V6 = V7 = 0 V.

20
 BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
Rev.2.3_00 S-82B2A/B Series

19. CO pin resistance "H"

(Test circuit 4)
The CO pin resistance "H" (RCOH) is the resistance between VDD pin and CO pin under the set conditions of V1 = V2 =
3.4 V, V3 = V6 = 0 V, V4 = 6.4 V.

20. CO pin resistance "L"

(Test circuit 4)
The CO pin resistance "L" (RCOL) is the resistance between VM pin and CO pin under the set conditions of V1 = V2 =
4.9 V, V3 = V6 = 0 V, V4 = 0.4 V.

21. DO pin resistance "H"

(Test circuit 4)
The DO pin resistance "H" (RDOH) is the resistance between VDD pin and DO pin under the set conditions of V1 = V2 =
3.4 V, V3 = V6 = 0 V, V5 = 6.4 V.

22. DO pin resistance "L"

(Test circuit 4)
The DO pin resistance "L" (RDOL) is the resistance between VSS pin and DO pin under the set conditions of V1 = V2 =
1.8 V, V3 = V6 = 0 V, V5 = 0.4 V.

23. Overcharge detection delay time

(Test circuit 5)
After setting V1 = V2 = 3.4 V, V3 = V6 = V7 = 0 V, the voltage V1 is increased. The time interval from when the voltage
V1 exceeds VCU until VCO goes to "L" is the overcharge detection delay time (tCU).

24. Overdischarge detection delay time

(Test circuit 5)
After setting V1 = V2 = 3.4 V, V3 = V6 = V7 = 0 V, the voltage V1 is decreased. The time interval from when the voltage
V1 falls below VDL until VDO goes to "L" is the overdischarge detection delay time (tDL).

25. Discharge overcurrent n detection delay time

(Test circuit 5)
After setting V1 = V2 = 3.4 V, V3 = 1.0 V, V6 = V7 = 0 V, the voltage V6 is increased. The time interval from when the
voltage V6 exceeds VDIOVn until VDO goes to "L" is the discharge overcurrent n detection delay time (tDIOVn).

26. Load short-circuiting detection delay time

(Test circuit 5)
After setting V1 = V2 = 3.4 V, V3 = 1.0 V, V6 = V7 = 0 V, the voltage V6 is increased. The time interval from when the
voltage V6 exceeds VSHORT until VDO goes to "L" is the load short-circuiting detection delay time (tSHORT).

27. Charge overcurrent detection delay time

(Test circuit 5)
After setting V1 = V2 = 3.4 V, V3 = V6 = V7 = 0 V, the voltage V6 is decreased. The time interval from when the voltage
V6 falls below VCIOV until VCO goes to "L" is the charge overcurrent detection delay time (tCIOV).

Remark n = 1, 2

21
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-82B2A/B Series Rev.2.3_00

28. Charge-discharge inhibition delay time (S-82B2A Series)

(Test circuit 5)
28. 1 CTL pin control logic active "H"
After setting V1 = V2 = 3.4 V, V3 = V6 = V7 = 0 V, the voltage V7 is increased. The time interval from when the voltage
V7 exceeds VCTLH until VCO and VDO go to "L" is the charge-discharge inhibition delay time (tCTL).

28. 2 CTL pin control logic active "L"

After setting V1 = V2 = 3.4 V, V3 = V6 = V7 = 0 V, the voltage V7 is increased. The time interval from when the voltage
V1 + V2 − V7 falls below VCTLL until VCO and VDO go to "L" is tCTL.

29. Power-saving delay time (S-82B2B Series)

(Test circuit 5)
29. 1 PS pin control logic active "H"
After setting V1 = V2 = 3.4 V, V3 = V6 = V7 = 0 V, the voltage V7 is increased. The time interval from when the voltage
V7 exceeds VPSH until VCO and VDO go to "L" is the power-saving delay time (tPS).

29. 2 PS pin control logic active "L"

After setting V1 = V2 = 3.4 V, V3 = V6 = V7 = 0 V, the voltage V7 is increased. The time interval from when the voltage
V1 + V2 − V7 falls below VPSL until VCO and VDO go to "L" is tPSL.

30. 0 V battery charge starting charger voltage (0 V battery charge enabled)

(Test circuit 4)
The 0 V battery charge starting charger voltage (V0CHA) is defined as the absolute value of voltage V3 at which the current
flowing through the CO pin (ICO) exceeds 1.0 μA when the voltage V3 is gradually decreased after setting V1 = V2 = V6
= 0 V, V3 = V4 = −0.5 V.

31. 0 V battery charge inhibition battery voltage n (0 V battery charge inhibited)

(Test circuit 2)
The 0 V battery charge inhibition battery voltage n (V0INHn) is defined as the voltage Vn at which VCO goes to "L" (VCO =
VVM) when the voltage Vn is gradually decreased after setting V1 = V2 = 1.5 V, V3 = −1.0 V, V6 = V7 = 0 V.

Remark n = 1, 2

22
 BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
Rev.2.3_00 S-82B2A/B Series

R1
= 100 Ω SW1 SW4 SW1
VDD CTL / PS VDD CTL / PS
V1 SW2 V1 V7
R2
= 100 Ω VC VC
V2 V2 SW3
SW2
VSS VM VSS VM
C1
= 0.1 μF VINI DO CO VINI DO CO
C2
= 0.1 μF
V VDO V VCO V6 V VDO V VCO V3

COM COM

Figure 5 Test Circuit 1 Figure 6 Test Circuit 2

IDD ICTL / IPS_IN SW1 SW1

A VDD CTL / PS A VDD CTL / PS
V1 SW4
V1 SW2
A VC V7
VC
IVC
V2
V2 SW3
VSS VM SW2 VSS VM
VINI DO CO VINI DO CO
IVM A

A IDO A ICO
V6 V3 V6 V3
V5 V4

COM COM

Figure 7 Test Circuit 3 Figure 8 Test Circuit 4

SW4 SW1
VDD CTL / PS
V1 V7
VC
V2 SW3
SW2
VSS VM
VINI DO CO

V6 Oscilloscope Oscilloscope V3

COM

Figure 9 Test Circuit 5

23
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-82B2A/B Series Rev.2.3_00

 Operation
Remark Refer to " Battery Protection IC Connection Example".

1. Normal status
This IC monitors the voltage of the battery connected between VDD pin and VC pin, VC pin and VSS pin, and the voltage
between VINI pin and VSS pin to control charging and discharging.

When the battery voltage is in the range from overdischarge detection voltage (VDL) to overcharge detection voltage
(VCU), the VINI pin voltage is in the range from charge overcurrent detection voltage (VCIOV) to discharge overcurrent 1
detection voltage (VDIOV1), both charge and discharge control FETs are turned on. This status is called the normal status,
and in this condition charging and discharging can be carried out freely.
Also, for the S-82B2A Series, input the voltage that releases the charge-discharge inhibition status to the CTL pin*1, and
for the S-82B2B Series, input the voltage that releases the power-saving status to the PS pin*2.
The resistance between VDD pin and VM pin (RVMD), and the resistance between VM pin and VSS pin (RVMS) are not
connected in the normal status.

*1. Refer to "6. Charge-discharge inhibition status (S-82B2A Series)".

*2. Refer to "7. Power-saving status (S-82B2B Series)".

Caution After the battery is connected, discharging may not be carried out. In this case, this IC returns to the
normal status by connecting a charger.

2. Overcharge status
2. 1 VCL ≠ VCU (Product in which overcharge release voltage differs from overcharge detection voltage)

When the battery voltage becomes higher than VCU during charging in the normal status and the status continues for
the overcharge detection delay time (tCU) or longer, the charge control FET is turned off and charging is stopped. This
status is called the overcharge status.
The overcharge status is released in the following two cases.

(1) In the case that the VM pin voltage is lower than 0.35 V typ., this IC releases the overcharge status when the
battery voltage falls below overcharge release voltage (VCL).
(2) In the case that the VM pin voltage is equal to or higher than 0.35 V typ., this IC releases the overcharge status
when the battery voltage falls below VCU.

When the discharge is started by connecting a load after the overcharge detection, the VM pin voltage rises by the Vf
voltage of the internal parasitic diode than the VSS pin voltage, because the discharge current flows through the
parasitic diode in the charge control FET. If this VM pin voltage is equal to or higher than 0.35 V typ., this IC releases
the overcharge status when the battery voltage is equal to or lower than VCU.

Caution If the battery is charged to a voltage higher than VCU and the battery voltage does not fall below
VCU even when a heavy load is connected, discharge overcurrent detection and load short-
circuiting detection do not function until the battery voltage falls below VCU. Since an actual battery
has an internal impedance of tens of mΩ, the battery voltage drops immediately after a heavy load
that causes overcurrent is connected, and discharge overcurrent detection and load short-
circuiting detection function.

24
 BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
Rev.2.3_00 S-82B2A/B Series

2. 2 VCL = VCU (Product in which overcharge release voltage is the same as overcharge detection voltage)
When the battery voltage becomes higher than VCU during charging in the normal status and the status continues for
tCU or longer, the charge control FET is turned off and charging is stopped. This status is called the overcharge status.
In the case that the VM pin voltage is equal to or higher than 0.35 V typ. and the battery voltage falls below VCU, this
IC releases the overcharge status.

When the discharge is started by connecting a load after the overcharge detection, the VM pin voltage rises by the Vf
voltage of the internal parasitic diode than the VSS pin voltage, because the discharge current flows through the
parasitic diode in the charge control FET. If this VM pin voltage is equal to or higher than 0.35 V typ., this IC releases
the overcharge status when the battery voltage is equal to or lower than VCU.

Caution 1. If the battery is charged to a voltage higher than VCU and the battery voltage does not fall below
VCU even when a heavy load is connected, discharge overcurrent detection and load short-
circuiting detection do not function until the battery voltage falls below VCU. Since an actual
battery has an internal impedance of tens of mΩ, the battery voltage drops immediately after a
heavy load that causes overcurrent is connected, and discharge overcurrent detection and load
short-circuiting detection function.
2. When a charger is connected after overcharge detection, the overcharge status is not released
even if the battery voltage is below VCL. The overcharge status is released when the discharge
current flows and the VM pin voltage goes over 0.35 V typ. by removing the charger.

3. Overdischarge status
When the battery voltage falls below VDL during discharging in the normal status and the status continues for the
overdischarge detection delay time (tDL) or longer, the discharge control FET is turned off and discharging is stopped.
This status is called the overdischarge status.
Under the overdischarge status, VDD pin and VM pin are shorted by RVMD in this IC. The VM pin voltage is pulled up by
RVMD.
When connecting a charger in the overdischarge status, the battery voltage reaches VDL or higher and this IC releases
the overdischarge status if the VM pin voltage is below 0 V typ.
The battery voltage reaches the overdischarge release voltage (VDU) or higher and this IC releases the overdischarge
status if the VM pin voltage is not below 0 V typ.
RVMS is not connected in the overdischarge status.

3. 1 With power-down function

Under the overdischarge status, when the VM pin voltage is 0.7 V typ. or higher, the power-down function works and
the current consumption is reduced to the current consumption during power-down (IPDN). By connecting a battery
charger, the power-down function is released when the VM pin voltage is 0.7 V typ. or lower.

• When a battery is not connected to a charger and the VM pin voltage ≥ 0.7 V typ., this IC maintains the
overdischarge status even when the battery voltage reaches VDU or higher.
• When a battery is connected to a charger and 0.7 V typ. > the VM pin voltage > 0 V typ., the battery voltage
reaches VDU or higher and this IC releases the overdischarge status.
• When a battery is connected to a charger and 0 V typ. ≥ the VM pin voltage, the battery voltage reaches VDL or
higher and this IC releases the overdischarge status.

3. 2 Without power-down function

Under the overdischarge status, the power-down function does not work even when the VM pin voltage is 0.7 V typ.
or higher.

• When a battery is not connected to a charger and the VM pin voltage ≥ 0.7 V typ., the battery voltage reaches VDU
or higher and this IC releases the overdischarge status.
• When a battery is connected to a charger and 0.7 V typ. > the VM pin voltage > 0 V typ., the battery voltage reaches
VDU or higher and this IC releases the overdischarge status.
• When a battery is connected to a charger and 0 V typ. ≥ the VM pin voltage, the battery voltage reaches VDL or
higher and this IC releases the overdischarge status.

25
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-82B2A/B Series Rev.2.3_00

4. Discharge overcurrent status

(discharge overcurrent 1, discharge overcurrent 2, load short- circuiting, load short-circuiting 2)
4. 1 Discharge overcurrent 1, discharge overcurrent 2, load short-circuiting
When a battery in the normal status is in the status where the VINI pin voltage is equal to or higher than VDIOV1
because the discharge current is equal to or higher than the specified value and the status continues for the discharge
overcurrent 1 detection delay time (tDIOV1) or longer, the discharge control FET is turned off and discharging is stopped.
This status is called the discharge overcurrent status.
Under the discharge overcurrent status, VM pin and VSS pin are shorted by RVMS in this IC. However, the VM pin
voltage is the VDD pin voltage due to the load as long as the load is connected. When the load is disconnected, VM
pin returns to the VSS pin voltage.
When the VM pin voltage returns to VRIOV or lower, this IC releases the discharge overcurrent status.
RVMD is not connected in the discharge overcurrent status.

4. 2 Load short-circuiting 2
When a battery in the normal status is in the status where a load causing discharge overcurrent is connected, and the
VM pin voltage is equal to or higher than VSHORT2 and the status continues for the load short-circuiting detection delay
time (tSHORT) or longer, the discharge control FET is turned off and discharging is stopped. This status is called the
discharge overcurrent status.
This IC releases the discharge overcurrent status in the same way as in "4. 1 Discharge overcurrent 1, discharge
overcurrent 2, load short-circuiting".

5. Charge overcurrent status

When a battery in the normal status is in the status where the VINI pin voltage is equal to or lower than VCIOV because
the charge current is equal to or higher than the specified value and the status continues for the charge overcurrent
detection delay time (tCIOV) or longer, the charge control FET is turned off and charging is stopped. This status is called
the charge overcurrent status.
This IC releases the charge overcurrent status when the discharge current flows and the VM pin voltage is 0.35 V typ.
or higher by removing the charger.
The charge overcurrent detection does not function in the overdischarge status.

26
 BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
Rev.2.3_00 S-82B2A/B Series

6. Charge-discharge inhibition status (S-82B2A Series)

6. 1 CTL pin control logic active "H"
When the CTL pin voltage is equal to or higher than CTL pin voltage "H" (VCTLH) and the status continues for the
charge-discharge inhibition delay time (tCTL) or longer, the charge control FET and the discharge control FET are
turned off, and charging and discharging are stopped. This status is called the charge-discharge inhibition status.
This IC releases charge-discharge inhibition status when the CTL pin voltage is equal to or lower than CTL pin voltage
"L" (VCTLL).

6. 2 CTL pin control logic active "L"

When the CTL pin voltage is equal to or lower than VCTLL and the status continues for tCTL or longer, the charge control
FET and the discharge control FET are turned off, and charging and discharging are stopped. This status is called
the charge-discharge inhibition status.
This IC releases charge-discharge inhibition status when the CTL pin voltage is equal to or higher than VCTLH.

6. 3 CTL pin internal resistance connection

6. 3. 1 CTL pin internal resistance connection "pull-up"

The CTL pin is shorted to the VDD pin by the CTL pin internal resistance (RCTL).

6. 3. 2 CTL pin internal resistance connection "pull-down"

The CTL pin is shorted to the VSS pin by RCTL.

When the power-down function works, RCTL is disconnected, and the input current and the output current to the CTL
pin are cut off.
The charge-discharge control by the CTL pin does not function in the overdischarge status.

7. Power-saving status (S-82B2B Series)

7. 1 PS pin control logic active "H"
When the PS pin voltage is equal to or higher than PS pin voltage "H" (VPSH) and the status continues for the power-
saving delay time (tPS) or longer, the charge control FET and the discharge control FET are turned off, and charging
and discharging are stopped. This status is called the power-saving status.
In the power-saving status, PS pin internal resistance (RPS) is shorted to the VDD pin, and the VM pin is pulled-up by
resistance between VDD pin and VM pin 2 (RVMD2) and is shorted to the VDD pin, reducing current consumption down
to current consumption during power-saving (IPS).
When PS pin voltage falls below PS pin voltage "L" (VPSL), power-saving status is released and RPS is shorted to the
VSS pin. At this time, RVMD2 is not connected.

7. 2 PS pin control logic active "L"

When the PS pin voltage is equal to or lower than VPSL and the status continues for tPS or longer, the charge control
FET and the discharge control FET are turned off, and charging and discharging are stopped. This status is called
the power-saving status.
In the power-saving status, RPS is shorted to the VSS pin, and the VM pin is pulled-up by RVMD2 and is shorted to the
VDD pin, reducing current consumption down to IPS.
When PS pin voltage reaches VPSH or higher, power-saving status is released and RPS is shorted to the VDD pin. At
this time, RVMD2 is not connected.

When the power-down function works, RPS is disconnected, and the input current and the output current to the PS pin
are cut off.
The charge-discharge control by the PS pin does not function in the overcharge status and the overdischarge status.

27
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-82B2A/B Series Rev.2.3_00

8. 0 V battery charge enabled

This function is used to recharge a connected battery whose voltage is 0 V due to self-discharge. When the 0 V battery
charge starting charger voltage (V0CHA) or a higher voltage is applied between the EB+ and EB− pins by connecting a
charger, the charge control FET gate is fixed to the VDD pin voltage.
When the voltage between the gate and source of the charge control FET becomes equal to or higher than the threshold
voltage due to the charger voltage, the charge control FET is turned on to start charging. At this time, the discharge
control FET is off and the charging current flows through the internal parasitic diode in the discharge control FET. When
the battery voltage becomes equal to or higher than VDL, this IC returns to the normal status.

Caution 1. Some battery providers do not recommend charging for a completely self-discharged lithium-ion
rechargeable battery. It depends on the characteristics of the lithium-ion rechargeable battery to
be used; therefore, please ask the battery provider to determine whether to enable or inhibit the 0
V battery charge.
2. The 0 V battery charge has higher priority than the charge overcurrent detection function.
Consequently, a product in which use of the 0 V battery charge is enabled charges a battery
forcibly and the charge overcurrent cannot be detected when the battery voltage is lower than VDL.

9. 0 V battery charge inhibited

This function inhibits charging when a battery that is internally short-circuited (0 V battery) is connected. When the battery
voltage is the 0 V battery charge inhibition battery voltage (V0INH) or lower, the charge control FET gate is fixed to the
EB− pin voltage to inhibit charging. When the battery voltage is V0INH or higher, charging can be performed.

Caution Some battery providers do not recommend charging for a completely self-discharged lithium-ion
rechargeable battery. It depends on the characteristics of the lithium-ion rechargeable battery to be
used; therefore, please ask the battery provider to determine whether to enable or inhibit the 0 V
battery charge.

10. Delay circuit

The detection delay times are determined by dividing a clock of approximately 4 kHz by the counter.

Remark tDIOV1, tDIOV2 and tSHORT start when VDIOV1 is detected. When VDIOV2 or VSHORT is detected over tDIOV2 or tSHORT
after the detection of VDIOV1, this IC turns the discharge control FET off within tDIOV2 or tSHORT of each detection.

VDD

DO pin voltage
tD 0 ≤ tD ≤ tSHORT
VSS

tSHORT Time
VDD

VSHORT
VINI pin voltage
VDIOV1

VSS
Time

Figure 10

28
 BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
Rev.2.3_00 S-82B2A/B Series

 Timing Charts
1. Overcharge detection, overdischarge detection

VCUn
VCLn (VCUn − VHCn)
Battery voltage
VDUn (VDLn + VHDn)
VDL

VDD
DO pin voltage

VSS

VDD
CO pin voltage

VSS
VEB−

VDD
VM pin voltage
0.35 V typ.
VSS
VEB−

VDD
VINI pin voltage
VDIOV1
VSS
VCIOV

Charger connection
Load connection
Overcharge detection delay time (tCU) Overdischarge detection delay time (tDL)

(1) (2) (1) (3) (1)

Status*1

*1. (1): Normal status

(2): Overcharge status
(3): Overdischarge status

Remark 1. The charger is assumed to charge with a constant current.

2. n = 1, 2

Figure 11

29
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-82B2A/B Series Rev.2.3_00

2. Discharge overcurrent detection

VCUn
VCLn (VCUn − VHCn)
Battery voltage
VDUn (VDLn + VHDn)
VDLn

VDD
DO pin voltage

VSS

VDD

CO pin voltage
VSS

VDD
VRIOV
VM pin voltage

VSS

VDD
VINI pin voltage
VSHORT
VDIOV2
VDIOV1
VSS

Load connection
Discharge overcurrent 1 Discharge overcurrent 2 Load short-circuiting
detection delay time (tDIOV1) detection delay time (tDIOV2) detection delay time (tSHORT)

(1) (2) (1) (2) (1) (2) (1)

Status*1

*1. (1): Normal status

(2): Discharge overcurrent status

Remark n = 1, 2

Figure 12

30
 BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
Rev.2.3_00 S-82B2A/B Series

3. Charge overcurrent detection

VCUn
VCLn (VCUn − VHCn)
Battery voltage
VDUn (VDLn + VHDn)
VDLn

VDD

DO pin voltage

VSS

VDD
CO pin voltage

VSS
VEB−

VDD
VM pin voltage
0.35 V typ.
VSS

VEB−

VDD
VINI pin voltage
VDIOV1
VSS
VCIOV

Charger connection
Load connection
Charge overcurrent Overdischarge Charge overcurrent
detection delay time (tCIOV) detection delay time (tDL) detection delay time (tCIOV)

(1) (2) (1) (3) (1) (2)

Status*1

*1. (1): Normal status

(2): Charge overcurrent status
(3): Overdischarge status

Remark 1. The charger is assumed to charge with a constant current.

2. n = 1, 2

Figure 13

31
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-82B2A/B Series Rev.2.3_00

4. Charge-discharge inhibition operation (S-82B2A Series)

VCUn
VCLn (VCUn − VHCn)
Battery voltage
VDUn (VDLn + VHDn)
VDLn

VDD
DO pin voltage

VSS

VDD
CO pin voltage

VSS
VEB−

VDD
VM pin voltage
VDIOV1
VSS
VCIOV
VEB−

VDD
VCTLH
CTL pin voltage
(Active "H")
VCTLL
VSS

VDD
VCTLH
CTL pin voltage
(Active "L")
VCTLL
VSS

Charger connection
Load connection
Charge-discharge Overdischarge detection Charge-discharge
inhibition delay time (tCTL) delay time (tDL) inhibition delay time (tCTL)

(1) (2) (1) (3) (1) (2)

Status*1

*1. (1): Normal status

(2): Charge-discharge inhibition status
(3): Overdischarge status

Remark 1. The charger is assumed to charge with a constant current.

2. n = 1, 2

Figure 14
32
 BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
Rev.2.3_00 S-82B2A/B Series

5. Power-saving operation (S-82B2B Series)

VCUn
VCLn (VCUn − VHCn)
Battery voltage
VDUn (VDLn + VHDn)
VDLn

VDD
DO pin voltage

VSS

VDD
CO pin voltage

VSS
VEB−

VDD
VM pin voltage
VDIOV1
VSS
VCIOV
VEB−

VDD
VPSH
PS pin voltage
(Active "H")
VPSL
VSS

VDD
VPSH
PS pin voltage
(Active "L")
VPSL
VSS

Charger connection
Load connection
Overdischarge detection
Power-saving delay time (tPS) delay time (tDL) Power-saving delay time (tPS)

(1) (2) (1) (3) (1) (2)

Status*1

*1. (1): Normal status

(2): Power-saving status
(3): Overdischarge status

Remark 1. The charger is assumed to charge with a constant current.

2. n = 1, 2

Figure 15
33
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-82B2A/B Series Rev.2.3_00

 Battery Protection IC Connection Example

EB+
R1
VDD R5
C1 CTL / PS External Input
BAT1
R2
VC

BAT2 C2

VSS

VINI DO CO VM

R3
R4 FET1 FET2
EB−

Figure 16

Table 16 Constants for External Components

Symbol Part Purpose Min. Typ. Max. Remark

N-channel Threshold voltage ≤ Overdischarge
FET1 Discharge control − − −
MOS FET detection voltage*1
N-channel Threshold voltage ≤ Overdischarge
FET2 Charge control − − −
MOS FET detection voltage*1
ESD protection,
R1, R2 Resistor 100 Ω 100 Ω 150 Ω*2 −
For power fluctuation
C1, C2 Capacitor For power fluctuation 0.068 μF 0.1 μF 1.0 μF −
ESD protection,
R3 Resistor Protection for reverse 300 Ω 1.0 kΩ 1.5 kΩ −
connection of a charger
R4 Resistor Overcurrent detection − 1 mΩ − −
R5 Resistor CTL / PS pin input protection − 1 kΩ − −

*1. If a FET with a threshold voltage equal to or higher than the overdischarge detection voltage is used, discharging may
be stopped before overdischarge is detected.
*2. Accuracy of overcharge detection voltage is guaranteed by R1 = 100 Ω. Connecting resistors with other values will
worsen the accuracy.

Caution 1. The constants may be changed without notice.

2. It has not been confirmed whether the operation is normal or not in circuits other than the connection
example. In addition, the connection example and the constants do not guarantee proper operation.
Perform thorough evaluation using the actual application to set the constants.

34
 BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
Rev.2.3_00 S-82B2A/B Series

 Precautions
• The application status s for the input voltage, output voltage, and load current should not exceed the power dissipation.

• Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.

• ABLIC Inc. claims no responsibility for any and all disputes arising out of or in connection with any infringement by
products including this IC of patents owned by a third party.

35
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-82B2A/B Series Rev.2.3_00

 Characteristics (Typical Data)

1. Current consumption
1. 1 IOPE vs. Ta 1. 2 IVC vs. Ta
8 0.10

6 0.05
IOPE [µA]

IVC [µA]
4 0.00

2 -0.05

0 -0.10
-40 -25 0 25 50 75 85 -40 -25 0 25 50 75 85
Ta [°C] Ta [°C]

1. 3 IPDN vs. Ta 1. 4 IOPED vs. Ta

100 1.2

75 IOPED [µA] 0.9

IPDN [nA]

50 0.6

25 0.3

0 0
-40 -25 0 25 50 75 85 -40 -25 0 25 50 75 85
Ta [°C] Ta [°C]

1. 5 IOPE vs. VDD

1. 5. 1 With power-down function 1. 5. 2 Without power-down function
8 8

6 6
IOPE [µA]

IOPE [µA]

4 4

2 2

0 0
0 2 4 6 8 10 0 2 4 6 8 10
VDD [V] VDD [V]

1. 6 IPS vs. Ta (S-82B2B Series) 1. 7 IPS vs. VDD (S-82B2B Series)

100 100

75 75
IPS [nA]

IPS [nA]

50 50

25 25

0 0
-40 -25 0 25 50 75 85 4.8 5.8 6.8 7.8 8.8
Ta [°C] VDD [V]

36
 BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
Rev.2.3_00 S-82B2A/B Series

2. Detection voltage, release voltage

2. 1 VCUn vs. Ta 2. 2 VCLn vs. Ta
4.27 4.16

4.25 4.12
VCUn [V]

VCLn [V]
4.23 4.08

4.21 4.04

4.19 4.00
-40 -25 0 25 50 75 85 -40 -25 0 25 50 75 85
Ta [°C] Ta [°C]

2. 3 VDLn vs. Ta 2. 4 VDUn vs. Ta

2.78 2.98

2.74 2.94
VDUn [V]
VDLn [V]

2.70 2.90

2.66 2.86

2.62 2.82
-40 -25 0 25 50 75 85 -40 -25 0 25 50 75 85
Ta [°C] Ta [°C]

2. 5 VDIOV1 vs. VDD 2. 6 VDIOV1 vs. Ta

27 27

26 26
VDIOV1 [mV]

VDIOV1 [mV]

25 25

24 24

23 23
4.8 5.8 6.8 7.8 8.8 -40 -25 0 25 50 75 85
VDD [V] Ta [°C]

2. 7 VDIOV2 vs. VDD 2. 8 VDIOV2 vs. Ta

54 54

52 52
VDIOV2 [mV]

VDIOV2 [mV]

50 50

48 48

46 46
4.8 5.8 6.8 7.8 8.8 -40 -25 0 25 50 75 85
VDD [V] Ta [°C]

Remark n = 1, 2

37
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-82B2A/B Series Rev.2.3_00

2. 9 VSHORT vs. VDD 2. 10 VSHORT vs. Ta

106 106

103 103
VSHORT [mV]

VSHORT [mV]
100 100

97 97

94 94
4.8 5.8 6.8 7.8 8.8 -40 -25 0 25 50 75 85
VDD [V] Ta [°C]

2. 11 VCIOV vs. VDD 2. 12 VCIOV vs. Ta

-13 -13

-14 -14
VCIOV [mV]

VCIOV [mV]
-15 -15

-16 -16

-17 -17
4.8 5.8 6.8 7.8 8.8 -40 -25 0 25 50 75 85
VDD [V] Ta [°C]

38
 BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
Rev.2.3_00 S-82B2A/B Series

3. Delay time
3. 1 tCU vs. Ta 3. 2 tDL vs. Ta
2.0 240

1.5 180

tDL [ms]
tCU [s]

1.0 120

0.5 60

0 0
-40 -25 0 25 50 75 85 -40 -25 0 25 50 75 85
Ta [°C] Ta [°C]

3. 3 tDIOV1 vs. VDD 3. 4 tDIOV1 vs. Ta

1024 1024

768 768
tDIOV1 [ms]

tDIOV1 [ms]
512 512

256 256

0 0
4.8 5.8 6.8 7.8 8.8 -40 -25 0 25 50 75 85
VDD [V] VDD [V]

3. 5 tDIOV2 vs. VDD 3. 6 tDIOV2 vs. Ta

32 32

24 24
tDIOV2 [ms]

tDIOV2 [ms]

16 16

8 8

0 0
4.8 5.8 6.8 7.8 8.8 -40 -25 0 25 50 75 85
VDD [V] VDD [V]

3. 7 tSHORT vs. VDD 3. 8 tSHORT vs. Ta

560 560

420 420
tSHORT [µs]

tSHORT [µs]

280 280

140 140

0 0
4.8 5.8 6.8 7.8 8.8 -40 -25 0 25 50 75 85
VDD [V] Ta [°C]

39
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-82B2A/B Series Rev.2.3_00

3. 9 tCIOV vs. VDD 3. 10 tCIOV vs. Ta

16 16

12 12
tCIOV [ms]

tCIOV [ms]
8 8

4 4

0 0
4.8 5.8 6.8 7.8 8.8 -40 -25 0 25 50 75 85
VDD [V] Ta [°C]

3. 11 tCTL vs. VDD (S-82B2A Series) 3. 12 tCTL vs. Ta (S-82B2A Series)

96 96

72 72
tCTL [ms]

tCTL [ms]
48 48

24 24

0 0
4.8 5.8 6.8 7.8 8.8 -40 -25 0 25 50 75 85
VDD [V] Ta [°C]

3. 13 tPS vs. VDD (S-82B2B Series) 3. 14 tPS vs. Ta (S-82B2B Series)

4 4

3 3
tPS [ms]

tPS [ms]

2 2

1 1

0 0
4.8 5.8 6.8 7.8 8.8 -40 -25 0 25 50 75 85
VDD [V] Ta [°C]

40
 BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
Rev.2.3_00 S-82B2A/B Series

4. Output resistance
4. 1 RCOH vs. VCO 4. 2 RCOL vs. VCO
20 10.0

15 7.5
RCOH [kΩ]

RCOL [kΩ]
10 5.0

5 2.5

0 0
0 3 6 9 12 0 3 6 9 12
VCO [V] VCO [V]

4. 3 RDOH vs. VDO 4. 4 RDOL vs. VDO

32 6.0

24 4.5
RDOH [kΩ]

RDOL [kΩ]
16 3.0

8 1.5

0 0
0 3 6 9 12 0 3 6 9 12
VDO [V] VDO [V]

41
BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
S-82B2A/B Series Rev.2.3_00

 Marking Specifications
1. SNT-8A
Top view
8 7 6 5 (1): Blank
(2) to (4): Product code (Refer to Product name vs. Product code)
(5), (6): Blank
(1) (2) (3) (4) (7) to (11): Lot number
(5) (6) (7) (8)

(9) (10) (11)

1 2 3 4

Product name vs. Product code

1. 1 S-82B2A Series 1. 2 S-82B2B Series

Product Code Product Code
Product Name Product Name
(2) (3) (4) (2) (3) (4)
S-82B2AAA-I8T1U7 9 D E S-82B2BAA-I8T1U7 9 D I

2. HSNT-8(1616)
Top view
8 7 6 5 (1): Blank
(2) to (4): Product code (Refer to Product name vs. Product code)
(5) to (7): Lot number

(1) (2) (3) (4)

(5) (6) (7)

1 2 3 4

Product name vs. Product code

2. 1 S-82B2A Series 2. 2 S-82B2B Series

Product Code Product Code
Product Name Product Name
(2) (3) (4) (2) (3) (4)
S-82B2AAA-A8T2U7 9 D E S-82B2BAA-A8T2U7 9 D I
S-82B2AAB-A8T2U7 9 D L

42
 BATTERY PROTECTION IC FOR 2-SERIAL-CELL PACK
Rev.2.3_00 S-82B2A/B Series

 Power Dissipation
SNT-8A HSNT-8(1616)

Tj = +125°C max. Tj = +125°C max.

1.0 1.0
Power dissipation (PD) [W]

Power dissipation (PD) [W]

0.8 0.8

B B
0.6 0.6
A

0.4 0.4 A

0.2 0.2

0.0 0.0
0 25 50 75 100 125 150 175 0 25 50 75 100 125 150 175
Ambient temperature (Ta) [°C] Ambient temperature (Ta) [°C]

Board Power Dissipation (PD) Board Power Dissipation (PD)

A 0.47 W A 0.47 W
B 0.58 W B 0.58 W
C − C −
D − D −
E − E −

43
 SNT-8A Test Board

(1) Board A IC Mount Area

Item Specification
Size [mm] 114.3 x 76.2 x t1.6
Material FR-4
Number of copper foil layer 2
1 Land pattern and wiring for testing: t0.070
2 -
Copper foil layer [mm]
3 -
4 74.2 x 74.2 x t0.070
Thermal via -

(2) Board B

Item Specification
Size [mm] 114.3 x 76.2 x t1.6
Material FR-4
Number of copper foil layer 4
1 Land pattern and wiring for testing: t0.070
2 74.2 x 74.2 x t0.035
Copper foil layer [mm]
3 74.2 x 74.2 x t0.035
4 74.2 x 74.2 x t0.070
Thermal via -

No. SNT8A-A-Board-SD-1.0

ABLIC Inc.
 HSNT-8(1616) Test Board

IC Mount Area
(1) Board A

Item Specification
Size [mm] 114.3 x 76.2 x t1.6
Material FR-4
Number of copper foil layer 2
1 Land pattern and wiring for testing: t0.070
2 -
Copper foil layer [mm]
3 -
4 74.2 x 74.2 x t0.070
Thermal via -

(2) Board B

Item Specification
Size [mm] 114.3 x 76.2 x t1.6
Material FR-4
Number of copper foil layer 4
1 Land pattern and wiring for testing: t0.070
2 74.2 x 74.2 x t0.035
Copper foil layer [mm]
3 74.2 x 74.2 x t0.035
4 74.2 x 74.2 x t0.070
Thermal via -

No. HSNT8-B-Board-SD-1.0

ABLIC Inc.
 1.97±0.03

8 7 6 5

+0.05
0.08 -0.02
1 2 3 4
0.5

0.48±0.02

0.2±0.05

No. PH008-A-P-SD-2.1

TITLE SNT-8A-A-PKG Dimensions

No. PH008-A-P-SD-2.1
ANGLE
UNIT mm

ABLIC Inc.
 +0.1
ø1.5 2.0±0.05 4.0±0.1 0.25±0.05
-0

ø0.5±0.1 0.65±0.05
2.25±0.05 4.0±0.1

4321

5 6 78

Feed direction

No. PH008-A-C-SD-2.0

TITLE SNT-8A-A-Carrier Tape

No. PH008-A-C-SD-2.0
ANGLE
UNIT mm

ABLIC Inc.
 +1.0
9.0 - 0.0

11.4±1.0

Enlarged drawing in the central part

ø13±0.2

(60°) (60°)

No. PH008-A-R-SD-2.0

TITLE SNT-8A-A-Reel

No. PH008-A-R-SD-2.0
ANGLE QTY. 5,000
UNIT mm

ABLIC Inc.
 0.52

2
2.01

0.52

0.2 0.3 1

1. (0.25 mm min. / 0.30 mm typ.)

2. (1.96 mm ~ 2.06 mm)
1.
2. 0.03 mm

3.
4. SNT

1. Pay attention to the land pattern width (0.25 mm min. / 0.30 mm typ.).
2. Do not widen the land pattern to the center of the package (1.96 mm to 2.06mm).
Caution 1. Do not do silkscreen printing and solder printing under the mold resin of the package.
2. The thickness of the solder resist on the wire pattern under the package should be 0.03 mm
or less from the land pattern surface.
3. Match the mask aperture size and aperture position with the land pattern.
4. Refer to "SNT Package User's Guide" for details.

1. (0.25 mm min. / 0.30 mm typ.)

2. (1.96 mm ~ 2.06 mm)

SNT-8A-A
TITLE
-Land Recommendation
No. PH008-A-L-SD-4.1 No. PH008-A-L-SD-4.1
ANGLE
UNIT mm

ABLIC Inc.
1.60±0.1 0.38±0.02

(1.40)

0.1±0.04 0.4

0.2±0.05 The heat sink of back side has different electric

potential depending on the product.
Confirm specifications of each product.
Do not use it as the function of electrode.

No. PY008-A-P-SD-1.0

TITLE HSNT-8-B-PKG Dimensions

No. PY008-A-P-SD-1.0
ANGLE
UNIT mm

ABLIC Inc.
 +0.1 2.0±0.05 4.0±0.1
ø1.5 -0 0.20±0.05

ø0.35 4.0±0.1
0.55
1.80

4 1

5 8

Feed direction

No. PY008-A-C-SD-1.0

TITLE HSNT-8-B-Carrier Tape

No. PY008-A-C-SD-1.0
ANGLE
UNIT mm

ABLIC Inc.
 +1.0
9.0 - 0.0
11.4±1.0

Enlarged drawing in the central part

ø13±0.2

(60°) (60°)

No. PY008-A-R-SD-1.0

TITLE HSNT-8-B-Reel
No. PY008-A-R-SD-1.0
ANGLE QTY. 5,000
UNIT mm

ABLIC Inc.
Land Pattern 0.40

1.30

0.25

Caution It is recommended to solder the heat sink to a board

in order to ensure the heat radiation.
PKG

0.40
Metal Mask Pattern

0.82

0.25

Caution Mask aperture ratio of the lead mounting part is 100%.

Mask aperture ratio of the heat sink mounting part is 40%.
Mask thickness: t0.12 mm

100%
40% HSNT-8-B
TITLE -Land Recommendation
t0.12 mm
No. PY008-A-L-SD-1.0
ANGLE
UNIT mm

No. PY008-A-L-SD-1.0

ABLIC Inc.
 Disclaimers (Handling Precautions)
1. All the information described herein (product data, specifications, figures, tables, programs, algorithms and
application circuit examples, etc.) is current as of publishing date of this document and is subject to change without
notice.
2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of
any specific mass-production design.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products
described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other
right due to the use of the information described herein.
3. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described
herein.
4. Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute
maximum ratings, operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to
the use of the products outside their specified ranges.
5. Before using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.
6. When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related
laws, and follow the required procedures.
7. The products are strictly prohibited from using, providing or exporting for the purposes of the development of
weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands
caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear,
biological or chemical weapons or missiles, or use any other military purposes.
8. The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by
ABLIC, Inc. Do not apply the products to the above listed devices and equipments.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of
the products.
9. In general, semiconductor products may fail or malfunction with some probability. The user of the products should
therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread
prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social
damage, etc. that may ensue from the products' failure or malfunction.
The entire system in which the products are used must be sufficiently evaluated and judged whether the products are
allowed to apply for the system on customer's own responsibility.
10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
13. The information described herein contains copyright information and know-how of ABLIC Inc. The information
described herein does not convey any license under any intellectual property rights or any other rights belonging to
ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this
document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express
permission of ABLIC Inc.
14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales
representative.
15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into
the English language and the Chinese language, shall be controlling.

2.4-2019.07

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