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Computer Arithmetic
and Verilog HDL
Fundamentals
Joseph Cavanagh
Santa Clara University
California, USA
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Preface ................................................................................................. xv
The purpose of this book is to present computer arithmetic for fixed-point, decimal,
and floating-point number representations for the operations of addition, subtraction,
multiplication, and division, and to implement those operations using the Verilog
Hardware Description Language (HDL). The Verilog HDL language provides a
means to model a digital system at many levels of abstraction.
The four basic operations are implemented in the execution unit of a computer
which includes the arithmetic and logic unit (ALU). The execution unit is the focal
point of the computer and performs all of the arithmetic and logical operations.
Addition and subtraction for all three number representations are relatively sim-
ple; however, multiplication and division are comparatively more complex. The
arithmetic algorithms for the three number representations are presented in sufficient
detail to permit ease of understanding.
The different modeling constructs supported by Verilog are described in detail.
Numerous examples are designed in each chapter for specific operations using the
appropriate number representation, including both combinational and clocked
sequential arithmetic circuits. Emphasis is placed on the detailed theory and design
of various arithmetic circuits using applicable algorithms. The Verilog HDL design
projects include the design module implemented using built-in primitives, dataflow
modeling, behavioral modeling or structural modeling, the test bench module, the
outputs obtained from the simulator, and the waveforms obtained from the simulator
that illustrate the complete functional operation of the design.
The book is intended to be tutorial, and as such, is comprehensive and self con-
tained. All designs are carried through to completion — nothing is left unfinished or
partially designed. Each chapter includes numerous problems of varying complexity
to be designed by the reader.
Chapter 1 covers the number systems of different radices, such as binary, octal,
binary-coded octal, decimal, binary-coded decimal, hexadecimal, and binary-coded
hexadecimal. The chapter also presents the number representations of sign magni-
tude, diminished-radix complement, and radix complement.
Chapter 2 presents a review of logic design fundamentals, including Boolean
algebra and minimization techniques for switching functions. The minimization
techniques include algebraic minimization using Boolean algebra, Karnaugh maps,
map-entered variables, the Quine-McCluskey algorithm, and the Petrick algorithm.
Various combinational logic macro functions are also presented. These include mul-
tiplexers of different sizes and types, such as linear-select multiplexers and nonlin-
ear-select multiplexers. The chapter also shows a one-to-one correspondence
between the data input numbers di of a multiplexer and the minterm locations in a
xv
Karnaugh map. Decoders and encoders are presented together with comparators.
Sequential logic includes SR latches, D flip-flops, and JK flip-flops. Counters of dif-
ferent moduli are designed for both count-up and count-down counters. The com-
plete design process for Moore and Mealy synchronous sequential machines is
presented.
Chapter 3 introduces Verilog HDL, which will be used throughout the book to de-
sign the arithmetic circuits. Verilog HDL is the state-of-the-art method for designing
digital and computer systems and is ideally suited to describe both combinational and
clocked sequential arithmetic circuits. Verilog provides a clear relationship between
the language syntax and the physical hardware. The Verilog simulator used in this
book is easy to learn and use, yet powerful enough for any application. It is a logic
simulator — called SILOS — developed by Silvaco International for use in the design
and verification of digital systems. The SILOS simulation environment is a method to
quickly prototype and debug any logic function. It is an intuitive environment that dis-
plays every variable and port from a module to a logic gate. SILOS allows single-step-
ping through the Verilog source code, as well as drag-and-drop ability from the source
code to a data analyzer for waveform generation and analysis. This chapter introduces
the reader to the different modeling techniques, including built-in primitives for logic
primitive gates and user-defined primitives for larger logic functions. The three main
modeling methods of dataflow modeling, behavioral modeling, and structural model-
ing are introduced.
Chapter 4 presents fixed-point addition. The different categories of addition cir-
cuits are: ripple-carry addition, carry lookahead addition, carry-save addition, mem-
ory-based addition, carry-select addition, and serial addition. A ripple-carry adder is
not considered a high-speed adder, but requires less logic than a high-speed adder
using the carry lookahead technique. Using the carry lookahead method, a consider-
able increase in speed can be realized by expressing the carry-out couti of any stage i as
a function of the two operand bits ai and bi and the carry-in cin–1 to the low-order
stage0 of the adder. Carry-save adders (CSAs) save the carry from propagating to the
next higher-order stage in an n-bit adder. They can be used to add multiple bits of the
same weight from multiple operands or to add multiple n-bit operands. With the
advent of high-density, high-speed memories, addition can be easily accomplished by
applying the augend and addend as address inputs to the memory — the outputs are the
sum. A carry-select adder is not as fast as the carry lookahead adder, however it has a
unique organization that is interesting. The carry-select principle produces two sums
that are generated simultaneously. One sum assumes that the carry-in to that group
was a 0; the other sum assumes that the carry-in was a 1. The predicted carry is
obtained using the carry lookahead technique which selects one of the two sums. If a
minimal amount of hardware is a prerequisite and speed is not essential, then a serial
adder may be utilized. A serial adder adds the augend and addend one bit per clock
pulse — thus, eight clock pulses are required to add two bytes of data.
Chapter 5 presents fixed-point subtraction, which like addition, is relatively sim-
ple. It also shares much of the same circuitry as addition. The two operands for sub-
traction are the minuend and the subtrahend — the subtrahend is subtracted from the
minuend. Computers use an adder for the subtraction operation by adding the radix
complement of the subtrahend to the minuend. A 2s complementer is used that
produces either the uncomplemented version of the addend for addition or the 2s com-
plement version of the subtrahend for subtraction. Subtraction can be performed in all
three number representations: sign magnitude, diminished-radix complement, and
radix complement; however, radix complement is the easiest and most widely used
method for subtraction in any radix.
Chapter 6 presents several methods for fixed-point multiplication. The multipli-
cand is multiplied by the multiplier to generate the product. In all methods the product
is usually 2n bits in length. The sequential add-shift method is a common approach for
low-speed multiplication, but usually requires that the multiplier be positive. The
Booth algorithm is an effective technique for multiplying operands that are in 2s com-
plement representation, including the case where the multiplier is negative. Unlike the
sequential add-shift method, it treats both positive and negative operands uniformly;
that is, the multiplicand and multiplier can both be negative or positive. Another
method is bit-pair recoding that represents a speedup technique that is derived from the
Booth algorithm and assures that an n-bit multiplier will have no more than n/2 partial
products. It also treats both positive and negative multipliers uniformly; that is, there
is no need to 2s complement the multiplier before multiplying, or to 2s complement
the product after multiplying. A table lookup multiplier permits a multiply operation
for unsigned operands and positive signed operands. For signed operands, the multi-
plier must be positive — the multiplicand can be positive or negative. Multiplication
can be accomplished by using a table that contains different versions of the multipli-
cand to be added to the partial products. Firmware loads the multiplicand table in
memory and the multiplier prior to the multiply operation. With the advent of high-
capacity, high-speed random-access memories (RAMs), multiplication using RAM
may be a viable option. The multiplicand and multiplier are used as address inputs to
the memory — the outputs are the product. The operands can be either unsigned or
signed numbers in 2s complement representation. Multiple-operand multiplication is
also presented.
Chapter 7 covers several methods of fixed-point division, including the sequential
shift-add/subtract restoring division method in which the partial remainder is restored
to its previous value if it is negative. The speed of the division algorithm can be
increased by modifying the algorithm to avoid restoring the partial remainder in the
event that a negative partial remainder occurs. This method allows both a positive par-
tial remainder and a negative partial remainder to be utilized in the division process. In
nonrestoring division, a negative partial remainder is not restored to the previous value
but is used unchanged in the following cycle. SRT division was developed indepen-
dently by Sweeney, Robertson, and Tocher as a way to increase the speed of a divide
operation. It was intended to improve radix-2 floating-point arithmetic by shifting
over strings of 0s or 1s in much the same way as the Booth algorithm shifts over strings
of 0s in a multiply operation. SRT division is designed in this chapter using a table
lookup approach and using the case statement, which is a multiple-way conditional
branch. Convergence division is also covered in which a multiplier is used in the
division process; thus, the method is referred to as multiplicative division. A combi-
national array can be used for division in much the same way as an array was used for
multiplication. This is an extremely fast division operation, because the array is
entirely combinational — the only delay is the propagation delay through the gates.
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