CSC 553 Operating Systems

Lecture 1- Computer System

Overview

Operating System
• Exploits the hardware resources of one or
more processors
• Provides a set of services to system users
• Manages secondary memory and I/O
devices
 Basic Elements

I/O
Processor Modules

Main System
Memory Bus

Processor

Controls the Performs the data

operation of the processing
computer functions

Referred to as the
Central
Processing Unit
(CPU)
 Main Memory
• Stores data and programs
• Typically volatile
– Contents of the memory is lost when the
computer is shut down
• Referred to as real memory or primary
memory

I/O Modules
Secondary
memory devices
(e.g. disks)
Move data
between the
Communications
computer and its equipment
external
environment
Terminals
 System Bus

• Provides for communication

among processors, main memory,
and I/O modules

CPU Main Memory

0
System 1
2
PC MAR Bus
Instruction
Instruction
Instruction
IR MBR

I/O AR
Data
Execution
unit Data
I/O BR Data
Data

I/O Module n-2

n-1

PC = Program counter
Buffers IR = Instruction register
MAR = Memory address register
MBR = Memory buffer register
I/O AR = Input/output address register
I/O BR = Input/output buffer register

Figure 1.1 Computer Components: Top-Level View

 Microprocessor
– Invention that brought about desktop and
handheld computing
– Contains a processor on a single chip
– Fastest general purpose processors
– Multiprocessors
– Each chip (socket) contains multiple
processors (cores)

Graphical Processing
Units (GPU’s)
– Provide efficient computation on arrays of data
using Single-Instruction Multiple Data (SIMD)
techniques pioneered in supercomputers
– No longer used just for rendering advanced
graphics
• Also used for general numerical processing
» Physics simulations for games
» Computations on large spreadsheets
 Digital Signal Processors (DSPs)
– Deal with streaming signals such as audio or
video
– Used to be embedded in I/O devices like
modems
–Are now becoming first-class
computational devices, especially in
handhelds
– Encoding/decoding speech and video
(codecs)
– Provide support for encryption and security

System on a Chip (SoC)

• To satisfy the requirements of handheld
devices, the classic microprocessor is
giving way to the SoC
• Other components of the system, such as
DSPs, GPUs, I/O devices (such as codecs
and radios) and main memory, in addition to
the CPUs and caches, are on the same chip
 Instruction Execution
• A program consists of a set of instructions
stored in memory

Processor reads
Processor executes
(fetches) instructions
each instruction
from memory

Two steps

Fetch Stage Execute Stage

Fetch Next Execute

START HALT
Instruction Instruction

Figure 1.2 Basic Instruction Cycle

• The processor fetches an instruction from
memory
• Typically the program counter (PC) holds
the address of the next instruction to be
fetched

PC is incremented after each fetch

Instruction Register (IR)

• Processor interprets the

Fetched instruction is instruction and performs
loaded into Instruction required action:
Register (IR)
– Processor-memory
– Processor-I/O
– Data processing
– Control
 Fetch Stage Execute Stage
Memory CPU Registers Memory CPU Registers
300 1 9 4 0 3 0 0 PC 300 1 9 4 0 3 0 1 PC
301 5 9 4 1 AC 301 5 9 4 1 0 0 0 3 AC
302 2 9 4 1 1 9 4 0 IR 302 2 9 4 1 1 9 4 0 IR
• •
• •
940 0 0 0 3 940 0 0 0 3
941 0 0 0 2 941 0 0 0 2
Step 1 Step 2
Memory CPU Registers Memory CPU Registers
300 1 9 4 0 3 0 1 PC 300 1 9 4 0 3 0 2 PC
301 5 9 4 1 0 0 0 3 AC 301 5 9 4 1 0 0 0 5 AC
302 2 9 4 1 5 9 4 1 IR 302 2 9 4 1 5 9 4 1 IR
• •
• •
940 0 0 0 3 940 0 0 0 3 3+2=5
941 0 0 0 2 941 0 0 0 2
Step 3 Step 4
Memory CPU Registers Memory CPU Registers
300 1 9 4 0 3 0 2 PC 300 1 9 4 0 3 0 3 PC
301 5 9 4 1 0 0 0 5 AC 301 5 9 4 1 0 0 0 5 AC
302 2 9 4 1 2 9 4 1 IR 302 2 9 4 1 2 9 4 1 IR
• •
• •
940 0 0 0 3 940 0 0 0 3
941 0 0 0 2 941 0 0 0 5
Step 5 Step 6

Figure 1.4 Example of Program Execution

(contents of memory and registers in hexadecimal)
 Interrupts
• Mechanism by which other modules may
interrupt the normal sequencing of the
processor
• Provided to improve processor utilization
• Most I/O devices are slower than the processor
• Processor must pause to wait for device
• Wasteful use of the processor
 User I/O
Program Program

1 4

I/O
Command
WRITE

Flow of 5

END
Control 2

Without WRITE

Interrupts
3

WRITE

(a) No interrupts

User I/O
Program Program

1 4

I/O
Command
WRITE

2a

Interrupt
Short I/O Wait 2b Handler

WRITE 5

END
3a

3b

WRITE

(b) Interrupts; short I/O wait

 User I/O
Program Program

1 4

I/O
Command
WRITE

Long I/O Wait 2

Interrupt
Handler

WRITE 5

END

WRITE

(c) Interrupts; long I/O wait

User Program Interrupt Handler

i
Interrupt
occurs here i+1

Figure 1.6 Transfer of Control via Interrupts

 Fetch Stage Execute Stage Interrupt Stage

Interrupts
Disabled
Check for
Fetch next Execute interrupt;
START instruction instruction initiate interrupt
Interrupts
handler
Enabled

HALT

Figure 1.7 Instruction Cycle with Interrupts

Time

1 1

4 4
I/O operation
I/O operation;
processor waits 2a concurrent with
processor executing

5 5

2b
2
4
I/O operation
4 3a concurrent with
processor executing
I/O operation;
processor waits 5

5 3b

(b) With interrupts

3

(a) Without interrupts

Figure 1.8 Program Timing: Short I/O Wait

Time
1 1

4 4

I/O operation; 2 I/O operation

processor waits concurrent with
processor executing;
then processor
waits
5

5
2
4
4
3 I/O operation
concurrent with
I/O operation; processor executing;
processor waits then processor
waits

5
5

3 (b) With interrupts

(a) Without interrupts

Figure 1.9 Program Timing: Long I/O Wait

Hardware Software

Device controller or
other system hardware
issues an interrupt
Save remainder of
process state
information
Processor finishes
execution of current
instruction

Process interrupt
Processor signals
acknowledgment
of interrupt
Restore process state
information
Processor pushes PSW
and PC onto control
stack
Restore old PSW
and PC
Processor loads new
PC value based on
interrupt

Figure 1.10 Simple Interrupt Processing

 T–M T–M
Y N+1
Control Control
Stack Stack
T T
N+1 Y+L+1
Program Program
Counter Counter

Y Start Y Start
Interrupt General Interrupt General
Service Registers Service Registers
Y + L Return Routine T Y + L Return Routine T–M
Stack Stack
Pointer Pointer

Processor Processor

T–M T

N User's N User's
N+1 N+1
Program Program

Main Main
Memory Memory

(a) Interrupt occurs after instruction

(b) Return from interrupt
at location N

Figure 1.11 Changes in Memory and Registers for an Interrupt

Multiple Interrupts

An interrupt occurs
while another interrupt Two approaches:
is being processed
• e.g. receiving data • Disable interrupts
from a while an interrupt is
communications line being processed
and printing results at • Use a priority scheme
the same time
 Interrupt
User Program Handler X

Interrupt
Handler Y

(a) Sequential interrupt processing

Interrupt
User Program Handler X

Interrupt
Handler Y

(b) Nested interrupt processing

Figure 1.12 Transfer of Control with Multiple Interrupts

Printer Communication
User Program
interrupt service routine interrupt service routine
t=0

15
10 t=
t=

t = 25

t= t = 25 Disk
40 interrupt service routine

t=
35

Figure 1.13 Example Time Sequence of Multiple Interrupts

 Memory Hierarchy
• Design constraints on a computer’s memory

How much?

How fast?

How expensive?
• If the capacity is there, applications will likely be
developed to use it
• Memory must be able to keep up with the
processor
• Cost of memory must be reasonable in
relationship to the other components

Memory Relationships

Greater capacity =
Faster access smaller cost per
time = bit
greater cost Greater capacity
per bit = slower access
speed
 The Memory Hierarchy

Going down the g-
Re rs
ist
e

hierarchy: I nb
Me oard
mo
ry
Ca
ch
e

in
Ma ory
m
Me

Decreasing cost per bit Ou

t eti
cD
isk
Sto boar gn OM
rag d Ma D-R W
C D-R W
Increasing capacity e C
D-
R
DV D-RA y
DV lu-R
M
a
B

Increasing access time Of pe

f Ta
Sto -line e tic
Decreasing frequency rag
e Ma
gn

of access to the
memory by the
processor
Figure 1.14 The Memory Hierarchy

T1 + T2

T2
Average access time

T1

0 1
Fraction of accesses involving only Level 1 (Hit ratio)

Figure 1.15 Performance of a Simple Two-Level Memory

• Memory references by the processor tend to
cluster
• Data is organized so that the percentage of
accesses to each successively lower level is
substantially less than that of the level
above
• Can be applied across more than two levels
of memory

Secondary
Memory

Also
referred to
as auxiliary
memory
• External
• Nonvolatile
• Used to store
program and
data files
• Invisible to the OS
• Interacts with other memory management
hardware
• Processor must access memory at least once per
instruction cycle
• Processor execution is limited by memory cycle
time
• Exploit the principle of locality with a small, fast
memory

Block Transfer
Word Transfer

CPU Cache Main Memory

Fast Slow

(a) Single cache

Level 1 Level 2 Level 3 Main

CPU
(L1) cache (L2) cache (L3) cache Memory

Fastest Fast
Less Slow
fast

(b) Three-level cache organization

Figure 1.16 Cache and Main Memory

Line Memory
Number Tag Block address
0 0
1 1
2 2 Block 0
3 (K words)

C-1
Block Length
(K Words)

(a) Cache

Block M – 1

2n - 1
Word
Length
(b) Main memory

Figure 1.17 Cache/Main-Memory Structure

START

RA - read address
Receive address
RA from CPU

Is block No Access main

containing RA memory for block
in cache? containing RA
Yes

Fetch RA word Allocate cache

and deliver slot for main
to CPU memory block

Load main
Deliver RA word
memory block
to CPU
into cache slot

DONE

Figure 1.18 Cache Read Operation

 Cache size

Number of
cache Block size
levels

Main
categories
are:

Write Mapping
policy function

Replacement
algorithm

Cache and Block Size

Cache Size
Block
Size
The unit of data
Small caches have
exchanged
significant impact
between cache
on performance
and main memory
 Mapping Function

Determines which cache

location the block will occupy
When one block is read in,
another may have to be
replaced
Two constraints affect
design:
The more flexible the
mapping function, the more
complex is the circuitry
required to search the cache

Replacement Algorithm

Least Recently Used (LRU) Algorithm
– Effective strategy is to replace a block that has
been in the cache the longest with no
references to it
– Hardware mechanisms are needed to identify
the least recently used block
• Chooses which block to replace when a new block is
to be loaded into the cache
 Write Policy
Dictates when the memory write operation takes
place

• Can occur every time the block is updated

• Can occur when the block is replaced
• Minimizes write operations
• Leaves main memory in an obsolete state

I/O Techniques
• When the processor encounters an
instruction relating to I/O, it executes that
instruction by issuing a command to the
appropriate I/O module
Three techniques are possible for I/O operations:

Programmed Interrupt- Direct Memory

I/O Driven I/O Access (DMA)
 Programmed I/O

• The I/O module performs the requested

action then sets the appropriate bits in the
I/O status register
• The processor periodically checks the status
of the I/O module until it determines the
instruction is complete
• With programmed I/O the performance
level of the entire system is severely
degraded

Interrupt-Driven I/O
Processor
issues an I/O The processor
command to a executes the data
module and transfer and then
then goes on to resumes its
do some other former
useful work processing

The I/O module will More efficient than

then interrupt the Programmed I/O but still
processor to request requires active
service when it is intervention of the
ready to exchange data processor to transfer
with the processor data between memory
and an I/O module
 Interrupt-Driven I/O Drawbacks

• Transfer rate is limited by the speed with

which the processor can test and service a
device
• The processor is tied up in managing an I/O
transfer

A number of instructions must be
executed for each I/O transfer

Direct Memory Access (DMA)

• Performed by a separate module on the

system bus or incorporated into an I/O
module
When the processor wishes to read or write data it issues
a command to the DMA module containing:
• Whether a read or write is requested
• The address of the I/O device involved
• The starting location in memory to read/write
• The number of words to be read/written
• Transfers the entire block of data directly to
and from memory without going through
the processor
• Processor is involved only at the beginning and end
of the transfer
• Processor executes more slowly during a transfer
when processor access to the bus is required
• More efficient than interrupt-driven or
programmed I/O

Symmetric Multiprocessors (SMP)

• A stand-alone computer system with the following
characteristics:
– All processors can perform the same functions
– The system is controlled by an integrated operating
system that provides interaction between processors
and their programs at the job, task, file, and data
element levels
 Symmetric Multiprocessors (SMP)
• A stand-alone computer system with the following
characteristics:
– Two or more similar processors of comparable
capability
– Processors share the same main memory and are
interconnected by a bus or other internal connection
scheme
– Processors share access to I/O devices

Performance Scaling
• A system with multiple • Vendors can offer a range of
processors will yield greater products with different price
performance if work can be and performance
done in parallel characteristics

Availability Incremental Growth

• The failure of a single • An additional processor can
processor does not halt the be added to enhance
machine performance
 Processor Processor Processor
L1 Cache L1 Cache L1 Cache

L2 Cache L2 Cache L2 Cache

System Bus

Main I/O
Memory I/O Adapter
Subsystem

I/O
Adapter

I/O
Adapter

Figure 1.19 Symmetric Multiprocessor Organization

Multicore Computer
• Also known as a chip multiprocessor
• Combines two or more processors (cores)
on a single piece of silicon (die)
• Each core consists of all of the components
of an independent processor
• In addition, multicore chips also include L2
cache and in some cases L3 cache