1.

Input device is

 Answer: a. Keyboard

2. RISC stands for

 Answer: a. Reduced Instruction set computer

3. 1 GB = _____ Bytes

 Answer: d. 1,000,000,000

4. RAM is

 Answer: a. Volatile memory

5. An address generated by CPU is generally referred as_______

 Answer: d. Logical Address

6. Which of the following is not a type of ROM

 Answer: c. EAROM

7. RAM can be:

 Answer: a. SRAM, DRAM

8. A_____ buffer can be used for fetch segment:

 Answer: c. FIFO (First In, First Out)

9. Name the parallel processing:

 Answer: d. All of the above (SIMD, MIMD, MISD, SISD)

10. Parallel processor is:

 Answer: a. Distributed architecture

11. The ___ stores intermediate data used during the execution of the instructions:

 Answer: Register

12. ALU performs micro operations for executing the:

 Answer: Arithmetic and logical operations

13. Register that holds the address for the stack is called:
  Answer: Stack pointer

14. The ____ points at the address of the next instruction in the program:

 Answer: Program counter

15. Memory refers to the ____ of a computer system.

 Answer: Storage

16. Parts of primary memory are ___ and ____.

 Answer: RAM (Random Access Memory) and ROM (Read-Only Memory)

17. EPROM stands for ______.

 Answer: Erasable Programmable Read-Only Memory.

18. Access time = _____ + _____.

 Answer: Seek Time + Latency (or Rotational Delay)

19. I/O Bus consists of ____, ____ and ____.

 Answer: Data Lines, Address Lines, and Control Lines.

20. In parallel MIMD systems, communication is essential for processing.

 Answer: Yes, in parallel MIMD (Multiple Instruction, Multiple Data) systems,

communication between processors is essential for coordinating tasks and processing
data efficiently.

Q21: Explain One-Address Instructions?

One-Address Instructions:

 Definition: A type of instruction format that uses a single address field.

 Structure: Consists of an opcode (specifying the operation) and one address (where
the operand is stored).
 Usage: Typically employs an accumulator as an implicit second operand.
 Example: ADD 1000 adds the value from memory address 1000 to the accumulator.
 Advantages: Simplifies instruction decoding and reduces hardware complexity.

Q22: Explain 1) Direct Address Mode, 2) Indirect Address Mode

1. Direct Address Mode:

  Definition: The address field directly specifies the location of the operand in
memory.
 Example: LOAD 2000 means load data from memory address 2000.
 Advantages: Provides fast access but limits the addressable memory range.

2. Indirect Address Mode:

 Definition: The address field specifies a memory location that contains the address of
the operand.
 Example: LOAD (2000) means load data from the address found at memory location
2000.
 Advantages: Allows greater flexibility in addressing and can access larger memory
space, but requires two memory accesses.

Q23: What are the steps followed by CPU when an interrupt occurs?

When an interrupt occurs, the CPU follows these steps:

1. Save Current State – The CPU saves the current execution state (registers, program
counter, etc.).
2. Disable Further Interrupts – It temporarily disables other interrupts to prevent
conflicts.
3. Identify the Interrupt – The CPU checks the interrupt type and its priority.
4. Fetch Interrupt Service Routine (ISR) Address – The CPU loads the address of the
corresponding ISR from the interrupt vector table.
5. Execute the ISR – The CPU runs the ISR to handle the interrupt.
6. Restore Saved State – Once the ISR is completed, the CPU restores the previously
saved state.
7. Resume Execution – The CPU resumes normal execution from where it left off.
8. Q24: Compare internal interrupts and external interrupts.

Q24: Compare internal interrupts and external interrupts.

Feature Internal Interrupts External Interrupts

Generated by internal CPU
Definition Generated by external hardware devices
conditions
Arithmetic overflow, division by Keyboard input, mouse clicks, network
Examples
zero signals
Synchronous (occur within the
Type Asynchronous (can occur at any time)
CPU)
Usage Handles errors and exceptions Signals the CPU for I/O operations
Initiation Triggered by the CPU itself Triggered by external devices
Impact on May alter the flow of execution Typically interrupts the CPU to handle
Execution directly an event

Q25: Short Note on 1) SRAM, 2) DRAM

1. SRAM (Static RAM)

  Definition: A type of volatile memory that retains data as long as power is supplied.
 Features:
 Faster access speed compared to DRAM.
 No need for periodic refresh cycles.
 Uses bistable latching circuitry to store data.
 Typical Use: Cache memory in CPUs and high-speed applications.
 Cost: More expensive than DRAM.

2. DRAM (Dynamic RAM)

 Definition: A type of volatile memory that stores each bit in a capacitor.

 Features:
 Requires periodic refreshing to maintain data due to charge leakage.
 Slower access speed compared to SRAM.
 Higher storage density compared to SRAM.
 Typical Use: Main system memory (RAM) in computers.
 Cost: Generally cheaper than SRAM.

Q26: Why Virtual Memory is Used in Computer Systems?

 Definition: A memory management technique that allows using disk storage as an

extension of RAM.
 Benefits:
 Increased Address Space: Enables running larger applications than physical RAM
alone can support.
 Process Isolation: Enhances security and stability by preventing one process from
interfering with another.
 Efficient Memory Use: Pages are loaded into memory only when needed (demand
paging).
 Mechanism:
 Utilizes a combination of hardware and software (e.g., page tables) to map virtual
addresses to physical memory addresses for effective management.

Q.27 What is memory mapping? Explain.

Memory mapping is the process of translating logical addresses used by a program

into physical addresses that the computer hardware actually uses. This translation
enables efficient access to data and instructions stored in memory. It plays a crucial
role in implementing virtual memory, allowing programs to use more memory than
physically available by mapping portions of memory to disk storage. It also enhances
memory protection by isolating different processes, ensuring they cannot interfere
with each other.

Q.29 What is the difference between static RAM and dynamic RAM?

 Storage Technique: SRAM uses flip-flops; DRAM uses capacitors.

 Speed: SRAM is faster as it doesn't need refreshing; DRAM is slower.
 Cost: SRAM is more expensive due to complex architecture; DRAM is cheaper.
 Power Consumption: SRAM consumes more power than DRAM.
 Density: DRAM can store more data in the same space compared to SRAM.
Q.30 What are the major functions of BIOS? The Basic Input/Output System (BIOS)
performs essential functions, including:

1. Power-On Self-Test (POST): Checks hardware components during boot-up.

2. Booting the Operating System: Loads the OS from disk into memory.
3. Hardware Initialization: Configures hardware settings for various devices.
4. Interface for Hardware Management: Provides a way for the operating system to
communicate with hardware.

Q.31 Write short note on synchronous and asynchronous data transfer.

Synchronous Data Transfer:

 Data is sent at regular intervals, synchronized with a shared clock signal between
sender and receiver.
 Ensures both parties operate in time, increasing transfer efficiency.
 Ideal for high-speed communication where large volumes of data need to be
transmitted quickly.
 Example: USB communication.

Asynchronous Data Transfer:

 Data is sent without a shared clock; it uses start and stop bits to indicate the beginning
and end of each byte.
 Allows for flexibility, as the sender and receiver do not need to be perfectly timed.
 Suitable for sporadic data transmission over longer distances.
 Example: RS-232 serial communication.

Q.32 Explain briefly interrupt priority encoder.

An interrupt priority encoder is a hardware component that manages multiple interrupt

requests from various devices in a computer system.

Key Points:

 Function: It determines which interrupt has the highest priority when multiple
interrupts occur simultaneously.
 Operation: The encoder generates a priority code corresponding to the highest-
priority interrupt, allowing the CPU to service it first.
 Importance: This ensures critical tasks are handled promptly while preventing lower-
priority interrupts from delaying the processing of more important ones, thus
maintaining system efficiency and stability.