Explain PSW of 8051.

PSW Definition: PSW stands for Program Status Word. It is an 8-bit register in the 8051 microcontroller that
holds various status flags indicating the current state of the processor.
Bits in PSW:
The PSW register consists of 8 bits, labeled as CY, AC, F0, RS1, RS0, OV, P, and SP.
Carry Flag (CY):
CY bit indicates if there is a carry or borrow in arithmetic and logical operations.
It's used in multi-byte arithmetic and shifting operations.
Auxiliary Carry Flag (AC):
AC bit is used for binary-coded decimal (BCD) arithmetic.
It indicates if there's a carry or borrow between bits 3 and 4 during an operation.
Register Bank Select (RS1 and RS0):
These two bits (RS1 and RS0) determine which register bank is currently selected.
The 8051 has four register banks, and these bits select one of them.
Overflow Flag (OV):
OV bit indicates if there is an overflow in signed arithmetic operations.
It's set when the result of a signed operation exceeds the capacity of the register.
Parity Flag (P):
P bit indicates the parity of the accumulator's content.
It's set if the number of set bits in the accumulator is even.
User-Defined Flag (F0):
F0 is a user-defined bit.
It can be used for any purpose by the programmer.
Stack Pointer (SP):
The SP bits indicate the current location of the stack pointer.
The stack pointer is used for managing subroutine calls and interrupts.
PSW in Decision Making:
Program flow decisions can be based on the status of various flags in the PSW, like the carry flag (CY) for
unsigned arithmetic or the overflow flag (OV) for signed arithmetic.
Explain internal RAM memory organization in 8051

The internal RAM (Random Access Memory) organization in the 8051 microcontroller is relatively
straightforward. Here's a simple explanation:
Overall Structure:
The 8051 microcontroller has 256 bytes of internal RAM.
This RAM is used for data storage during program execution.
Banking:
The RAM is divided into two main banks: Bank 0 and Bank 1.
Each bank consists of 128 bytes of memory.
Direct Addressing:
The RAM in the 8051 can be directly addressed using 8-bit addresses (0x00 to 0xFF).
The address space is linear, meaning each byte in the RAM has a unique address.
Special Function Registers (SFRs):
Some portions of the internal RAM are reserved for special function registers (SFRs).
These registers control various functions of the microcontroller, such as timers, ports, and
interrupt control.
Registers and Bit Addressable RAM:
The RAM of the 8051 is not only byte-addressable but also bit-addressable.
This means that each bit in the RAM can be accessed individually, which is useful for setting or
clearing specific flags or control bits.
Use in Program Execution:
The internal RAM is commonly used for storing variables, intermediate results of calculations,
and other data required during program execution.
Program code cannot be stored in RAM; it is typically stored in external memory (ROM or
Flash).
Stack Memory:
A portion of the RAM is reserved for use as stack memory.
The stack is used for storing return addresses and local variables during subroutine calls.
Usage Considerations:
Programmers need to manage RAM usage efficiently to avoid running out of memory.
Due to its limited size, it's essential to optimize variable usage and minimize unnecessary data
storage.
What are different types of buses in microprocessor based system? Discuss the role in th system in brief

In a microprocessor-based system, various types of buses facilitate communication between different

components. Here are the main types of buses and their roles in the system:
Address Bus:
The address bus carries addresses of memory locations or I/O ports.
It is unidirectional, meaning it only carries information from the microprocessor to the memory or I/O
devices.
The width of the address bus determines the maximum memory capacity that the microprocessor can
address.
Data Bus:
The data bus carries data between the microprocessor, memory, and I/O devices.
It is bidirectional, allowing data to be transferred both to and from the microprocessor.
The width of the data bus determines the maximum amount of data that can be transferred in a single
operation.
Control Bus:
The control bus carries control signals that coordinate the operation of various components in the system.
It includes signals such as read, write, interrupt, clock, and bus request/acknowledge signals.
These signals control the timing and sequencing of operations within the system, ensuring proper
communication and coordination between components.
System Bus:
The system bus is a collection of address, data, and control buses that connect the microprocessor to
memory and I/O devices.
It provides a pathway for data transfer and control signals between the microprocessor and other system
components.
The system bus architecture may vary depending on the specific microprocessor and system design.
Expansion Bus:
The expansion bus allows for the connection of additional devices or expansion cards to the
microprocessor-based system.
Common expansion buses include ISA (Industry Standard Architecture), PCI (Peripheral Component
Interconnect), and PCIe (PCI Express).
Expansion buses enable the integration of additional functionality, such as graphics cards, network
adapters, and storage controllers, into the system.
What is memory segmentation of 8086? Explain in brief

Memory segmentation in the Intel 8086 microprocessor is a memory management technique that divides
the memory address space into segments. Each segment is a continuous block of memory with a
maximum size of 64 KB (kilobytes). The 8086 uses a segmented memory model to address up to 1 MB
(megabyte) of memory.
Here's a brief explanation of memory segmentation in the 8086:
Segment and Offset:
Memory addresses in the 8086 are represented as a combination of a segment and an offset.
A segment is a 16-bit value that points to the base address of a memory segment.
An offset is also a 16-bit value that specifies the distance from the base address within the segment.
Segment Registers:
The 8086 has four 16-bit segment registers: CS (Code Segment), DS (Data Segment), SS (Stack
Segment), and ES (Extra Segment).
These segment registers hold the base addresses of different types of memory segments.
The CS register points to the segment containing the currently executing program's instructions.
The DS register typically points to the segment containing data used by the program.
The SS register points to the segment containing the program's stack.
The ES register is often used for additional data segments in certain instructions.
Address Calculation:
To calculate a physical memory address, the 8086 combines the segment and offset values.
The physical address is obtained by multiplying the segment value by 16 and adding the offset value.
This calculation results in a 20-bit physical address, allowing access to up to 1 MB of memory.
Segmentation vs. Paging:
Memory segmentation in the 8086 is a simpler form of memory management compared to paging used in
modern systems.
Segmentation provides a flat address space within each segment but requires the programmer to manage
segment registers manually.
Paging, on the other hand, divides memory into fixed-size pages and uses a page table for address
translation, providing more flexibility and memory protection.
If CS = 2000H, DS = 4000H, SS = 6000H and draw memory map of 8086 CPU with starting end physical
address of each segment
CS (Code Segment): CS = 2000H
Starting Physical Address: 20000H (CS * 16)
Ending Physical Address: 2FFFFH (CS * 16 + 0xFFFF)
DS (Data Segment): DS = 4000H
Starting Physical Address: 40000H (DS * 16)
Ending Physical Address: 4FFFFH (DS * 16 + 0xFFFF)
SS (Stack Segment): SS = 6000H
Starting Physical Address: 60000H (SS * 16)
Ending Physical Address: 6FFFFH (SS * 16 + 0xFFFF)

Here's the memory map representation:

|------------------|

| Code Segment | <- Physical Address Range: 20000H to 2FFFFH

|------------------|

| |

| |

|------------------|

| Data Segment | <- Physical Address Range: 40000H to 4FFFFH

|------------------|

| |

| |

|------------------|

| Stack Segment | <- Physical Address Range: 60000H to 6FFFFH

|------------------|
2. A. Explain hardware architecture of 8051

The hardware architecture of the 8051 microcontroller comprises various components that work together
to execute instructions and perform tasks. Here's an overview of the key elements of the 8051 hardware
architecture:
Central Processing Unit (CPU):
The CPU is the core of the 8051 microcontroller.
It consists of an ALU (Arithmetic Logic Unit), accumulator, general-purpose registers, and various
control and status registers.
The CPU fetches instructions from memory, decodes them, and executes them sequentially.
Memory:
The 8051 microcontroller has separate address spaces for program memory (ROM or Flash) and data
memory (RAM).
Program memory stores the user's program code, while data memory stores variables, intermediate
results, and stack space.
The Harvard architecture separates program and data memory, providing faster access and enabling
simultaneous instruction fetch and data access.
Registers:
The 8051 includes several types of registers:
Accumulator (A): Used for arithmetic and logical operations.
B Register: Supports some arithmetic operations.
Data Pointer Registers (DPTR): Used for indirect addressing.
Program Counter (PC): Holds the address of the next instruction to be fetched.
Stack Pointer (SP): Points to the top of the stack in RAM.
Various special function registers (SFRs) control peripheral devices and system functions.
Interrupts:
The 8051 supports multiple interrupt sources, including external hardware interrupts and internal software
interrupts.
Interrupts can be prioritized and individually enabled or disabled using control registers.
When an interrupt occurs, the CPU suspends the current task, saves its context, and jumps to the interrupt
service routine (ISR) to handle the interrupt.
Timers/Counters:
The 8051 typically includes one or more built-in timers/counters.
These timers/counters can be used for various timing and counting applications, such as generating
delays, measuring time intervals, or counting external events.
They have control registers for configuring their operating modes and behavior.
I/O Ports:
The 8051 features multiple I/O ports for interfacing with external devices.
Each port typically consists of multiple pins that can be configured as inputs or outputs.
Special function registers control the direction and status of individual port pins.
Serial Communication:
Many 8051 variants include built-in UART (Universal Asynchronous Receiver/Transmitter) modules for
serial communication.
UART modules support asynchronous serial communication protocols like RS-232 and are commonly
used for interfacing with peripheral devices or communication with other microcontrollers.

2. B. Write a program to generate square wave of 1KHZ and 60% duty cycle at pin P0.1. assume 8051
operating at 11.0592Mhz. Use timer() in model

ORG 0H ; Start of the program

MOV TMOD, #01H ; Timer 0, mode 1 (16-bit mode)

HERE:
MOV TL0, #0F2H ; Load TL0 with 0F2H, the low byte
MOV TH0, #0FFH ; Load TH0 with FFH, the high byte
SETB TR0 ; Start Timer 0
WAIT_LOOP:
JNB TF0, WAIT_LOOP ; Wait until Timer 0 overflows
CLR TR0 ; Stop Timer 0
CLR TF0 ; Clear Timer 0 overflow flag
CPL P0.1 ; Toggle P0.1
ACALL DELAY ; Call delay subroutine
SJMP HERE ; Repeat the loop
DELAY:
MOV R2, #107 ; Load R2 with 107 (adjust based on clock frequency)
DELAY_LOOP:
DJNZ R2, DELAY_LOOP ; Delay loop
RET
END
3. A. Write an assembly lang prog for 8051 to transfer message "ECS SE '' serially at the baud rate of
9600 in mode 1. Assume 8051 operates at frequency 11.0592 MHz
#include <reg51.h>
void SerTx(unsigned char);
void main(void){

TMOD=0x20; //use Timer 1, mode 2

TH1=0xFD; //9600 baud rate
SCON=0x50;
TR1=1; //start timer
while (1) {

SerTx(‘E’);
SerTx(‘C’);
SerTx(‘S’);
SerTx(‘ ’);
SerTx(‘S’);
SerTx(‘E’);

}
void SerTx(unsigned char x){

SBUF=x; //place value in buffer

while (TI==0); //wait until transmitted
TI=0;

}
3.A. Design a 32kb RAM using 16bit chip

3. B. Describe the features of programmable interrupt controller 8259. What is master slave config of
8259
The 8259 Programmable Interrupt Controller (PIC) is a widely used interrupt controller chip in
microprocessor-based systems. It is designed to manage and prioritize interrupt requests from various
peripheral devices in the system. Here are the key features of the 8259 PIC:

1. Multiple Interrupt Inputs:

- The 8259 PIC supports up to eight interrupt inputs, labeled IR0 through IR7.
- Each interrupt input can be connected to a different peripheral device in the system.

2. Priority Encoding:
- The 8259 PIC provides priority encoding for interrupt requests.
- Higher priority interrupts are serviced before lower priority interrupts.
- Priority levels are determined based on the connection of interrupt lines to the IR inputs.

3. Interrupt Masking:
- Each interrupt input can be individually masked or unmasked to enable or disable interrupt requests
from specific devices.
- Masking an interrupt input prevents the corresponding device from generating interrupts.

4. Cascade Mode:
- The 8259 PIC supports cascade mode, allowing multiple 8259 chips to be connected together to
handle more than eight interrupt sources.
 - In cascade mode, one 8259 chip acts as the master, while the others act as slaves.

5. Interrupt Acknowledge and Vectoring:

- When an interrupt occurs, the CPU sends an interrupt acknowledge signal to the 8259 PIC.
- The 8259 PIC responds by providing an interrupt vector, which is the memory address of the interrupt
service routine (ISR) corresponding to the triggered interrupt.

6. End of Interrupt (EOI) Handling:

- After servicing an interrupt, the CPU sends an End of Interrupt (EOI) signal to the 8259 PIC.
- This signal informs the PIC that the interrupt has been processed and allows the PIC to clear its
interrupt request flag for that interrupt.

7. Special Mask Mode:

- The 8259 PIC supports a special mask mode, which allows certain interrupts to be masked
automatically after being serviced.
- This feature is useful for handling certain types of interrupts that do not need to be serviced
continuously.

The master-slave configuration of the 8259 PIC involves connecting multiple 8259 chips together to
handle more than eight interrupt sources. In this configuration:

- One 8259 chip is designated as the master, and the others are designated as slaves.
- The master 8259 is connected to the CPU's interrupt request line.
- The slave 8259 chips are cascaded together, with the output of one chip connected to the input of the
next.
- The master 8259 prioritizes interrupts from both its own inputs and the cascaded slave chips.
- If an interrupt occurs on a slave 8259, it signals the master 8259, which then requests an interrupt from
the CPU.

4. A. Interface LCD to 8051 and write assembly language program to display message “Year 2024” on it
4. B. Design a 8086 based system with 32k RAM (2 chips of 16K)
5. A. Interface HEX Keypad to 8051 and write assembly language program to read the key pressed and
send it to one of the ports
ORG 0H ; Starting address of the program

; Define LCD control signals

RS equ P2.0 ; Register Select (RS) pin of LCD
RW equ P2.1 ; Read/Write (RW) pin of LCD
E equ P2.2 ; Enable (E) pin of LCD

; Define LCD data port

LCD_DATA equ P1 ; Data port for LCD

; Define LCD commands

LCD_CLEAR_DISPLAY equ 01H ; Clear display command
LCD_RETURN_HOME equ 02H ; Return home command
LCD_ENTRY_MODE equ 06H ; Entry mode set command
LCD_DISPLAY_CTRL equ 0CH ; Display control command
LCD_CURSOR_SHIFT equ 10H ; Cursor or display shift command
LCD_FUNCTION_SET equ 38H ; Function set command (8-bit, 2-line display)

START:
; Initialize LCD
CALL INIT_LCD
 ; Display message "Year 2024"
MOV A, #'Y'
CALL SEND_CHAR
MOV A, #'e'
CALL SEND_CHAR
MOV A, #'a'
CALL SEND_CHAR
MOV A, #'r'
CALL SEND_CHAR
MOV A, ' '
CALL SEND_CHAR
MOV A, #'2'
CALL SEND_CHAR
MOV A, #'0'
CALL SEND_CHAR
MOV A, #'2'
CALL SEND_CHAR
MOV A, #'4'
CALL SEND_CHAR

; End of program
SJMP $

; Subroutine to initialize LCD

INIT_LCD:
; Wait for LCD to power up (wait at least 15ms after VDD reaches 4.5V)
; Your delay subroutine implementation here

; Initialize LCD function (8-bit, 2-line display)

MOV A, LCD_FUNCTION_SET
CALL SEND_COMMAND

; Set entry mode (increment cursor, no display shift)

MOV A, LCD_ENTRY_MODE
CALL SEND_COMMAND

; Clear display
MOV A, LCD_CLEAR_DISPLAY
CALL SEND_COMMAND

; Display ON, cursor OFF, blink OFF

MOV A, LCD_DISPLAY_CTRL
CALL SEND_COMMAND
 RET

; Subroutine to send command to LCD

SEND_COMMAND:
CLR RS ; RS = 0 for command
CLR RW ; RW = 0 for write mode
SETB E ; Enable pulse
NOP ; Small delay
CLR E ; Disable pulse
; Your delay subroutine implementation here
RET

; Subroutine to send character to LCD

SEND_CHAR:
SETB RS ; RS = 1 for data
CLR RW ; RW = 0 for write mode
SETB E ; Enable pulse
MOV LCD_DATA, A ; Send character to data port
NOP ; Small delay
CLR E ; Disable pulse
; Your delay subroutine implementation here
RET

END

5. B. Design an 8086 based system with 34 K RAM (2 chips of 16 bit each) . Draw the memory map of
the system designed.

6.A. Explain stepper motor interfacing with 8051

Interfacing a stepper motor with an 8051 microcontroller involves controlling the stepper motor's motion
by sending specific sequences of control signals to its driver circuitry. Stepper motors are
electromechanical devices that convert digital pulses into precise mechanical motion. Here's a general
overview of how to interface a stepper motor with an 8051 microcontroller:
Stepper Motor Basics:
Stepper motors consist of multiple coils (phases) arranged in a specific pattern.
By energizing these coils in a particular sequence, the stepper motor rotates in discrete steps.
The number of steps per revolution and the step angle depend on the motor's construction and the driving
technique used.
Driver Circuitry:
Stepper motors require driver circuitry to control the current flow through the motor coils.
Common driver types include H-bridge drivers, Darlington transistor arrays, and dedicated stepper motor
driver ICs.
The driver circuitry receives control signals from the microcontroller and regulates the current flow to the
motor coils accordingly.
Interfacing Steps:
Connect the stepper motor to the driver circuitry as per the motor and driver datasheets.
Connect the driver circuitry to the appropriate pins of the 8051 microcontroller.
Typically, at least four output pins are required to control a bipolar stepper motor (two coils), while
unipolar stepper motors may require more.
Ensure proper power supply connections for the stepper motor and driver circuitry.
Control Sequence:
Stepper motors can be controlled using various driving techniques, such as full-step, half-step, or
microstepping.
In each step, specific coils are energized to produce motion.
The microcontroller sends control signals to the driver circuitry to generate the desired motion sequence.
The control sequence depends on the motor's type (bipolar or unipolar) and the driving technique chosen.
Programming the Microcontroller:
Write a program for the 8051 microcontroller to generate the control signals required to drive the stepper
motor.
Define the control sequence for the stepper motor based on the chosen driving technique.
Implement the program logic to generate the required control signals and send them to the driver circuitry.
Testing and Debugging:
Test the stepper motor interfacing setup by running the program on the 8051 microcontroller.
Verify that the motor rotates in the expected direction and speed.
Debug any issues related to wiring, power supply, or program logic.

6. B. Interface 8255 with 8086 and write an assembly language program to blink led connected to bit 6
port C of 8255.