102401CS

Roll No………………………..

Course Code: 102401CS

Examination: APRIL-MAY 2023
Course: COMPUTER ORGANIZATION AND ARCHITECTURE

Time Allowed: 3 Hours Maximum Marks: 100

Minimum Marks: 35
Note: Attempt all questions. Part (A) of each question is compulsory
and carries 4 marks; attempt any two parts from part (B), (C) and (D)
carrying 8 marks each.
Q1 A Write down the various steps required for the 4
execution of instruction ADD R3, R1.
B Explain the working of Hardwired control and micro 8
programmed control unit
C Explain 16-bit common bus architecture of basic 8
computer.
D An instruction is stored at location 300 with its address 8
field at location 301. The address field has value 400,
a processor register R1 contain the number 200.
Evaluate effective address if the addressing modes of
the instruction are
(i) direct (ii) immediate (iii) relative (iv) register
indirect.
Q2 A Define Guard and Rounding Bits 4
B Multiply the following pair of signed 2’s complement 8
numbers using the Booth algorithm. Assume that A is
the multiplicand and B is the multiplier.
A = (- 8 ) and B = ( - 14 )
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 102401CS

C Divide 8 by 3 using restoring division method. 8

D Explain IEEE floating point number representation 8
and its operation for 16 bits / 32 bits.
Q3 A Explain memory hierarchy in brief. 4
B Explain working of associative memory with block 8
diagram and derive the expression for match logic.
C Explain virtual memory in details. 8
D Explain multimodule memory and memory 8
interleaving.
Q4 A Explain any 2 peripheral devices of computer in brief. 4
B Define priority interrupt. Explain daisy chaining 8
priority interrupt with a block diagram
C What is direct memory access technique? Explain the 8
function of DMA controller with diagram.
D What is address space? Explain isolated vs memory 8
mapped I/O.
Q5 A Difference between RISC and CISC Processors 4
B What do you understand by parallel processing? 8
Describe Flynn’s classification of parallel processing.
C Consider the execution of the program of 15000 8
instructions a linear pipeline processor with a clock
rate of 25 MHz. Assume that the instruction pipeline
has 5 stages and that one instruction is issued per clock
cycle. Calculate (i) speed up factor (ii) efficiency (iii)
throughput
D Explain Vector processing and Array processing 8

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 102401CS

Roll No………………………..

Course Code: 102401CS

Examination: APRIL-MAY 2023
Course: COMPUTER ORGANIZATION AND ARCHITECTURE

Time Allowed: 3 Hours Maximum Marks: 100

Minimum Marks: 35
Note: Attempt all questions. Part (A) of each question is compulsory
and carries 4 marks; attempt any two parts from part (B), (C) and (D)
carrying 8 marks each.
Q1 A Write down the various steps required for the 4
execution of instruction ADD R3, R1.
B Explain the working of Hardwired control and micro 8
programmed control unit
C Explain 16-bit common bus architecture of basic 8
computer.
D An instruction is stored at location 300 with its address 8
field at location 301. The address field has value 400,
a processor register R1 contain the number 200.
Evaluate effective address if the addressing modes of
the instruction are
(i) direct (ii) immediate (iii) relative (iv) register
indirect.
Q2 A Define Guard and Rounding Bits 4
B Multiply the following pair of signed 2’s complement 8
numbers using the Booth algorithm. Assume that A is
the multiplicand and B is the multiplier.
A = (- 8 ) and B = ( - 14 )
Page 1 of 2
 102401CS

C Divide 8 by 3 using restoring division method. 8

D Explain IEEE floating point number representation 8
and its operation for 16 bits / 32 bits.
Q3 A Explain memory hierarchy in brief. 4
B Explain working of associative memory with block 8
diagram and derive the expression for match logic.
C Explain virtual memory in details. 8
D Explain multimodule memory and memory 8
interleaving.
Q4 A Explain any 2 peripheral devices of computer in brief. 4
B Define priority interrupt. Explain daisy chaining 8
priority interrupt with a block diagram
C What is direct memory access technique? Explain the 8
function of DMA controller with diagram.
D What is address space? Explain isolated vs memory 8
mapped I/O.
Q5 A Difference between RISC and CISC Processors 4
B What do you understand by parallel processing? 8
Describe Flynn’s classification of parallel processing.
C Consider the execution of the program of 15000 8
instructions a linear pipeline processor with a clock
rate of 25 MHz. Assume that the instruction pipeline
has 5 stages and that one instruction is issued per clock
cycle. Calculate (i) speed up factor (ii) efficiency (iii)
throughput
D Explain Vector processing and Array processing 8

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