Notice: The teacher is not allowed to explain any more

Dec. 12th, 2018

Head of ECC

HCMC University of Technology and ANSWER OF SEMESTER-1, 2018-2019

Education Course: Digital Systems
Faculty for High Quality Training Course code: DIGI330163E
Number of pages: 01 pages Duration: 90
minutes.
Only used one A4-handwriting paper.
Question 1 (2.5 points)
Given an asynchronous counter with 4 JK-FFs.
a) Design and draw one asynchronous counter with the MOD-11, in which its
inputs and outputs need to be noted clearly.

Figure 1.1
With an asynchronous counter using the negative clock pulse, the low active CLEARs
and PRESETs in FF-JKs are set to be 1 for operation respond to CKs, Mod-11 has
Q1Q2Q3Q4=1101 which are connected to a NAND with 3 inputs as shown in Fig. 1.1
b) Explain the operation of this MOD-11 counter.
In this asynchronous counter with the negative clock pulse, Mod-11 has
Q1Q2Q3Q4=1101. Therefore, three outputs Q1, Q2, Q4 of the FF-JK with 1s will
be connected to the inputs of a NAND gate as shown in Figure 1. Thus when the
circuit counts from zero to this state 11, it means that the FF-JK inputs Q1, Q2, Q4
simultaneously are one and the NAND will be zero. It means that the CLR is zero
and all outputs are zero. Thus, the inputs of the NAND are zero and its output is
one, this makes the circuit counts again from zero.
 c) Draw the output waveforms of the MOD-11 counter.

Figure 1.2
After 11 CKs, the circuit is reset so that all outputs of JK-FFs are zero and the
circuit counts again as shown in Fig. 1.2
d) Re-design the logic circuit for the CLEAR function in the MOD-11 counter to
use the NAND gates with 2 inputs only.

Figure 1.3
A CLEAR circuit is designed to use 3 NAND gates with 2 inputs as shown in
Fig.
1.3.
Question 2 (3 points)
Inputs Outputs

I0 I1 I2 I3 Y1 Y0
x x x 0 1 1
x x 0 1 1 0
x 0 1 1 0 1
0 1 1 1 0 0
Figure 2
Given the following table:
a) Write the output expressions and draw a logic circuit with the output
expressions using logic gates.
 Y1  I3  I2.I3  I3  I2
Y0  I3 I1.I2.I3  I3 I1.I2
b) What is the name of this logic circuit? Why?
This is the encoder, in which 4 inputs with the active, zero and 2 outputs. It
means that there is an input code, there will be a corresponding to output as
shown in
Figure 3
c) Draw the Pin diagram of this circuit

Figure 3
Question 3 (2.5 points)
Given the ROM memory as shown in Figure 4
a) Determine the memory capacity corresponding to the addresses
from the 9th register to the 25th register in byte.
The memory capacity is calculated as follows:
B=25-9+1=17 bytes, corresponding to 17 registers due to its
data bus is 8-bit
b) Describe functions, inputs and outputs of ROM in Figure.
This is a memory IC with Read Only, in which there are 6
addresses (from A0 to A5), 8 data lines (8-bit data) and CE
(Chip Enable, low active) enables the operating IC with the
low level. Figure 4
th
c) Determine the address at the 60 register in Hex
In this case, it means that we calculate from the register 0 to the register 59.
Thus the 59th register address is (A5A4A3A2A1A0=111011=3BH)
Question 4: (2 points)
Given a Digital to Analog converter with 5 digital inputs and 1 analog output, its
maximum voltage is 15.5 V.
a) Determine the K resolution.
The resolution: K=Vmax/Digital input=15.5/31=0.5 V, in which the digital
input of 5-bit is 111112=31
b) Assume that the digital input is 11001, determine the analog output?
We have:
V=K* Digital input=0.5*25=12.5 V
 Notice: The teacher is not allowed to explain any more

Dec. 12th, 2018

Head of ECC
HCMC UNIVERSITY OF
TECHNOLOGY AND EDUCATION
Faculty for High Quality Training Program name:_ ECET_

ANSWERS OF FINAL EXAMINATION

SEMESTER 2 – ACADEMIC YEAR 2018-2019
Course name: Digital Systems
Course ID: DIGI330163
Exam code: 1; Number of pages: 1 Duration: 90 minutes.
 Open-Two pages of A4.
Question 1: (3 mark/10)
Design a synchronous counter with the states from 000 to 111
a. Show the truth table with Present states, Next states and J-K states (1 mark)

b. Determine the J-K expressions using K-map (1 mark)

c. Draw the logic circuit with JK-FFs and the expressions above (1 mark)
J0 = K0 = 1 J1 = K1 = Q0 J2 = K2 = Q0Q1
Question 2: (1.5 mark/10) Choose one of the following questions
a. Assume that there is one asynchronous counter with the MOD-12, how many FFs can be used in
this counter and which the outputs of the FFs (Q 1, Q2, Q3, Q4) will be connected to the Clear input
through one logic circuit.
- One asynchronous counter with the MOD-12 need 4 FFs used in the counter. - The Truth
table:

- Q4, Q3 will be connected to the Clear input through NAND gate.

b. Design an encoder with 42, in which draw the circuit, the truth table, write the expressions of
the encoder and explain its operation.
Let 4 to 2 Encoder has four inputs I 3, I2, I1 & I0 and two outputs O1 & O0. The block diagram of 4 to
2 Encoder is shown in the following figure. (0.25 mark)
At any time, only one of these 4 inputs can be ‘1’ in order to get the respective binary code at the
output. The Truth table of 4 to 2 encoder is shown below. (0.25 mark)

Inputs Outputs

I3 I2 I1 I0 O1 O0

0 0 0 1 0 0

0 0 1 0 0 1

0 1 0 0 1 0

1 0 0 0 1 1
From Truth table, we can write the Boolean functions for each output as (0.5 mark)
O1=I3+I2O1=I3+I2
O0=I3+I1O0=I3+I1
We can implement the above two Boolean functions by using two input OR gates. The circuit
diagram of 4 to 2 encoder is shown in the following figure. (0.5 mark)

The above circuit diagram contains two OR gates. These OR gates encode the four inputs with two
bits.
c. Design a de-multiplexer with 14, in which draw the circuit, the truth table, write the
expressions and explain its operation.
- Draw the circuit (0.5 mark)
 - The truth table (0.5 mark)

- Explain its operation (0.5 mark)

I S1 S0

O0
O1

O2

O3

Question 3: (3 mark/10)
Given the memory IC as shown in Figure 1
 a. Determine the memory capacity in byte (1 mark)
Memory capacity in bit: B = 215 = 32768 bits memory capacity in byte
C = 32768/8 = 4096 bytes = 4 Kbytes.
b. Determine the memory capacity in Hex from the memory register with the address
(0DE0H) to the memory register with the address (0EF0H) (1 mark)
0EF0H = 3824 in Decimal
0DE0H = 3552 in Decimal M = 3824 -
3552 +1 = 273 bytes
c. Show the difference between RAM and ROM (1 mark)

Question 4: (2.5 mark/10)

a. Design a binary full adder, in which draw the circuit, the truth table, determine the equation and
explain the operation of the full adder. (1.5 mark)
- The truth table (0.5 mark)
- Determine the equation (0.5 mark)
Logical Expression for SUM:
SUM = A’ B’ C-IN + A’ B C-IN’ + A B’ C-IN’ + A B C-IN
= C-IN (A’ B’ + A B) + C-IN’ (A’ B + A B’)
= C-IN XOR (A XOR B)
Logical Expression for C-OUT:
C-Out = A’ B C-IN + A B’ C-IN + A B C-IN’ + A B C-IN
= A B + B C-IN + A C-IN
Therefore C-OUT = AB + C-IN (A EX – OR B)
- Draw the circuit (0.5 mark)

b. Subtract two binary numbers corresponding to the following decimal numbers of (9-7)
(1 mark)
910 = 10012
710 = 01112
910 – 710 = 10012 - 01112 = 00102

HCM, / / 2019
Approved by program chair
(signed and named)
HCMC University of Technology and ANSWER SHEET OF SEMESTER-2, 2017-2018
Education Course: Digital Systems
Faculty for High Quality Training Course code: DIGI330163E
Number of pages: 02 pages Duration: 90 minutes.
Only used one A4-handwriting paper. Question
1: (1.5 points)
a) According to the truth table of FF-D, the output Q=D, when having the clock pulse

(0.5p)
Clock pulse is negative edge and the iuput D is low at this time, so the output Q is
low, repeat for next pulses, we have the whole output Q
b) When D=A, the output Q=D and when Q=1, the output X of the NOR gate is high;
when Q=0, the output X of the NOR gate is “Clock Pulse”, but inverted as the below
waveforms.

(1p)
Figure 1 Question
2: (2.5 points)
Design a synchronous counter with the state as shown in Figure 2 and Flip-Flop_JK in
Figure 1 having the start state 001, in which two undesired states 000 and 101 have the next
state of 001.
001  010  011  100  110  111

Figure 2
+ Design the table for counter states
 Qn Inputs of FF
Qn+1
Q3 Q2 Q1 Q3’ Q2’ Q1’ J3 K3 J2 K2 J1 K1
0 0 0 0 0 1 0X 0X 1X
0 0 1 0 1 0 0X 1X X1
0 1 0 0 1 1 0X X0 1X
0 1 1 1 0 0 1X X1 X1
1 0 0 1 1 0 X0 1X 0X
1 0 1 0 0 1 X1 0X X0
1 1 0 1 1 1 X0 X0 1X
1 1 1 0 0 1 X1 X1 X0

(0.5P)
+ Determine the expressions: (0,75đ)
Question 3: (2.5 points)
Choose one of the following questions:
a) Design a binary adder circuit with Full Adder, in which draw the circuit, the truth
table and explain them.

where
A: input digits
B: Input digits S:
Sum out
C0 : Carry out
CI : Carry in
(0.5p) (0.5p)
 (1p
) (0.5p)

b) Design a decoder circuit with 2 inputs and 4 outputs, in which draw the circuit using
logic gates, the truth table, write expressions and explain them.
A,B: Inputs
G: Enable input with low active
Y0, Y1, Y2, Y3: Output with low active
(0.5p)

(0.5p)

(1p) (0.5p)

c) Design a multiplexer circuit with 4à1, in which draw the circuit, the truth table,
write expressions and explain them.
 (1.5p)

(0.5p)
YB.A.D0 B.A.D1 B.A.D2 B.A.D
3
(0.5p)

Question 4: (2 points)
Given the ROM memory as shown in Figure 3.
a) Determine the memory capacity in byte.
6 bit of address (A0 to A5) and 8 bit of data, so 26=64byte of the memory capacity.
(0.75p)
b) Determine the memory capacity in bit from the 2 nd memory register to the 10th
memory register.
The total register number=(10-2)+1=9 (0.5p) and
each register has 8 bit of data=1byte.
Therefore, the memory capacity in bit is 9*8=72 bit. (0.75p)
 Figure 3 (0.5p)

Question 5: (1.5 points)

Given the oscillator using IC555 having T = 4ms, C = 0,47µF and the total resistor
(R1+R2) = 8,16kΩ. Determine the resistor values.

Calculate the resistor values.

We have T = 4ms and
Ton  0.7(R1+R2)C and Toff  0.7R2C
T= Toff + Ton 0.7(R1+2R2)C  0.47. 10-6. 0.7(R1+2R2)  4. 10-3 (0.5p) or
R1+2R2  12.16 kΩ (1)
We have R1+R2=8.16 kΩ (2);
From (1) and (2), we have R2  4 kΩ and R1  4.16kΩ; (0.5p)

June 19th, 2018

Head of ECC