計算機組織

Computer Organization

Syllabus

Kun-Chih (Jimmy) Chen 陳坤志

[email protected]
Institute of Electronics,
National Yang Ming Chiao Tung University
 Fact Sheet
❖ Lecture
❖ ED B26 Mon. 10:10am – 12:00pm; Wed. 9am – 9:50am
❖ Instructor
❖ Kun-Chih Chen (ED 404) [email protected]
❖ Office Hour
❖ Tue. 9am – 12pm, ED 404
❖ TA Information
❖ 潘柏宇 (Glenn) [email protected]
陳柏淳 (Brian) [email protected]
黃炫喻 (Andrews) [email protected]
陳祖喬 (joan) [email protected]
顏彥臣 (Nelson) [email protected]
❖ TAs' Lab: ED 428
❖ Class web page (video, handout, announcement)
❖ E3數位教學平台 (E3@NYCU)

❖ Prerequisites (but not necessary)

❖ Computer Organization ❖ Logic design
❖ Computer programming (C or C++)
❖ Grading
❖ Homework 40% (HW#1:10%, HW#2: 10%, HW#3: 10%, HW#4: 10%)
❖ Final project 20%
❖ Exam 60% (including midterm and final exam)

P2
 Textbook and References

❖ Textbook
❖ John L. Hennessy and David A. Patterson, Computer
Organization and Design: The Hardware/Software
Interface RISV-V ed., Morgan Kaufmann Publishers, 2018.
(ISBN: 978-0-12-812275-4)

❖ Reference (Not required to purchase)

❖ John L. Hennessy and David A. Patterson, Computer
Organization and Design: The Hardware/Software
Interface 5th ed., Elsevier, 2014. (ISBN: 978-986-6052-67-5)

❖ John L. Hennessy and David A. Patterson, Computer

Architecture : A Quantitative Approach 5th ed., Morgan
Kaufmann Publishers, 2017. (ISBN: 978-0-12-811905-1)

P3
 Schedule (1/2)
Week Date Lecture Handout Submit
1 9/2, 9/4 Syllabus
2 9/9, 9/11 Computing Platform & Evaluation
Metrics
3 9/16, 9/18 Instruction Set Architecture (I) HW#1
(virtual)
4 9/23, 9/25 Instruction Set Architecture (II)
(virtual)
5 9/30, 10/2 Arithmetic Designs (I) HW#1

6 10/7, 10/9 • Arithmetic Designs (II) HW#2

• Single-Cycle Datapath/Control (I)
7 10/14, 10/16 Single-Cycle Datapath/Control (II)
8 10/21, 10/23 Midterm HW#2
9 10/28, 10/30 Pipelined Datapath (I)

P4
 Schedule (2/2)

Week Date Lecture Handout Submit

10 11/4, 11/6 Pipelined Datapath (II)
(virtual)
11 11/11, 11/13 Memory Hierarchy (I) HW#3
Final project
12 11/27, 11/29 Memory Hierarchy (II)
13 11/18, 11/20 Virtual Memory (I) HW#4 HW#3
(virtual)
14 11/25, 11/27 Virtual Memory (II)
15 12/2, 12/4 Multiprocessor HW#4
16 12/9, 12/11 Final Exam
17 12/20 N/A Final project

P5
 Class Policy
❖ Lecture
❖ Do not hesitate to ask questions in office hour
❖ The videos are only allowed to keep it to yourself
❖ Homework/Project
❖ Homework: Submit the hardcopy report in class
❖ Project: Submit the softcopy report and your final program to TA (zip file)
➢ File Naming Rule: (Student ID #)_(Student Name) ex. D12345_王小明
❖ Late homework/project 1/3 off each week, no late homework after 3 weeks
❖ Discussion with classmates is encouraged!
❖ Cheating = zero grade for both students!
❖ Midterm/Final Exam
❖ Close book
❖ Bag isolation
❖ Seat assignment
❖ Cheating = zero grade for both students!

P6
 Why RISC-V
Computer Organization and Design: The Hardware/Software
Interface, RISC-V Edition
David Patterson and John Hennessy, 2018

Andy Yu-Guang Chen 7

P7
 Current Computer Organization
Computer architecture, HW/SW, systems, bioinformatics, security

Hybrid Main Memory

Heterogeneous Persistent Memory/Storage

Processors and
Accelerators

Graphics and Vision Processing

Build fundamentally better architectures

P8
 Four Key Current Directions

❖ Fundamentally Secure/Reliable/Safe Architectures

❖ Fundamentally Energy-Efficient Architectures

❖ Memory-centric (Data-centric) Architectures

❖ Fundamentally Low-Latency and Predictable Architectures

❖ Architectures for AI/ML, Genomics, Medicine, Health

P9
 The Transformation Hierarchy

Problem
Algorithm
Program/Language
System Software
Computer Architecture SW/HW Interface Computer Architecture
(expanded view) (narrow view)
Micro-architecture
Logic
Devices
Electrons

P10
 Axiom

❖ To achieve the highest energy efficiency and performance:

we must take the expanded view

of computer architecture

Problem
Algorithm
Program/Language
System Software Co-design across the hierarchy:
SW/HW Interface Algorithms to devices
Micro-architecture
Logic Specialize as much as possible
Devices within the design goals
Electrons

P11
 Current Research Mission & Major Topics
Build fundamentally better architectures
❖ Data-centric arch. for low energy & high perf.
Problem ❖ Proc. in Mem/DRAM, NVM, unified mem/storage
Algorithm ❖ Low-latency & predictable architectures
Program/Language ❖ Low-latency, low-energy yet low-cost memory
System Software ❖ QoS-aware and predictable memory systems
SW/HW Interface
❖ Fundamentally secure/reliable/safe arch.
Micro-architecture
❖ Tolerating all bit flips; patchable HW; secure mem
Logic
Devices ❖ Architectures for ML/AI/Genomics/Graph/Med
Electrons ❖ Algorithm/arch./logic co-design; full heterogeneity
Broad research ❖ Data-driven and data-aware architectures
spanning apps, systems, logic
with architecture at the center ❖ ML/AI-driven architectural controllers and design
❖ Expressive memory and expressive systems

P12
 What is computer architecture?
❖ is the science and art of designing computing platforms (hardware,
interface, system SW, and programming model)

❖ to achieve a set of design goals

❖ E.g., highest performance on earth on workloads X, Y, Z
❖ E.g., longest battery life at a form factor that fits in your pocket with cost <
$$$ USD
❖ E.g., best average performance across all known workloads at the best
performance/cost ratio
❖…

❖ Designing a supercomputer is different from designing a smartphone → But,

many fundamental principles are similar

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Different Platforms, Different Goals

Source: http://www.sia-online.org (semiconductor industry association)

P14
Different Platforms, Different Goals

Source: https://iq.intel.com/5-awesome-uses-for-drone-technology/
P15
Different Platforms, Different Goals

Source: http://datacentervoice.com/wp-content/uploads/2015/10/data-center.jpg
P16
 Different Platforms, Different Goals

Jouppi et al., “In-Datacenter Performance Analysis of a Tensor Processing Unit”, ISCA 2017.

P17
 Different Platforms, Different Goals

❖ ML accelerator: 260 mm2, 6 billion transistors, 600 GFLOPS GPU, 12

ARM 2.2 GHz CPUs.
❖ Two redundant chips for better safety.

https://youtu.be/Ucp0TTmvqOE?t=4236
P18
 Why Study Computer Organization?
❖ Enable better systems: make computers faster, cheaper, smaller, more
reliable, …
❖ By exploiting advances and changes in underlying technology/circuits

❖ Enable new applications

❖ Life-like 3D visualization 20 years ago? Virtual reality?
❖ Self-driving cars?
❖ Personalized genomics? Personalized medicine?

❖ Enable better solutions to problems

❖ Software innovation is built on trends and changes in computer architecture
➢ > 50% performance improvement per year has enabled this innovation

❖ Understand why computers work the way they do

P19
 Introduction of Final Projects
❖ Ripes Simulator
❖ Ripes is a visual computer architecture simulator and assembly code editor built
for the RISC-V instruction set architecture.
➢ (40%) L1 cache → More memory hierarchy level?
➢ (40%) Set association policy in the cache → Different set association policy?

P20
 計算機組織
Computer Organization

RISC-V: The Open Era of Computing

Source: Calista Redmond, RISC-V: The Open Era of

Computing, RISC-V (https://riscv.org/about/)
 RISC-V is the free and open
Instruction Set Architecture…

Welcome to the … Driven through open

collaboration
open era of … Enabling freedom of design

computing. across all domains and

industries

… Cementing the strategic

foundation of semiconductors

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 Disruptive Technology

Barriers Legacy ISA RISC-V ISA

1500+ base instructions 47 base instructions
Complexity
Incremental ISA Modular ISA
Design freedom $$$ – Limited Free – Unlimited

License and Royalty fees $$$ Free

Design ecosystem Moderate Growing rapidly. Numerous

extensions, open and
proprietary cores

Software ecosystem Extensive Growing rapidly

P23
Industry innovation on RISC-V

P24
 Unconstrained Opportunity

RISC-V Business Model

Collaboration
partners
Development

Supply chain
Barriers removed
• Design risk
Expanded Expanded
• Cost of entry markets geographies
• Partner limitations
• Supply chain

P25
 By 2025, 40% of
application-specific
integrated circuits
(ASICs) will be designed
by OEMs, up from
around 30% today.

Custom ICs Based on RISC-V Will Enable

Cost-Effective IoT Product
Differentiation

Gartner, June 2020

Source: Gartner
Rapid RISC-V growth led by industrial

62.4 billion RISC-V CPU cores

by 2025
Semico Research predicts
the market will consume 62.4
billion RISC-V CPU cores by
2025, a 146.2% CAGR 2018-
2025. The industrial sector to
lead with 16.7 billion cores.

Source: Semico Research Corp

P27
Nearly a quarter of designs incorporate RISC-V

Wilson Research
Group/Siemens found that
23% of ASIC and FPGA
projects incorporated RISC-
V in at least one processor in a
double-blind 2020 study.

P28
 RISC-V IP, SW, and Tools build momentum

❖ The total market for RISC-V IP and Software is expected to grow to

$1.07 billion by 2025 at a CAGR of 54.1%

P29
 美國社會學家關心的問題

❖ How do Taiwanese engineering students view their social role (how

can they contribute to society or to the development of Taiwan)?

❖ What do you think the (engineering) students think about political

issues? or geopolitical issues?

台灣工程領域(尤其半導體相關)學生是否真有意識到他們
的社會責任以及在地緣政治上的影響力與責任？

P30