Archi: definitions

Term Definition/explanation

System Any collection of hardware, software and firmware

Metrics Criteria used to evaluate the performance of the system

component

Workloads The requests made by the users of the system. Raw materials
for the computations or treatment.

CPU Hardware section that is used to execute instructions.

Modern CPUs are divided into sub-units with clear
responsibilities.

ALU Part of the CPU responsible for performing arithmetic

operations.

RAM Type of memory that is volatile i.e. gets empty when the
computer is shut down. The elements are stored as bits and
can be accessed by their physical address in the RAM.

Control unit Sub-unit of the CPU that provides the ALU with the
elements to do the computations.

IP (instruction pointer) Stores the address in the code of the following instruction to
execute. This information is stored in a register.

Registers Type of memory that is very close to the CPU. It is even

faster than a cache but their capacity is very limited.

instruction set Available instructions of a CPU

ISA Instruction set + number of registers available

Binary compatibility A program compiled on a CPU with a given ISA will be

compatible with any CPU with the same ISA— no matter
the internal implementation of the CPU.

CISC (complex instruction set A computer architecture in which single instructions can
computer) execute several low-level operations.

Example:
load from memory, arithmetic operations, …
 Cache Memory component that is located between the CPU and
the RAM. It is faster than the RAM and is used to store data
that are likely to be requested in the near future. It allows the
CPU to lose less cycles when it needs data from RAM.

Working set The set of data that have been used the past time interval ∆

Temporal locality A data that has been used in the near past is very likely to be
used in the near future

Spacial locality A data that is close to a data (in memory) that has recently
been used is very likely to be used in the near future

Inclusive cache management Data that is in the L1 cache is also in L2 cache. If an entry is
removed from L1, it is still in L2.

Exclusive cache management Data is only present in one cache at a time. Is an entry is
removed from L1, it is either completely removed or moved
to L2.

CPI Cycle per instruction (how many cycle an instruction takes

to be executed).

DMA Used to avoid moving one byte at a time for large data
movement. Bypasses CPU to transfer data directly between
an I/O device and memory.

Dirty flag A bit indicating if the data in a page has changed. This allows
us to write the page to disk at a later point in time.

Factor Variable that affects the performance outcome of a system.

Levels (of a factor) The values that a factor can assume

Hardware prefetching Memory blocks are fetched before they are needed. They
anticipately are put in the cache to reduce the number of
cache misses.

RISC A computer architecture designed to simplify the individual

instructions given to the computer to accomplish tasks.

IOMMU Maps device-visible virtual adresses to physical memory

adresses.

RING-1 The level of access rights the host kernel has.

RDMA: Used to access memory of another host by bypassing the

CPU (used in datacenters)
 MMU Translates the virtual adresses in the CPU to physical
addresses in the memory.

Page Block of physical addresses to which a virtual address is

mapped

Present flag Indicates whether the page is present in RAM. Accessing a

page that in not present in the RAM (P=0) causes a page
fault.

Paging Allocating more memory than there is physical memory in

the computer. It uses the virtual memory and the swap
in/out mechanisms.

Access flag Indicates whether a page has recently been accessed by the
CPU.

TLB Cache for page table entries. It stores #frame + flags

U flag Indicates whether a page can be accessed by a used or only in

privilege mode.

SISD Single instruction single data

SIMD Single instruction multiple data

SMT Simultaneous multi-threading

Latency Time to complete an instruction

Throughput Number of instructions that can be issued per cycles

GPU Processors oriented to 3D graphics tasks. They are highly

multithreaded (they use SIMT)

Knee capacity Capacity befire getting a lower gain

Nominal capacity The throughput in ideal conditions

Clustering Divide workloads in groups that can be represented by a

single benchmark

Response variable outcome

Primary factors Factors whose effects need to be quantified

Secondary factors Factors whose effects can be negligated

Experimet/test Execution of the setup for a single level of each factor

Replication/Run Repetition of all or some experiments

Design The number of experiments the factor level and number

replications for each experiment

ALU The sub-unit of a CPU that does the calculations

RAID Redundant Array of Independent Disks.

RAID 0 Put blocks alternatively on disk A and disk B so double the

bandwidth and double the danger (cannot recover if one disk
fails)

RAID 1 One disk is a copy of the other. If you loose one disk, you
have the other as a backup.

RAID 4 3 disks, the last one for parity (A XOR B = C), You can read a
file from A and B at the same time : double bandwidth.
Writing is more complicated : you have to write the “XOR”
on C (Fine for large write). For small writes, we have to
rewrite the block in C (Inefficient as C becomes a
bottleneck).

RAID 5 like RAID 4 but the parity is rotating between A, B and C.

RAID 6 double parity (using reed solomon)

RAID 10 Combination of RAID 0 and RAID 1.