Question One

(a) In memory system design, enumerate the design goals and considerations to achieve an
efficient memory system. (State at least three (3) points).

Answer:
To achieve an efficient memory system, the following design goals and considerations are
important:

​ 1.​ Speed – Memory should provide fast access to data to match processor speeds
and avoid bottlenecks.

​ 2.​ Capacity – The memory hierarchy should balance storage size to optimize cost
and performance.

​ 3.​ Cost-effectiveness – Memory design should optimize price per bit while
maintaining efficiency.

(b) Explain fault-tolerant computing and fault-tolerant systems.

Answer:

​ •​ Fault-tolerant computing refers to a system’s ability to continue operating

correctly despite the presence of faults or errors.

​ •​ Fault-tolerant systems are designed to detect, isolate, and recover from hardware
or software failures, ensuring minimal disruption in operations.

(c) Describe three (3) techniques for masking failure in fault-tolerant systems.

Answer:

​ 1.​ Redundancy – Using multiple components (hardware/software) to provide

backup in case of failure.

​ 2.​ Error Detection and Correction – Implementing parity bits, Hamming codes, and
ECC to identify and fix errors.

​ 3.​ Checkpointing and Rollback Recovery – Saving system states at intervals to

restore operations if failure occurs.

(d) Differentiate between RISC and CISC. Give at least two (2) points.

Answer:

Feature RISC (Reduced Instruction CISC (Complex Instruction

Set Computing) Set Computing)
 Instruction Set Uses a small, optimized set Uses a large, complex set of
of instructions instructions

Execution Speed Executes instructions faster Takes multiple cycles for

with single-cycle execution execution

(e) Define the following terms:

(i) Hit rate – The percentage of memory accesses found in cache memory, improving overall
performance.

(ii) Miss rate – The percentage of memory accesses not found in cache memory, leading to
slower access from the main memory.

Question Two

(a) Describe how semiconductor memories are packaged and state one (1) key design issue in
the packaging of memories.

Answer:

Semiconductor memories are packaged using integrated circuits (ICs) with different
configurations such as DIP (Dual Inline Package), SOIC (Small Outline IC), and BGA (Ball Grid
Array).

Key design issue: Heat dissipation – High-density memory chips generate heat, which must be
managed to prevent failure.

(b) Describe the errors that occur in semiconductor memories and state one (1) method for
detecting or correcting the errors.

Answer:

Types of errors:

​ 1.​ Soft errors – Temporary faults caused by environmental factors like radiation.

​ 2.​ Hard errors – Permanent defects due to manufacturing flaws or physical damage.

Error detection method: Parity bits – A single bit added to data to detect single-bit errors.

(c) Explain the term interleaved memory.

Answer:

Interleaved memory is a technique that divides memory into multiple banks that can be
accessed simultaneously, improving speed by reducing wait times between memory accesses.

Question Three

(a) Explain the reason why mapping is needed between the main memory and cache memory of
a computer system. State one (1) technique used for carrying out mapping.

Answer:

Mapping is needed to determine how cache memory stores and retrieves data from main
memory efficiently, reducing access time.

Mapping technique: Direct Mapping – Each block of main memory maps to a specific location in
cache.

(b) Cache memory using single-level and multi-level cache organization and describe the cache
operation.

Answer:

​ •​ Single-level cache (L1 Cache) – Directly integrated with the CPU for fast data
access.

​ •​ Multi-level cache (L1, L2, L3) – Uses multiple layers, with L1 being fastest and L3
being slower but larger.

Cache Operation:

​ 1.​ CPU requests data.

​ 2.​ Cache checks for data (cache hit/miss).

​ 3.​ If found (hit), data is sent to CPU; if not (miss), data is fetched from RAM.

Question Four

(a) With respect to Disk I/O transfer, explain the following terms:

(i) Seek time – The time required for the disk’s read/write head to move to the correct track.

(ii) Rotational latency – The delay before the desired data sector rotates under the read/write
head.

(iii) Transfer time – The time taken to move data from the disk to memory.
(b) Explain the term RAID, state its different levels, and differentiate between stripping, parity,
and mirroring in RAID.

Answer:

RAID (Redundant Array of Independent Disks) is a data storage technology that improves
performance, redundancy, or both by combining multiple disk drives.

RAID Levels:

​ •​ RAID 0 (Striping) – Splits data across disks for high speed, but no redundancy.

​ •​ RAID 1 (Mirroring) – Copies data onto multiple disks for redundancy.

​ •​ RAID 5 (Parity) – Distributes data and parity for fault tolerance.

Differences:

​ •​ Striping – Divides data across multiple disks to improve speed.

​ •​ Parity – Stores calculated data to reconstruct lost information.

​ •​ Mirroring – Copies exact data on another disk for redundancy.

Question Five

(a) Enumerate the main components of the central processing unit. Describe the control unit
and state clearly its function.

Answer:

Main components of CPU:

​ 1.​ Arithmetic Logic Unit (ALU) – Performs arithmetic and logic operations.

​ 2.​ Control Unit (CU) – Directs operations within the CPU.

​ 3.​ Registers – Store temporary data and instructions.

Control Unit Function:

​ •​ Fetches, decodes, and executes instructions by controlling data flow in the CPU.

(b) Explain the two main approaches for implementing the control unit.

Answer:
​ 1.​ Hardwired Control – Uses fixed logic circuits to execute instructions quickly but
lacks flexibility.

​ 2.​ Microprogrammed Control – Uses stored microinstructions to implement control

logic, making it more adaptable.

Question Six

(a) Describe asynchronous input/output synchronization. State clearly the problem faced in this
I/O synchronization and the possible solution to the problem.

Answer:

Asynchronous I/O synchronization allows the CPU to continue executing while waiting for I/O
operations.

Problem:

​ •​ The CPU may not know when the I/O operation is complete, leading to
inefficiency.

Solution:

​ •​ Use Interrupts or Polling to notify the CPU when I/O is done.

(b) Enumerate five (5) input and output (I/O) module functions.

Answer:

​ 1.​ Data transfer between peripherals and memory

​ 2.​ Data buffering to manage speed differences

​ 3.​ Error detection and correction

​ 4.​ Control and status reporting

​ 5.​ Device addressing and command execution